From 347212085bc5b1f1b94946c2e5cacb42bdc4a4c8 Mon Sep 17 00:00:00 2001 From: Pawel Dembicki Date: Mon, 18 Mar 2024 14:33:54 +0100 Subject: [PATCH] layerscape: kernel: refresh 6.6 patches Taken refreshed version from Layerscape 6.6 tree: 302-arm64-dts-ls1012a-update-with-ppfe-support.patch 304-arm64-dts-ls1012a-rdb-workaround-by-updating-qspi-fl.patch 400-LF-20-3-mtd-spi-nor-Use-1-bit-mode-of-spansion-s25fs.patch 701-staging-add-fsl_ppfe-driver.patch 702-phy-Add-2.5G-SGMII-interface-mode.patch 704-net-phylink-treat-PHY_INTERFACE_MODE_2500SGMII-in-ph.patch Removed: 704-net-phylink-treat-PHY_INTERFACE_MODE_2500SGMII-in-ph.patch (meld into 702) Signed-off-by: Pawel Dembicki --- ...dts-ls1012a-update-with-ppfe-support.patch | 196 ++++++------------ ...a-frdm-workaround-by-updating-qspi-f.patch | 4 +- ...a-rdb-workaround-by-updating-qspi-fl.patch | 2 +- ...nor-Use-1-bit-mode-of-spansion-s25fs.patch | 4 +- .../701-staging-add-fsl_ppfe-driver.patch | 117 +++++------ ...02-phy-Add-2.5G-SGMII-interface-mode.patch | 20 +- ...t-PHY_INTERFACE_MODE_2500SGMII-in-ph.patch | 42 ---- 7 files changed, 141 insertions(+), 244 deletions(-) delete mode 100644 target/linux/layerscape/patches-6.6/704-net-phylink-treat-PHY_INTERFACE_MODE_2500SGMII-in-ph.patch diff --git a/target/linux/layerscape/patches-6.6/302-arm64-dts-ls1012a-update-with-ppfe-support.patch b/target/linux/layerscape/patches-6.6/302-arm64-dts-ls1012a-update-with-ppfe-support.patch index 70e624a2a9..bd69aa042d 100644 --- a/target/linux/layerscape/patches-6.6/302-arm64-dts-ls1012a-update-with-ppfe-support.patch +++ b/target/linux/layerscape/patches-6.6/302-arm64-dts-ls1012a-update-with-ppfe-support.patch @@ -1,19 +1,20 @@ -From 1bb35ff4ce33e65601c8d9c736be52e4aabd6252 Mon Sep 17 00:00:00 2001 -From: Calvin Johnson -Date: Sat, 16 Sep 2017 14:20:23 +0530 -Subject: [PATCH] arm64: dts: freescale: ls1012a: update with ppfe support +From 008465a02bf29b366ca7a56dba48ad3a85417ba2 Mon Sep 17 00:00:00 2001 +From: Li Yang +Date: Thu, 18 Nov 2021 21:46:21 -0600 +Subject: [PATCH] arm64: dts: ls1012a: add ppfe support to boards -Update ls1012a dtsi and platform dts files with support for ppfe. +Update ls1012a dtsi and platform dts files with +support for ppfe. Signed-off-by: Calvin Johnson Signed-off-by: Anjaneyulu Jagarlmudi +Signed-off-by: Li Yang --- - .../boot/dts/freescale/fsl-ls1012a-frdm.dts | 43 +++++++++++++++++ - .../boot/dts/freescale/fsl-ls1012a-frwy.dts | 43 +++++++++++++++++ - .../boot/dts/freescale/fsl-ls1012a-qds.dts | 43 +++++++++++++++++ - .../boot/dts/freescale/fsl-ls1012a-rdb.dts | 47 +++++++++++++++++++ + .../boot/dts/freescale/fsl-ls1012a-frdm.dts | 44 +++++++++++++++++++ + .../boot/dts/freescale/fsl-ls1012a-qds.dts | 43 ++++++++++++++++++ + .../boot/dts/freescale/fsl-ls1012a-rdb.dts | 40 +++++++++++++++++ .../arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 29 ++++++++++++ - 5 files changed, 205 insertions(+) + 4 files changed, 156 insertions(+) --- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts @@ -29,7 +30,7 @@ Signed-off-by: Anjaneyulu Jagarlmudi sys_mclk: clock-mclk { compatible = "fixed-clock"; #clock-cells = <0>; -@@ -95,6 +100,44 @@ +@@ -110,6 +115,45 @@ }; }; @@ -43,15 +44,9 @@ Signed-off-by: Anjaneyulu Jagarlmudi + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; /* GEM_ID */ -+ fsl,gemac-bus-id = <0x0>; /* BUS_ID */ -+ fsl,gemac-phy-id = <0x2>; /* PHY_ID */ + fsl,mdio-mux-val = <0x0>; + phy-mode = "sgmii"; -+ fsl,pfe-phy-if-flags = <0x0>; -+ -+ mdio@0 { -+ reg = <0x1>; /* enabled/disabled */ -+ }; ++ phy-handle = <&sgmii_phy1>; + }; + + pfe_mac1: ethernet@1 { @@ -59,99 +54,43 @@ Signed-off-by: Anjaneyulu Jagarlmudi + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1>; /* GEM_ID */ -+ fsl,gemac-bus-id = <0x1>; /* BUS_ID */ -+ fsl,gemac-phy-id = <0x1>; /* PHY_ID */ + fsl,mdio-mux-val = <0x0>; + phy-mode = "sgmii"; -+ fsl,pfe-phy-if-flags = <0x0>; -+ -+ mdio@0 { -+ reg = <0x0>; /* enabled/disabled */ -+ }; ++ phy-handle = <&sgmii_phy2>; + }; -+}; + - &qspi { - status = "okay"; - ---- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts -+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts -@@ -14,6 +14,11 @@ - / { - model = "LS1012A FRWY Board"; - compatible = "fsl,ls1012a-frwy", "fsl,ls1012a"; -+ -+ aliases { -+ ethernet0 = &pfe_mac0; -+ ethernet1 = &pfe_mac1; -+ }; - }; - - &duart0 { -@@ -28,6 +33,44 @@ - status = "okay"; - }; - -+&pfe { -+ status = "okay"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ pfe_mac0: ethernet@0 { -+ compatible = "fsl,pfe-gemac-port"; ++ mdio@0 { + #address-cells = <1>; + #size-cells = <0>; -+ reg = <0x0>; /* GEM_ID */ -+ fsl,gemac-bus-id = <0x0>; /* BUS_ID */ -+ fsl,gemac-phy-id = <0x2>; /* PHY_ID */ -+ fsl,mdio-mux-val = <0x0>; -+ phy-mode = "sgmii"; -+ fsl,pfe-phy-if-flags = <0x0>; + -+ mdio@0 { -+ reg = <0x1>; /* enabled/disabled */ ++ sgmii_phy1: ethernet-phy@2 { ++ reg = <0x2>; + }; -+ }; + -+ pfe_mac1: ethernet@1 { -+ compatible = "fsl,pfe-gemac-port"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x1>; /* GEM_ID */ -+ fsl,gemac-bus-id = <0x1>; /* BUS_ID */ -+ fsl,gemac-phy-id = <0x1>; /* PHY_ID */ -+ fsl,mdio-mux-val = <0x0>; -+ phy-mode = "sgmii"; -+ fsl,pfe-phy-if-flags = <0x0>; -+ -+ mdio@0 { -+ reg = <0x0>; /* enabled/disabled */ ++ sgmii_phy2: ethernet-phy@1 { ++ reg = <0x1>; + }; + }; +}; + - &qspi { + &sai2 { status = "okay"; - + }; --- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts -@@ -18,6 +18,11 @@ +@@ -16,6 +16,8 @@ + aliases { + mmc0 = &esdhc0; mmc1 = &esdhc1; - }; - -+ aliases { + ethernet0 = &pfe_mac0; + ethernet1 = &pfe_mac1; -+ }; -+ + }; + sys_mclk: clock-mclk { - compatible = "fixed-clock"; - #clock-cells = <0>; -@@ -132,6 +137,44 @@ - }; +@@ -148,6 +150,47 @@ }; }; -+ + +&pfe { + status = "okay"; + #address-cells = <1>; @@ -162,15 +101,9 @@ Signed-off-by: Anjaneyulu Jagarlmudi + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; /* GEM_ID */ -+ fsl,gemac-bus-id = <0x0>; /* BUS_ID */ -+ fsl,gemac-phy-id = <0x1>; /* PHY_ID */ + fsl,mdio-mux-val = <0x2>; + phy-mode = "sgmii-2500"; -+ fsl,pfe-phy-if-flags = <0x0>; -+ -+ mdio@0 { -+ reg = <0x1>; /* enabled/disabled */ -+ }; ++ phy-handle = <&sgmii_phy1>; + }; + + pfe_mac1: ethernet@1 { @@ -178,35 +111,46 @@ Signed-off-by: Anjaneyulu Jagarlmudi + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1>; /* GEM_ID */ -+ fsl,gemac-bus-id = <0x1>; /* BUS_ID */ -+ fsl,gemac-phy-id = <0x2>; /* PHY_ID */ + fsl,mdio-mux-val = <0x3>; + phy-mode = "sgmii-2500"; -+ fsl,pfe-phy-if-flags = <0x0>; ++ phy-handle = <&sgmii_phy2>; ++ }; ++ ++ mdio@0 { ++ #address-cells = <1>; ++ #size-cells = <0>; + -+ mdio@0 { -+ reg = <0x0>; /* enabled/disabled */ ++ sgmii_phy1: ethernet-phy@1 { ++ compatible = "ethernet-phy-ieee802.3-c45"; ++ reg = <0x1>; ++ }; ++ ++ sgmii_phy2: ethernet-phy@2 { ++ compatible = "ethernet-phy-ieee802.3-c45"; ++ reg = <0x2>; + }; + }; +}; - - &qspi { ++ + &sai2 { status = "okay"; + }; --- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts -@@ -16,6 +16,8 @@ - - aliases { +@@ -18,6 +18,8 @@ serial0 = &duart0; -+ ethernet0 = &pfe_mac0; -+ ethernet1 = &pfe_mac1; mmc0 = &esdhc0; mmc1 = &esdhc1; - }; -@@ -86,6 +88,44 @@ ++ ethernet0 = &pfe_mac0; ++ ethernet1 = &pfe_mac1; }; }; +@@ -104,3 +106,41 @@ + &sata { + status = "okay"; + }; ++ +&pfe { + status = "okay"; + #address-cells = <1>; @@ -217,15 +161,9 @@ Signed-off-by: Anjaneyulu Jagarlmudi + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; /* GEM_ID */ -+ fsl,gemac-bus-id = <0x0>; /* BUS_ID */ -+ fsl,gemac-phy-id = <0x2>; /* PHY_ID */ + fsl,mdio-mux-val = <0x0>; + phy-mode = "sgmii"; -+ fsl,pfe-phy-if-flags = <0x0>; -+ -+ mdio@0 { -+ reg = <0x1>; /* enabled/disabled */ -+ }; ++ phy-handle = <&sgmii_phy>; + }; + + pfe_mac1: ethernet@1 { @@ -233,21 +171,23 @@ Signed-off-by: Anjaneyulu Jagarlmudi + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1>; /* GEM_ID */ -+ fsl,gemac-bus-id = < 0x1 >; /* BUS_ID */ -+ fsl,gemac-phy-id = < 0x1 >; /* PHY_ID */ + fsl,mdio-mux-val = <0x0>; -+ phy-mode = "rgmii-txid"; -+ fsl,pfe-phy-if-flags = <0x0>; ++ phy-mode = "rgmii-id"; ++ phy-handle = <&rgmii_phy>; ++ }; ++ mdio@0 { ++ #address-cells = <1>; ++ #size-cells = <0>; + -+ mdio@0 { -+ reg = <0x0>; /* enabled/disabled */ ++ sgmii_phy: ethernet-phy@2 { ++ reg = <0x2>; ++ }; ++ ++ rgmii_phy: ethernet-phy@1 { ++ reg = <0x1>; + }; + }; +}; -+ - &qspi { - status = "okay"; - --- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi @@ -568,6 +568,35 @@ @@ -264,7 +204,7 @@ Signed-off-by: Anjaneyulu Jagarlmudi + }; + }; + -+ pfe: pfe@04000000 { ++ pfe: pfe@4000000 { + compatible = "fsl,pfe"; + reg = <0x0 0x04000000 0x0 0xc00000>, /* AXI 16M */ + <0x0 0x83400000 0x0 0xc00000>; /* PFE DDR 12M */ diff --git a/target/linux/layerscape/patches-6.6/303-arm64-dts-ls1012a-frdm-workaround-by-updating-qspi-f.patch b/target/linux/layerscape/patches-6.6/303-arm64-dts-ls1012a-frdm-workaround-by-updating-qspi-f.patch index 5d19cb92dc..f42859b7ac 100644 --- a/target/linux/layerscape/patches-6.6/303-arm64-dts-ls1012a-frdm-workaround-by-updating-qspi-f.patch +++ b/target/linux/layerscape/patches-6.6/303-arm64-dts-ls1012a-frdm-workaround-by-updating-qspi-f.patch @@ -15,7 +15,7 @@ Signed-off-by: Pawel Dembicki --- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts -@@ -148,8 +148,8 @@ +@@ -110,8 +110,8 @@ spi-max-frequency = <50000000>; m25p,fast-read; reg = <0>; @@ -28,7 +28,7 @@ Signed-off-by: Pawel Dembicki --- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts -@@ -186,8 +186,8 @@ +@@ -145,8 +145,8 @@ spi-max-frequency = <50000000>; m25p,fast-read; reg = <0>; diff --git a/target/linux/layerscape/patches-6.6/304-arm64-dts-ls1012a-rdb-workaround-by-updating-qspi-fl.patch b/target/linux/layerscape/patches-6.6/304-arm64-dts-ls1012a-rdb-workaround-by-updating-qspi-fl.patch index 53cfd193b7..fd1dff747b 100644 --- a/target/linux/layerscape/patches-6.6/304-arm64-dts-ls1012a-rdb-workaround-by-updating-qspi-fl.patch +++ b/target/linux/layerscape/patches-6.6/304-arm64-dts-ls1012a-rdb-workaround-by-updating-qspi-fl.patch @@ -16,7 +16,7 @@ Signed-off-by: Kuldeep Singh --- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts -@@ -136,8 +136,8 @@ +@@ -98,8 +98,8 @@ spi-max-frequency = <50000000>; m25p,fast-read; reg = <0>; diff --git a/target/linux/layerscape/patches-6.6/400-LF-20-3-mtd-spi-nor-Use-1-bit-mode-of-spansion-s25fs.patch b/target/linux/layerscape/patches-6.6/400-LF-20-3-mtd-spi-nor-Use-1-bit-mode-of-spansion-s25fs.patch index b06c0f8133..b85053eba9 100644 --- a/target/linux/layerscape/patches-6.6/400-LF-20-3-mtd-spi-nor-Use-1-bit-mode-of-spansion-s25fs.patch +++ b/target/linux/layerscape/patches-6.6/400-LF-20-3-mtd-spi-nor-Use-1-bit-mode-of-spansion-s25fs.patch @@ -1,4 +1,4 @@ -From 20b1193c8c1d81a8d44ae36e579f70e6fbab45b9 Mon Sep 17 00:00:00 2001 +From bd3fa0b0ed51dd6a6564c01d37b36ff475f87ed4 Mon Sep 17 00:00:00 2001 From: Han Xu Date: Tue, 14 Apr 2020 11:58:44 -0500 Subject: [PATCH] LF-20-3 mtd: spi-nor: Use 1 bit mode of spansion(s25fs512s) @@ -15,7 +15,7 @@ Signed-off-by: Kuldeep Singh --- a/drivers/mtd/spi-nor/spansion.c +++ b/drivers/mtd/spi-nor/spansion.c -@@ -398,8 +398,8 @@ static const struct flash_info spansion_ +@@ -798,8 +798,8 @@ static const struct flash_info spansion_ MFR_FLAGS(USE_CLSR) }, { "s25fs512s", INFO6(0x010220, 0x4d0081, 256 * 1024, 256) diff --git a/target/linux/layerscape/patches-6.6/701-staging-add-fsl_ppfe-driver.patch b/target/linux/layerscape/patches-6.6/701-staging-add-fsl_ppfe-driver.patch index a52ac6201f..764d29f10d 100644 --- a/target/linux/layerscape/patches-6.6/701-staging-add-fsl_ppfe-driver.patch +++ b/target/linux/layerscape/patches-6.6/701-staging-add-fsl_ppfe-driver.patch @@ -1,4 +1,4 @@ -From 4bb50554937246443767e89d32e54df7a12396ca Mon Sep 17 00:00:00 2001 +From 9ee016f90af0bbcac576af881f1760ee9d9e38e0 Mon Sep 17 00:00:00 2001 From: Calvin Johnson Date: Sat, 16 Sep 2017 07:05:49 +0530 Subject: [PATCH] staging: add fsl_ppfe driver @@ -6,10 +6,8 @@ MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit -This is squash of all commits with ppfe driver taken from NXP 6.1 tree: -https://github.com/nxp-qoriq/linux/tree/lf-6.1.y - -List of original commits: +This is squash of all commits with ppfe driver taken from NXP 6.6 tree: +https://github.com/nxp-qoriq/linux/tree/lf-6.6.y net: fsl_ppfe: dts binding for ppfe @@ -577,7 +575,38 @@ staging: fsl_ppfe: Addressed build warnings Signed-off-by: Chaitanya Sakinam -Signed-off-by: Pawel Dembicki +staging: fsl_ppfe: Remove C45 check and related code in driver + +The MDIO core will not pass a C45 request via the C22 API call any +more. So, removed the code. The old way of C45 muxed addresses is +removed from the upstream kernel after clear seperation of C45 and +C22. +Upstream kernel commit details for reference: +99d5fe9c7f3d net: mdio: Remove support for building C45 muxed addresses + +Signed-off-by: Chaitanya Sakinam + +staging: fsl_ppfe: update class_create() usage + +Cope with API change: +1aaba11da9aa ("driver core: class: remove module * from class_create()") + +Signed-off-by: Krishna Chaitanya Sakinam + +LF-10777-2 staging: fsl_ppfe: remove unused pfe_eth_mdio_write_addr + +Fix the following build warning: +drivers/staging/fsl_ppfe/pfe_eth.c:887:12: warning: ‘pfe_eth_mdio_write_addr’ defined but not used [-Wunused-function] + 887 | static int pfe_eth_mdio_write_addr(struct mii_bus *bus, int mii_id, + +The only user of this API is MII_ADDR_C45 checking logic which +was removed since the commit 9d95b13bd084 ("staging: fsl_ppfe: Remove +C45 check and related code in driver"). So this API should be removed +together as no users anymore. + +Fixes: 9d95b13bd084 ("staging: fsl_ppfe: Remove C45 check and related code in driver") +Reviewed-by: Jason Liu +Signed-off-by: Dong Aisheng --- .../devicetree/bindings/net/fsl_ppfe/pfe.txt | 199 ++ MAINTAINERS | 8 + @@ -602,7 +631,7 @@ Signed-off-by: Pawel Dembicki drivers/staging/fsl_ppfe/pfe_ctrl.h | 100 + drivers/staging/fsl_ppfe/pfe_debugfs.c | 99 + drivers/staging/fsl_ppfe/pfe_debugfs.h | 13 + - drivers/staging/fsl_ppfe/pfe_eth.c | 2588 +++++++++++++++++ + drivers/staging/fsl_ppfe/pfe_eth.c | 2550 +++++++++++++++++ drivers/staging/fsl_ppfe/pfe_eth.h | 175 ++ drivers/staging/fsl_ppfe/pfe_firmware.c | 398 +++ drivers/staging/fsl_ppfe/pfe_firmware.h | 21 + @@ -619,7 +648,7 @@ Signed-off-by: Pawel Dembicki drivers/staging/fsl_ppfe/pfe_perfmon.h | 26 + drivers/staging/fsl_ppfe/pfe_sysfs.c | 840 ++++++ drivers/staging/fsl_ppfe/pfe_sysfs.h | 17 + - 40 files changed, 11015 insertions(+) + 40 files changed, 10977 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/fsl_ppfe/pfe.txt create mode 100644 drivers/staging/fsl_ppfe/Kconfig create mode 100644 drivers/staging/fsl_ppfe/Makefile @@ -862,7 +891,7 @@ Signed-off-by: Pawel Dembicki +}; --- a/MAINTAINERS +++ b/MAINTAINERS -@@ -8255,6 +8255,14 @@ F: drivers/ptp/ptp_qoriq.c +@@ -8359,6 +8359,14 @@ F: drivers/ptp/ptp_qoriq.c F: drivers/ptp/ptp_qoriq_debugfs.c F: include/linux/fsl/ptp_qoriq.h @@ -879,7 +908,7 @@ Signed-off-by: Pawel Dembicki L: linux-spi@vger.kernel.org --- a/drivers/staging/Kconfig +++ b/drivers/staging/Kconfig -@@ -80,4 +80,6 @@ source "drivers/staging/qlge/Kconfig" +@@ -78,4 +78,6 @@ source "drivers/staging/qlge/Kconfig" source "drivers/staging/vme_user/Kconfig" @@ -888,7 +917,7 @@ Signed-off-by: Pawel Dembicki endif # STAGING --- a/drivers/staging/Makefile +++ b/drivers/staging/Makefile -@@ -29,3 +29,4 @@ obj-$(CONFIG_PI433) += pi433/ +@@ -28,3 +28,4 @@ obj-$(CONFIG_PI433) += pi433/ obj-$(CONFIG_XIL_AXIS_FIFO) += axis-fifo/ obj-$(CONFIG_FIELDBUS_DEV) += fieldbus/ obj-$(CONFIG_QLGE) += qlge/ @@ -2678,7 +2707,7 @@ Signed-off-by: Pawel Dembicki + pr_debug("PFE CDEV assigned major number: %d\n", pfe_majno); + + /* Register the class for the device */ -+ pfe_char_class = class_create(THIS_MODULE, PFE_CLASS_NAME); ++ pfe_char_class = class_create(PFE_CLASS_NAME); + if (IS_ERR(pfe_char_class)) { + pr_err( + "Failed to init class for PFE CDEV. PFE CDEV not available.\n"); @@ -3233,7 +3262,7 @@ Signed-off-by: Pawel Dembicki +#endif /* _PFE_DEBUGFS_H_ */ --- /dev/null +++ b/drivers/staging/fsl_ppfe/pfe_eth.c -@@ -0,0 +1,2588 @@ +@@ -0,0 +1,2550 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2015-2016 Freescale Semiconductor, Inc. @@ -4120,24 +4149,6 @@ Signed-off-by: Pawel Dembicki + return 0; +} + -+static int pfe_eth_mdio_write_addr(struct mii_bus *bus, int mii_id, -+ int dev_addr, int regnum) -+{ -+ struct pfe_mdio_priv_s *priv = (struct pfe_mdio_priv_s *)bus->priv; -+ -+ __raw_writel(EMAC_MII_DATA_PA(mii_id) | -+ EMAC_MII_DATA_RA(dev_addr) | -+ EMAC_MII_DATA_TA | EMAC_MII_DATA(regnum), -+ priv->mdio_base + EMAC_MII_DATA_REG); -+ -+ if (pfe_eth_mdio_timeout(priv, EMAC_MDIO_TIMEOUT)) { -+ dev_err(&bus->dev, "phy MDIO address write timeout\n"); -+ return -1; -+ } -+ -+ return 0; -+} -+ +static int pfe_eth_mdio_write(struct mii_bus *bus, int mii_id, int regnum, + u16 value) +{ @@ -4147,22 +4158,12 @@ Signed-off-by: Pawel Dembicki + if ((mii_id) && (pfe->mdio_muxval[mii_id])) + pfe_eth_mdio_mux(pfe->mdio_muxval[mii_id]); + -+ if (regnum & MII_ADDR_C45) { -+ pfe_eth_mdio_write_addr(bus, mii_id, (regnum >> 16) & 0x1f, -+ regnum & 0xffff); -+ __raw_writel(EMAC_MII_DATA_OP_CL45_WR | -+ EMAC_MII_DATA_PA(mii_id) | -+ EMAC_MII_DATA_RA((regnum >> 16) & 0x1f) | -+ EMAC_MII_DATA_TA | EMAC_MII_DATA(value), -+ priv->mdio_base + EMAC_MII_DATA_REG); -+ } else { -+ /* start a write op */ -+ __raw_writel(EMAC_MII_DATA_ST | EMAC_MII_DATA_OP_WR | -+ EMAC_MII_DATA_PA(mii_id) | -+ EMAC_MII_DATA_RA(regnum) | -+ EMAC_MII_DATA_TA | EMAC_MII_DATA(value), -+ priv->mdio_base + EMAC_MII_DATA_REG); -+ } ++ /* start a write op */ ++ __raw_writel(EMAC_MII_DATA_ST | EMAC_MII_DATA_OP_WR | ++ EMAC_MII_DATA_PA(mii_id) | ++ EMAC_MII_DATA_RA(regnum) | ++ EMAC_MII_DATA_TA | EMAC_MII_DATA(value), ++ priv->mdio_base + EMAC_MII_DATA_REG); + + if (pfe_eth_mdio_timeout(priv, EMAC_MDIO_TIMEOUT)) { + dev_err(&bus->dev, "%s: phy MDIO write timeout\n", __func__); @@ -4180,22 +4181,12 @@ Signed-off-by: Pawel Dembicki + if ((mii_id) && (pfe->mdio_muxval[mii_id])) + pfe_eth_mdio_mux(pfe->mdio_muxval[mii_id]); + -+ if (regnum & MII_ADDR_C45) { -+ pfe_eth_mdio_write_addr(bus, mii_id, (regnum >> 16) & 0x1f, -+ regnum & 0xffff); -+ __raw_writel(EMAC_MII_DATA_OP_CL45_RD | -+ EMAC_MII_DATA_PA(mii_id) | -+ EMAC_MII_DATA_RA((regnum >> 16) & 0x1f) | -+ EMAC_MII_DATA_TA, -+ priv->mdio_base + EMAC_MII_DATA_REG); -+ } else { -+ /* start a read op */ -+ __raw_writel(EMAC_MII_DATA_ST | EMAC_MII_DATA_OP_RD | -+ EMAC_MII_DATA_PA(mii_id) | -+ EMAC_MII_DATA_RA(regnum) | -+ EMAC_MII_DATA_TA, priv->mdio_base + -+ EMAC_MII_DATA_REG); -+ } ++ /* start a read op */ ++ __raw_writel(EMAC_MII_DATA_ST | EMAC_MII_DATA_OP_RD | ++ EMAC_MII_DATA_PA(mii_id) | ++ EMAC_MII_DATA_RA(regnum) | ++ EMAC_MII_DATA_TA, priv->mdio_base + ++ EMAC_MII_DATA_REG); + + if (pfe_eth_mdio_timeout(priv, EMAC_MDIO_TIMEOUT)) { + dev_err(&bus->dev, "%s: phy MDIO read timeout\n", __func__); diff --git a/target/linux/layerscape/patches-6.6/702-phy-Add-2.5G-SGMII-interface-mode.patch b/target/linux/layerscape/patches-6.6/702-phy-Add-2.5G-SGMII-interface-mode.patch index 8beee8f2dc..abb0a1e5ed 100644 --- a/target/linux/layerscape/patches-6.6/702-phy-Add-2.5G-SGMII-interface-mode.patch +++ b/target/linux/layerscape/patches-6.6/702-phy-Add-2.5G-SGMII-interface-mode.patch @@ -1,4 +1,4 @@ -From fd32b1bc9a49919d3d59a50d775d03fe7ca5e654 Mon Sep 17 00:00:00 2001 +From 3823e4e1078a95e26b9a69e88c9bf862b0267e1c Mon Sep 17 00:00:00 2001 From: Bhaskar Upadhaya Date: Wed, 29 Nov 2017 15:27:57 +0530 Subject: [PATCH] phy: Add 2.5G SGMII interface mode @@ -9,13 +9,13 @@ in existing phy_interface list Signed-off-by: Bhaskar Upadhaya --- drivers/net/phy/phy-core.c | 1 + - drivers/net/phy/phylink.c | 1 + + drivers/net/phy/phylink.c | 2 ++ include/linux/phy.h | 3 +++ - 3 files changed, 5 insertions(+) + 3 files changed, 6 insertions(+) --- a/drivers/net/phy/phy-core.c +++ b/drivers/net/phy/phy-core.c -@@ -136,6 +136,7 @@ int phy_interface_num_ports(phy_interfac +@@ -138,6 +138,7 @@ int phy_interface_num_ports(phy_interfac case PHY_INTERFACE_MODE_RXAUI: case PHY_INTERFACE_MODE_XAUI: case PHY_INTERFACE_MODE_1000BASEKX: @@ -33,9 +33,17 @@ Signed-off-by: Bhaskar Upadhaya return SPEED_2500; case PHY_INTERFACE_MODE_5GBASER: +@@ -526,6 +527,7 @@ unsigned long phylink_get_capabilities(p + break; + + case PHY_INTERFACE_MODE_2500BASEX: ++ case PHY_INTERFACE_MODE_2500SGMII: + caps |= MAC_2500FD; + break; + --- a/include/linux/phy.h +++ b/include/linux/phy.h -@@ -159,6 +159,7 @@ typedef enum { +@@ -165,6 +165,7 @@ typedef enum { PHY_INTERFACE_MODE_10GKR, PHY_INTERFACE_MODE_QUSGMII, PHY_INTERFACE_MODE_1000BASEKX, @@ -43,7 +51,7 @@ Signed-off-by: Bhaskar Upadhaya PHY_INTERFACE_MODE_MAX, } phy_interface_t; -@@ -280,6 +281,8 @@ static inline const char *phy_modes(phy_ +@@ -286,6 +287,8 @@ static inline const char *phy_modes(phy_ return "100base-x"; case PHY_INTERFACE_MODE_QUSGMII: return "qusgmii"; diff --git a/target/linux/layerscape/patches-6.6/704-net-phylink-treat-PHY_INTERFACE_MODE_2500SGMII-in-ph.patch b/target/linux/layerscape/patches-6.6/704-net-phylink-treat-PHY_INTERFACE_MODE_2500SGMII-in-ph.patch deleted file mode 100644 index 1a1d7a0ac7..0000000000 --- a/target/linux/layerscape/patches-6.6/704-net-phylink-treat-PHY_INTERFACE_MODE_2500SGMII-in-ph.patch +++ /dev/null @@ -1,42 +0,0 @@ -From eb57941154e2ad142c07d47e874a221328467349 Mon Sep 17 00:00:00 2001 -From: Ioana Ciornei -Date: Thu, 2 Jun 2022 12:11:11 +0300 -Subject: [PATCH] net: phylink: treat PHY_INTERFACE_MODE_2500SGMII in - phylink_get_linkmodes -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -There is a downstream patch which adds a new interface type - -PHY_INTERFACE_MODE_2500SGMII (which is really the same one as -PHY_INTERFACE_MODE_2500BASEX). - -We backported from upstream the following phylink patch which, of -course, does not treat the PHY_INTERFACE_MODE_2500SGMII interface mode -in a switch case statement. - 34ae2c09d46a ("net: phylink: add generic validate implementation") - -Because of this, we get the following build warning. - -drivers/net/phy/phylink.c: In function ‘phylink_get_linkmodes’: -drivers/net/phy/phylink.c:322:2: warning: enumeration value ‘PHY_INTERFACE_MODE_2500SGMII’ not handled in switch [-Wswitch] - 322 | switch (interface) { - | ^~~~~~ - -Fix it by treating the new interface mode in the switch-case statement. - -Signed-off-by: Ioana Ciornei ---- - drivers/net/phy/phylink.c | 1 + - 1 file changed, 1 insertion(+) - ---- a/drivers/net/phy/phylink.c -+++ b/drivers/net/phy/phylink.c -@@ -505,6 +505,7 @@ unsigned long phylink_get_capabilities(p - break; - - case PHY_INTERFACE_MODE_2500BASEX: -+ case PHY_INTERFACE_MODE_2500SGMII: - caps |= MAC_2500FD; - break; - -- 2.30.2