From 32385427106a0ac68ea53b51f603f76c32920f49 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 31 Dec 2018 16:48:04 +0100 Subject: [PATCH] rcar_gen3: plat: Disable IPMMU PV0 cache on E3 Disable the IPMMU PV0 cache on E3 rev. 1.x . Signed-off-by: Marek Vasut --- plat/renesas/rcar/bl2_plat_setup.c | 1 + plat/renesas/rcar/include/rcar_def.h | 2 ++ 2 files changed, 3 insertions(+) diff --git a/plat/renesas/rcar/bl2_plat_setup.c b/plat/renesas/rcar/bl2_plat_setup.c index 99f98f35..52dfb40b 100644 --- a/plat/renesas/rcar/bl2_plat_setup.c +++ b/plat/renesas/rcar/bl2_plat_setup.c @@ -264,6 +264,7 @@ tlb: } else if ((product_cut == (RCAR_PRODUCT_E3 | RCAR_CUT_VER10)) || (product_cut == (RCAR_PRODUCT_E3 | RCAR_CUT_VER11))) { mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE); + mmio_write_32(IPMMUVP0_IMSCTLR, IMSCTLR_DISCACHE); mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE); } diff --git a/plat/renesas/rcar/include/rcar_def.h b/plat/renesas/rcar/include/rcar_def.h index 3dbd3f58..1829e59c 100644 --- a/plat/renesas/rcar/include/rcar_def.h +++ b/plat/renesas/rcar/include/rcar_def.h @@ -231,6 +231,8 @@ #define IPMMUMM_IMSCTLR_ENABLE (0xC0000000U) #define IPMMUMM_IMAUXCTLR_NMERGE40_BIT (0x01000000U) #define IMSCTLR_DISCACHE (0xE0000000U) +#define IPMMU_VP0_BASE (0xFE990000U) +#define IPMMUVP0_IMSCTLR (IPMMU_VP0_BASE + 0x0500U) #define IPMMU_VI0_BASE (0xFEBD0000U) #define IPMMUVI0_IMSCTLR (IPMMU_VI0_BASE + 0x0500U) #define IPMMU_VI1_BASE (0xFEBE0000U) -- 2.30.2