From 31d97dc2d876d1948963e4f4e6ef3b549dc98e18 Mon Sep 17 00:00:00 2001 From: Anthony Zhou Date: Mon, 13 Mar 2017 16:47:58 +0800 Subject: [PATCH] Tegra: pmc: fix defects flagged during MISRA analysis Main fixes: * Fixed if/while statement conditional to be essentially boolean [Rule 14.4] * Added curly braces ({}) around if/for/while statements in order to make them compound [Rule 15.6] * Added explicit casts (e.g. 0U) to integers in order for them to be compatible with whatever operation they're used in [Rule 10.1] Change-Id: Ic72b248aeede6cf18bf85051188ea7b8fd8ae829 Signed-off-by: Anthony Zhou --- plat/nvidia/tegra/common/drivers/pmc/pmc.c | 72 +++++++++++----------- plat/nvidia/tegra/include/drivers/pmc.h | 29 ++++----- 2 files changed, 52 insertions(+), 49 deletions(-) diff --git a/plat/nvidia/tegra/common/drivers/pmc/pmc.c b/plat/nvidia/tegra/common/drivers/pmc/pmc.c index 09e4c4aa..d8827e10 100644 --- a/plat/nvidia/tegra/common/drivers/pmc/pmc.c +++ b/plat/nvidia/tegra/common/drivers/pmc/pmc.c @@ -11,8 +11,10 @@ #include #include +#define RESET_ENABLE 0x10U + /* Module IDs used during power ungate procedure */ -static const int pmc_cpu_powergate_id[4] = { +static const uint32_t pmc_cpu_powergate_id[4] = { 0, /* CPU 0 */ 9, /* CPU 1 */ 10, /* CPU 2 */ @@ -23,7 +25,7 @@ static const int pmc_cpu_powergate_id[4] = { * Power ungate CPU to start the boot process. CPU reset vectors must be * populated before calling this function. ******************************************************************************/ -void tegra_pmc_cpu_on(int cpu) +void tegra_pmc_cpu_on(int32_t cpu) { uint32_t val; @@ -31,35 +33,34 @@ void tegra_pmc_cpu_on(int cpu) * Check if CPU is already power ungated */ val = tegra_pmc_read_32(PMC_PWRGATE_STATUS); - if (val & (1 << pmc_cpu_powergate_id[cpu])) - return; - - /* - * The PMC deasserts the START bit when it starts the power - * ungate process. Loop till no power toggle is in progress. - */ - do { - val = tegra_pmc_read_32(PMC_PWRGATE_TOGGLE); - } while (val & PMC_TOGGLE_START); - - /* - * Start the power ungate procedure - */ - val = pmc_cpu_powergate_id[cpu] | PMC_TOGGLE_START; - tegra_pmc_write_32(PMC_PWRGATE_TOGGLE, val); - - /* - * The PMC deasserts the START bit when it starts the power - * ungate process. Loop till powergate START bit is asserted. - */ - do { - val = tegra_pmc_read_32(PMC_PWRGATE_TOGGLE); - } while (val & (1 << 8)); - - /* loop till the CPU is power ungated */ - do { - val = tegra_pmc_read_32(PMC_PWRGATE_STATUS); - } while ((val & (1 << pmc_cpu_powergate_id[cpu])) == 0); + if ((val & (1U << pmc_cpu_powergate_id[cpu])) == 0U) { + /* + * The PMC deasserts the START bit when it starts the power + * ungate process. Loop till no power toggle is in progress. + */ + do { + val = tegra_pmc_read_32(PMC_PWRGATE_TOGGLE); + } while ((val & PMC_TOGGLE_START) != 0U); + + /* + * Start the power ungate procedure + */ + val = pmc_cpu_powergate_id[cpu] | PMC_TOGGLE_START; + tegra_pmc_write_32(PMC_PWRGATE_TOGGLE, val); + + /* + * The PMC deasserts the START bit when it starts the power + * ungate process. Loop till powergate START bit is asserted. + */ + do { + val = tegra_pmc_read_32(PMC_PWRGATE_TOGGLE); + } while ((val & (1U << 8)) != 0U); + + /* loop till the CPU is power ungated */ + do { + val = tegra_pmc_read_32(PMC_PWRGATE_STATUS); + } while ((val & (1U << pmc_cpu_powergate_id[cpu])) == 0U); + } } /******************************************************************************* @@ -69,9 +70,10 @@ void tegra_pmc_cpu_setup(uint64_t reset_addr) { uint32_t val; - tegra_pmc_write_32(PMC_SECURE_SCRATCH34, (reset_addr & 0xFFFFFFFF) | 1); - val = reset_addr >> 32; - tegra_pmc_write_32(PMC_SECURE_SCRATCH35, val & 0x7FF); + tegra_pmc_write_32(PMC_SECURE_SCRATCH34, + ((uint32_t)reset_addr & 0xFFFFFFFFU) | 1U); + val = (uint32_t)(reset_addr >> 32U); + tegra_pmc_write_32(PMC_SECURE_SCRATCH35, val & 0x7FFU); } /******************************************************************************* @@ -101,7 +103,7 @@ __dead2 void tegra_pmc_system_reset(void) uint32_t reg; reg = tegra_pmc_read_32(PMC_CONFIG); - reg |= 0x10; /* restart */ + reg |= RESET_ENABLE; /* restart */ tegra_pmc_write_32(PMC_CONFIG, reg); wfi(); diff --git a/plat/nvidia/tegra/include/drivers/pmc.h b/plat/nvidia/tegra/include/drivers/pmc.h index 7bf3f813..ea9392b6 100644 --- a/plat/nvidia/tegra/include/drivers/pmc.h +++ b/plat/nvidia/tegra/include/drivers/pmc.h @@ -9,20 +9,21 @@ #include #include +#include -#define PMC_CONFIG 0x0U -#define PMC_PWRGATE_STATUS 0x38U -#define PMC_PWRGATE_TOGGLE 0x30U -#define PMC_TOGGLE_START 0x100U -#define PMC_SCRATCH39 0x138U -#define PMC_SECURE_DISABLE2 0x2c4U -#define PMC_SECURE_DISABLE2_WRITE22_ON (1U << 28) -#define PMC_SECURE_SCRATCH22 0x338U -#define PMC_SECURE_DISABLE3 0x2d8U -#define PMC_SECURE_DISABLE3_WRITE34_ON (1U << 20) -#define PMC_SECURE_DISABLE3_WRITE35_ON (1U << 22) -#define PMC_SECURE_SCRATCH34 0x368U -#define PMC_SECURE_SCRATCH35 0x36cU +#define PMC_CONFIG U(0x0) +#define PMC_PWRGATE_STATUS U(0x38) +#define PMC_PWRGATE_TOGGLE U(0x30) +#define PMC_TOGGLE_START U(0x100) +#define PMC_SCRATCH39 U(0x138) +#define PMC_SECURE_DISABLE2 U(0x2c4) +#define PMC_SECURE_DISABLE2_WRITE22_ON (U(1) << 28) +#define PMC_SECURE_SCRATCH22 U(0x338) +#define PMC_SECURE_DISABLE3 U(0x2d8) +#define PMC_SECURE_DISABLE3_WRITE34_ON (U(1) << 20) +#define PMC_SECURE_DISABLE3_WRITE35_ON (U(1) << 22) +#define PMC_SECURE_SCRATCH34 U(0x368) +#define PMC_SECURE_SCRATCH35 U(0x36c) static inline uint32_t tegra_pmc_read_32(uint32_t off) { @@ -36,7 +37,7 @@ static inline void tegra_pmc_write_32(uint32_t off, uint32_t val) void tegra_pmc_cpu_setup(uint64_t reset_addr); void tegra_pmc_lock_cpu_vectors(void); -void tegra_pmc_cpu_on(int cpu); +void tegra_pmc_cpu_on(int32_t cpu); __dead2 void tegra_pmc_system_reset(void); #endif /* __PMC_H__ */ -- 2.30.2