From 30037f66ce63b6b7ca1fbfb06605b831f4a60df6 Mon Sep 17 00:00:00 2001 From: Venkatesh Pallipadi Date: Sun, 30 Oct 2005 14:59:38 -0800 Subject: [PATCH] [PATCH] x86: when L3 is present show its size in /proc/cpuinfo The code that prints the cache size assumes that L3 always lives in chipset and is shared across CPUs. Which is not really true. I think all the cachesizes reported by cpuid are in the processor itself. The attached patch changes the code to reflect that. Signed-off-by: Venkatesh Pallipadi Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- arch/i386/kernel/cpu/intel_cacheinfo.c | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/arch/i386/kernel/cpu/intel_cacheinfo.c b/arch/i386/kernel/cpu/intel_cacheinfo.c index c802206274c2..7cc84a4a6df9 100644 --- a/arch/i386/kernel/cpu/intel_cacheinfo.c +++ b/arch/i386/kernel/cpu/intel_cacheinfo.c @@ -278,13 +278,7 @@ unsigned int __devinit init_intel_cacheinfo(struct cpuinfo_x86 *c) if ( l3 ) printk(KERN_INFO "CPU: L3 cache: %dK\n", l3); - /* - * This assumes the L3 cache is shared; it typically lives in - * the northbridge. The L1 caches are included by the L2 - * cache, and so should not be included for the purpose of - * SMP switching weights. - */ - c->x86_cache_size = l2 ? l2 : (l1i+l1d); + c->x86_cache_size = l3 ? l3 : (l2 ? l2 : (l1i+l1d)); } return l2; -- 2.30.2