From 2bba85f41246d2bc1db00f2b0cce831b5efd4dfe Mon Sep 17 00:00:00 2001 From: York Sun Date: Wed, 24 Aug 2011 09:40:25 -0700 Subject: [PATCH] powerpc/mpc8xxx: Extend CWL table Extend CAS write Latency (CWL) table to comply with DDR3 spec Signed-off-by: York Sun Signed-off-by: Kumar Gala --- arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c index 3824aade89..6aee14a609 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c @@ -94,6 +94,10 @@ static inline int fsl_ddr_get_rtt(void) * 6 if 2.5ns > tCK >= 1.875ns * 7 if 1.875ns > tCK >= 1.5ns * 8 if 1.5ns > tCK >= 1.25ns + * 9 if 1.25ns > tCK >= 1.07ns + * 10 if 1.07ns > tCK >= 0.935ns + * 11 if 0.935ns > tCK >= 0.833ns + * 12 if 0.833ns > tCK >= 0.75ns */ static inline unsigned int compute_cas_write_latency(void) { @@ -108,8 +112,18 @@ static inline unsigned int compute_cas_write_latency(void) cwl = 7; else if (mclk_ps >= 1250) cwl = 8; - else - cwl = 8; + else if (mclk_ps >= 1070) + cwl = 9; + else if (mclk_ps >= 935) + cwl = 10; + else if (mclk_ps >= 833) + cwl = 11; + else if (mclk_ps >= 750) + cwl = 12; + else { + cwl = 12; + printf("Warning: CWL is out of range\n"); + } return cwl; } -- 2.30.2