From 248cdf0b5270651ca5eefb1aff4a338df6a1ca25 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Beno=C3=AEt=20Th=C3=A9baudeau?= Date: Thu, 27 Sep 2012 10:21:22 +0000 Subject: [PATCH] mx5: Fix clock gate values MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit The clock gate values are 2-bit bit-fields. Hence, setting or clearing only one of these bits like what was done is wrong and can lead to unpredictable behavior depending on the original value of these bit-fields. Signed-off-by: Benoît Thébaudeau Cc: Stefano Babic --- arch/arm/cpu/armv7/mx5/clock.c | 27 +++++++++++++----------- arch/arm/include/asm/arch-mx5/crm_regs.h | 3 +++ 2 files changed, 18 insertions(+), 12 deletions(-) diff --git a/arch/arm/cpu/armv7/mx5/clock.c b/arch/arm/cpu/armv7/mx5/clock.c index cba5d1bf0b..171d7629ef 100644 --- a/arch/arm/cpu/armv7/mx5/clock.c +++ b/arch/arm/cpu/armv7/mx5/clock.c @@ -101,10 +101,11 @@ void set_usboh3_clk(void) void enable_usboh3_clk(unsigned char enable) { - if (enable) - setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_USBOH3_60M(1)); - else - clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_USBOH3_60M(1)); + unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF; + + clrsetbits_le32(&mxc_ccm->CCGR2, + MXC_CCM_CCGR2_USBOH3_60M(MXC_CCM_CCGR_CG_MASK), + MXC_CCM_CCGR2_USBOH3_60M(cg)); } #ifdef CONFIG_I2C_MXC @@ -132,10 +133,11 @@ void set_usb_phy1_clk(void) void enable_usb_phy1_clk(unsigned char enable) { - if (enable) - setbits_le32(&mxc_ccm->CCGR4, MXC_CCM_CCGR4_USB_PHY1(1)); - else - clrbits_le32(&mxc_ccm->CCGR4, MXC_CCM_CCGR4_USB_PHY1(1)); + unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF; + + clrsetbits_le32(&mxc_ccm->CCGR4, + MXC_CCM_CCGR4_USB_PHY1(MXC_CCM_CCGR_CG_MASK), + MXC_CCM_CCGR4_USB_PHY1(cg)); } void set_usb_phy2_clk(void) @@ -145,10 +147,11 @@ void set_usb_phy2_clk(void) void enable_usb_phy2_clk(unsigned char enable) { - if (enable) - setbits_le32(&mxc_ccm->CCGR4, MXC_CCM_CCGR4_USB_PHY2(1)); - else - clrbits_le32(&mxc_ccm->CCGR4, MXC_CCM_CCGR4_USB_PHY2(1)); + unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF; + + clrsetbits_le32(&mxc_ccm->CCGR4, + MXC_CCM_CCGR4_USB_PHY2(MXC_CCM_CCGR_CG_MASK), + MXC_CCM_CCGR4_USB_PHY2(cg)); } /* diff --git a/arch/arm/include/asm/arch-mx5/crm_regs.h b/arch/arm/include/asm/arch-mx5/crm_regs.h index d5eb303388..3b0ed64fc0 100644 --- a/arch/arm/include/asm/arch-mx5/crm_regs.h +++ b/arch/arm/include/asm/arch-mx5/crm_regs.h @@ -285,6 +285,9 @@ struct mxc_ccm_reg { /* Define the bits in register CCGRx */ #define MXC_CCM_CCGR_CG_MASK 0x3 +#define MXC_CCM_CCGR_CG_OFF 0x0 +#define MXC_CCM_CCGR_CG_RUN_ON 0x1 +#define MXC_CCM_CCGR_CG_ON 0x3 #define MXC_CCM_CCGR0_ARM_BUS_OFFSET 0 #define MXC_CCM_CCGR0_ARM_BUS(v) (((v) & 0x3) << 0) -- 2.30.2