From 18f705fae35be3457edc6bd32efb66f539bde1dd Mon Sep 17 00:00:00 2001 From: Derek Basehore Date: Wed, 10 May 2017 21:59:31 -0700 Subject: [PATCH] rockchip/rk3399: Remove unneeded register sets This removes the mmio_... function calls to set the multicast bit for the PHY registers when overriding the write leveling values. These are not needed since multicast is set by default when calling the function, and it's also better not to leave the side effect of disabling multicast when exiting the function. Change-Id: I83e089a2a2d55268b3832f36724c3b2c4be81082 Signed-off-by: Derek Basehore --- plat/rockchip/rk3399/drivers/dram/suspend.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/plat/rockchip/rk3399/drivers/dram/suspend.c b/plat/rockchip/rk3399/drivers/dram/suspend.c index 3aba57ca..57fbfed9 100644 --- a/plat/rockchip/rk3399/drivers/dram/suspend.c +++ b/plat/rockchip/rk3399/drivers/dram/suspend.c @@ -139,9 +139,6 @@ static void override_write_leveling_value(uint32_t ch) { uint32_t byte; - /* PHY_896 PHY_FREQ_SEL_MULTICAST_EN 1bit offset_0 */ - mmio_setbits_32(PHY_REG(ch, 896), 1); - /* * PHY_8/136/264/392 * phy_per_cs_training_multicast_en_X 1bit offset_16 @@ -156,9 +153,6 @@ static void override_write_leveling_value(uint32_t ch) 0xffff << 16, 0x200 << 16); - /* PHY_896 PHY_FREQ_SEL_MULTICAST_EN 1bit offset_0 */ - mmio_clrbits_32(PHY_REG(ch, 896), 1); - /* CTL_200 ctrlupd_req 1bit offset_8 */ mmio_clrsetbits_32(CTL_REG(ch, 200), 0x1 << 8, 0x1 << 8); } -- 2.30.2