From 18b401874aee10c80b5745c9b93280dae5a59809 Mon Sep 17 00:00:00 2001 From: Su Sung Chung Date: Fri, 21 Jun 2019 16:14:36 -0400 Subject: [PATCH] drm/amd/display: fix not calling ppsmu to trigger PME [why] dcn20_clk_mgr_construct was not initializing pp_smu, and PME call gets filtered out by the null check [how] initialize pp_smu dcn20_clk_mgr_construct Signed-off-by: Su Sung Chung Reviewed-by: Eric Yang Acked-by: Leo Li Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c index e9a7a7af11df..4842c91771d8 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c @@ -346,6 +346,8 @@ void dcn20_clk_mgr_construct( clk_mgr->base.dprefclk_khz = 700000; // 700 MHz planned if VCO is 3.85 GHz, will be retrieved + clk_mgr->pp_smu = pp_smu; + if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) { dcn2_funcs.update_clocks = dcn2_update_clocks_fpga; clk_mgr->dentist_vco_freq_khz = 3850000; -- 2.30.2