From 16031ebaf89f68ff3328e8d4a922adb244c2d5ae Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Sun, 2 Feb 2020 18:02:11 +0200 Subject: [PATCH] ath79: add support for Atheros AR934x HS UART AR934x chips also got the 'old' qca,ar9330-uart in addition to the 'new' ns16550a compatible one. Add support for UART1 clock selector as well as device-tree bindings in ar934x.dtsi to make use of that uart. Reported-by: Piotr Dymacz Signed-off-by: Daniel Golle --- target/linux/ath79/dts/ar934x.dtsi | 13 +++++ ...S-ath79-export-UART1-reference-clock.patch | 52 +++++++++++++++++++ 2 files changed, 65 insertions(+) create mode 100644 target/linux/ath79/patches-4.19/0039-MIPS-ath79-export-UART1-reference-clock.patch diff --git a/target/linux/ath79/dts/ar934x.dtsi b/target/linux/ath79/dts/ar934x.dtsi index c17623511b80..e8c21fb71061 100644 --- a/target/linux/ath79/dts/ar934x.dtsi +++ b/target/linux/ath79/dts/ar934x.dtsi @@ -133,6 +133,19 @@ #reset-cells = <1>; }; + + hs_uart: uart@18500000 { + compatible = "qca,ar9330-uart"; + reg = <0x18500000 0x14>; + + interrupts = <6>; + interrupt-parent = <&miscintc>; + + clocks = <&pll ATH79_CLK_UART1>; + clock-names = "uart"; + + status = "disabled"; + }; }; nand: nand@1b000200 { diff --git a/target/linux/ath79/patches-4.19/0039-MIPS-ath79-export-UART1-reference-clock.patch b/target/linux/ath79/patches-4.19/0039-MIPS-ath79-export-UART1-reference-clock.patch new file mode 100644 index 000000000000..8656fafe0ecf --- /dev/null +++ b/target/linux/ath79/patches-4.19/0039-MIPS-ath79-export-UART1-reference-clock.patch @@ -0,0 +1,52 @@ +--- a/arch/mips/ath79/clock.c ++++ b/arch/mips/ath79/clock.c +@@ -42,6 +42,7 @@ static const char * const clk_names[ATH7 + [ATH79_CLK_AHB] = "ahb", + [ATH79_CLK_REF] = "ref", + [ATH79_CLK_MDIO] = "mdio", ++ [ATH79_CLK_UART1] = "uart1", + }; + + static const char * __init ath79_clk_name(int type) +@@ -346,6 +347,9 @@ static void __init ar934x_clocks_init(vo + if (clk_ctrl & AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL) + ath79_set_clk(ATH79_CLK_MDIO, 100 * 1000 * 1000); + ++ if (clk_ctrl & AR934X_PLL_SWITCH_CLOCK_CONTROL_UART1_CLK_SEL) ++ ath79_set_clk(ATH79_CLK_UART1, 100 * 1000 * 1000); ++ + iounmap(dpll_base); + } + +@@ -651,6 +655,9 @@ static void __init ath79_clocks_init_dt( + if (!clks[ATH79_CLK_MDIO]) + clks[ATH79_CLK_MDIO] = clks[ATH79_CLK_REF]; + ++ if (!clks[ATH79_CLK_UART1]) ++ clks[ATH79_CLK_UART1] = clks[ATH79_CLK_REF]; ++ + if (of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data)) { + pr_err("%pOF: could not register clk provider\n", np); + goto err_iounmap; +--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h ++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +@@ -351,6 +351,7 @@ + #define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) + + #define AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL BIT(6) ++#define AR934X_PLL_SWITCH_CLOCK_CONTROL_UART1_CLK_SEL BIT(7) + + #define QCA953X_PLL_CPU_CONFIG_REG 0x00 + #define QCA953X_PLL_DDR_CONFIG_REG 0x04 +--- a/include/dt-bindings/clock/ath79-clk.h ++++ b/include/dt-bindings/clock/ath79-clk.h +@@ -15,7 +15,8 @@ + #define ATH79_CLK_AHB 2 + #define ATH79_CLK_REF 3 + #define ATH79_CLK_MDIO 4 ++#define ATH79_CLK_UART1 5 + +-#define ATH79_CLK_END 5 ++#define ATH79_CLK_END 6 + + #endif /* __DT_BINDINGS_ATH79_CLK_H */ -- 2.30.2