From 15652ec3ff381fc3cb0249908dd29153913918bc Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 14 Jun 2018 06:26:45 +0200 Subject: [PATCH] rcar_gen3: drivers: qos: Add D3 QoS tables Add QoS tables for R-Car D3 SoC. Signed-off-by: Marek Vasut --- .../staging/renesas/rcar/qos/D3/qos_init_d3.c | 581 ++++++++++++++++++ .../staging/renesas/rcar/qos/D3/qos_init_d3.h | 13 + drivers/staging/renesas/rcar/qos/qos.mk | 6 + drivers/staging/renesas/rcar/qos/qos_init.c | 29 +- 4 files changed, 626 insertions(+), 3 deletions(-) create mode 100644 drivers/staging/renesas/rcar/qos/D3/qos_init_d3.c create mode 100644 drivers/staging/renesas/rcar/qos/D3/qos_init_d3.h diff --git a/drivers/staging/renesas/rcar/qos/D3/qos_init_d3.c b/drivers/staging/renesas/rcar/qos/D3/qos_init_d3.c new file mode 100644 index 00000000..b115d633 --- /dev/null +++ b/drivers/staging/renesas/rcar/qos/D3/qos_init_d3.c @@ -0,0 +1,581 @@ +/* + * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include "qos_init_d3.h" + + +#define RCAR_QOS_VERSION "rev.0.05" + +#define RCAR_QOS_NONE (3U) +#define RCAR_QOS_TYPE_DEFAULT (0U) + +#define RCAR_DRAM_SPLIT_LINEAR (0U) +#define RCAR_DRAM_SPLIT_4CH (1U) +#define RCAR_DRAM_SPLIT_2CH (2U) +#define RCAR_DRAM_SPLIT_AUTO (3U) + +#define RST_BASE (0xE6160000U) +#define RST_MODEMR (RST_BASE + 0x0060U) + +#define DBSC_BASE (0xE6790000U) +#define DBSC_DBSYSCNT0 (DBSC_BASE + 0x0100U) +#define DBSC_AXARB (DBSC_BASE + 0x0800U) +#define DBSC_DBCAM0CNF0 (DBSC_BASE + 0x0900U) +#define DBSC_DBCAM0CNF1 (DBSC_BASE + 0x0904U) +#define DBSC_DBCAM0CNF2 (DBSC_BASE + 0x0908U) +#define DBSC_DBCAM0CNF3 (DBSC_BASE + 0x090CU) +#define DBSC_DBCAMDIS (DBSC_BASE + 0x09fCU) +#define DBSC_DBSCHCNT0 (DBSC_BASE + 0x1000U) +#define DBSC_DBSCHCNT1 (DBSC_BASE + 0x1004U) +#define DBSC_DBSCHSZ0 (DBSC_BASE + 0x1010U) +#define DBSC_DBSCHRW0 (DBSC_BASE + 0x1020U) +#define DBSC_DBSCHRW1 (DBSC_BASE + 0x1024U) +#define DBSC_DBSCHQOS_0_0 (DBSC_BASE + 0x1030U) +#define DBSC_DBSCHQOS_0_1 (DBSC_BASE + 0x1034U) +#define DBSC_DBSCHQOS_0_2 (DBSC_BASE + 0x1038U) +#define DBSC_DBSCHQOS_0_3 (DBSC_BASE + 0x103CU) +#define DBSC_DBSCHQOS_1_0 (DBSC_BASE + 0x1040U) +#define DBSC_DBSCHQOS_1_1 (DBSC_BASE + 0x1044U) +#define DBSC_DBSCHQOS_1_2 (DBSC_BASE + 0x1048U) +#define DBSC_DBSCHQOS_1_3 (DBSC_BASE + 0x104CU) +#define DBSC_DBSCHQOS_2_0 (DBSC_BASE + 0x1050U) +#define DBSC_DBSCHQOS_2_1 (DBSC_BASE + 0x1054U) +#define DBSC_DBSCHQOS_2_2 (DBSC_BASE + 0x1058U) +#define DBSC_DBSCHQOS_2_3 (DBSC_BASE + 0x105CU) +#define DBSC_DBSCHQOS_3_0 (DBSC_BASE + 0x1060U) +#define DBSC_DBSCHQOS_3_1 (DBSC_BASE + 0x1064U) +#define DBSC_DBSCHQOS_3_2 (DBSC_BASE + 0x1068U) +#define DBSC_DBSCHQOS_3_3 (DBSC_BASE + 0x106CU) +#define DBSC_DBSCHQOS_4_0 (DBSC_BASE + 0x1070U) +#define DBSC_DBSCHQOS_4_1 (DBSC_BASE + 0x1074U) +#define DBSC_DBSCHQOS_4_2 (DBSC_BASE + 0x1078U) +#define DBSC_DBSCHQOS_4_3 (DBSC_BASE + 0x107CU) +#define DBSC_DBSCHQOS_5_0 (DBSC_BASE + 0x1080U) +#define DBSC_DBSCHQOS_5_1 (DBSC_BASE + 0x1084U) +#define DBSC_DBSCHQOS_5_2 (DBSC_BASE + 0x1088U) +#define DBSC_DBSCHQOS_5_3 (DBSC_BASE + 0x108CU) +#define DBSC_DBSCHQOS_6_0 (DBSC_BASE + 0x1090U) +#define DBSC_DBSCHQOS_6_1 (DBSC_BASE + 0x1094U) +#define DBSC_DBSCHQOS_6_2 (DBSC_BASE + 0x1098U) +#define DBSC_DBSCHQOS_6_3 (DBSC_BASE + 0x109CU) +#define DBSC_DBSCHQOS_7_0 (DBSC_BASE + 0x10A0U) +#define DBSC_DBSCHQOS_7_1 (DBSC_BASE + 0x10A4U) +#define DBSC_DBSCHQOS_7_2 (DBSC_BASE + 0x10A8U) +#define DBSC_DBSCHQOS_7_3 (DBSC_BASE + 0x10ACU) +#define DBSC_DBSCHQOS_8_0 (DBSC_BASE + 0x10B0U) +#define DBSC_DBSCHQOS_8_1 (DBSC_BASE + 0x10B4U) +#define DBSC_DBSCHQOS_8_2 (DBSC_BASE + 0x10B8U) +#define DBSC_DBSCHQOS_8_3 (DBSC_BASE + 0x10BCU) +#define DBSC_DBSCHQOS_9_0 (DBSC_BASE + 0x10C0U) +#define DBSC_DBSCHQOS_9_1 (DBSC_BASE + 0x10C4U) +#define DBSC_DBSCHQOS_9_2 (DBSC_BASE + 0x10C8U) +#define DBSC_DBSCHQOS_9_3 (DBSC_BASE + 0x10CCU) +#define DBSC_DBSCHQOS_10_0 (DBSC_BASE + 0x10D0U) +#define DBSC_DBSCHQOS_10_1 (DBSC_BASE + 0x10D4U) +#define DBSC_DBSCHQOS_10_2 (DBSC_BASE + 0x10D8U) +#define DBSC_DBSCHQOS_10_3 (DBSC_BASE + 0x10DCU) +#define DBSC_DBSCHQOS_11_0 (DBSC_BASE + 0x10E0U) +#define DBSC_DBSCHQOS_11_1 (DBSC_BASE + 0x10E4U) +#define DBSC_DBSCHQOS_11_2 (DBSC_BASE + 0x10E8U) +#define DBSC_DBSCHQOS_11_3 (DBSC_BASE + 0x10ECU) +#define DBSC_DBSCHQOS_12_0 (DBSC_BASE + 0x10F0U) +#define DBSC_DBSCHQOS_12_1 (DBSC_BASE + 0x10F4U) +#define DBSC_DBSCHQOS_12_2 (DBSC_BASE + 0x10F8U) +#define DBSC_DBSCHQOS_12_3 (DBSC_BASE + 0x10FCU) +#define DBSC_DBSCHQOS_13_0 (DBSC_BASE + 0x1100U) +#define DBSC_DBSCHQOS_13_1 (DBSC_BASE + 0x1104U) +#define DBSC_DBSCHQOS_13_2 (DBSC_BASE + 0x1108U) +#define DBSC_DBSCHQOS_13_3 (DBSC_BASE + 0x110CU) +#define DBSC_DBSCHQOS_14_0 (DBSC_BASE + 0x1110U) +#define DBSC_DBSCHQOS_14_1 (DBSC_BASE + 0x1114U) +#define DBSC_DBSCHQOS_14_2 (DBSC_BASE + 0x1118U) +#define DBSC_DBSCHQOS_14_3 (DBSC_BASE + 0x111CU) +#define DBSC_DBSCHQOS_15_0 (DBSC_BASE + 0x1120U) +#define DBSC_DBSCHQOS_15_1 (DBSC_BASE + 0x1124U) +#define DBSC_DBSCHQOS_15_2 (DBSC_BASE + 0x1128U) +#define DBSC_DBSCHQOS_15_3 (DBSC_BASE + 0x112CU) +#define DBSC_SCFCTST2 (DBSC_BASE + 0x170CU) + +#define AXI_BASE (0xE6784000U) +#define AXI_ADSPLCR0 (AXI_BASE + 0x0008U) +#define AXI_ADSPLCR3 (AXI_BASE + 0x0014U) + +#define MSTAT_BASE (0xE67E0000U) +#define MSTAT_FIX_QOS_BANK0 (MSTAT_BASE + 0x0000U) +#define MSTAT_FIX_QOS_BANK1 (MSTAT_BASE + 0x1000U) +#define MSTAT_BE_QOS_BANK0 (MSTAT_BASE + 0x2000U) +#define MSTAT_BE_QOS_BANK1 (MSTAT_BASE + 0x3000U) +#define MSTAT_SL_INIT (MSTAT_BASE + 0x8000U) +#define MSTAT_REF_ARS (MSTAT_BASE + 0x8004U) +#define MSTAT_STATQC (MSTAT_BASE + 0x8008U) + +#define RALLOC_BASE (0xE67F0000U) +#define RALLOC_RAS (RALLOC_BASE + 0x0000U) +#define RALLOC_FIXTH (RALLOC_BASE + 0x0004U) +#define RALLOC_RAEN (RALLOC_BASE + 0x0018U) +#define RALLOC_REGGD (RALLOC_BASE + 0x0020U) +#define RALLOC_DANN (RALLOC_BASE + 0x0030U) +#define RALLOC_DANT (RALLOC_BASE + 0x0038U) +#define RALLOC_EC (RALLOC_BASE + 0x003CU) +#define RALLOC_EMS (RALLOC_BASE + 0x0040U) +#define RALLOC_FSS (RALLOC_BASE + 0x0048U) +#define RALLOC_INSFC (RALLOC_BASE + 0x0050U) +#define RALLOC_BERR (RALLOC_BASE + 0x0054U) +#define RALLOC_EARLYR (RALLOC_BASE + 0x0060U) +#define RALLOC_RACNT0 (RALLOC_BASE + 0x0080U) +#define RALLOC_TICKDUPL (RALLOC_BASE + 0x0088U) + +#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) + +static inline void io_write_32(uintptr_t addr, uint32_t value) +{ + *(volatile uint32_t*)addr = value; +} + +static inline void io_write_64(uintptr_t addr, uint64_t value) +{ + *(volatile uint64_t*)addr = value; +} + +typedef struct { + uintptr_t addr; + uint64_t value; +} mstat_slot_t; + + +#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT +static const mstat_slot_t mstat_fix[] = { + {0x0000U, 0x0000000000000000U}, + {0x0008U, 0x0000000000000000U}, + {0x0010U, 0x0000000000000000U}, + {0x0018U, 0x0000000000000000U}, + {0x0020U, 0x0000000000000000U}, + {0x0028U, 0x0000000000000000U}, + {0x0030U, 0x001004340000FFFFU}, + {0x0038U, 0x001004140000FFFFU}, + {0x0040U, 0x0000000000000000U}, + {0x0048U, 0x0000000000000000U}, + {0x0050U, 0x0000000000000000U}, + {0x0058U, 0x00140B030000FFFFU}, + {0x0060U, 0x001408610000FFFFU}, + {0x0068U, 0x0000000000000000U}, + {0x0070U, 0x0000000000000000U}, + {0x0078U, 0x0000000000000000U}, + {0x0080U, 0x0000000000000000U}, + {0x0088U, 0x001410620000FFFFU}, + {0x0090U, 0x0000000000000000U}, + {0x0098U, 0x0000000000000000U}, + {0x00A0U, 0x000C041C0000FFFFU}, + {0x00A8U, 0x000C04090000FFFFU}, + {0x00B0U, 0x000C04110000FFFFU}, + {0x00B8U, 0x0000000000000000U}, + {0x00C0U, 0x000C041C0000FFFFU}, + {0x00C8U, 0x000C04090000FFFFU}, + {0x00D0U, 0x000C04110000FFFFU}, + {0x00D8U, 0x0000000000000000U}, + {0x00E0U, 0x0000000000000000U}, + {0x00E8U, 0x0000000000000000U}, + {0x00F0U, 0x001018570000FFFFU}, + {0x00F8U, 0x0000000000000000U}, + {0x0100U, 0x0000000000000000U}, + {0x0108U, 0x0000000000000000U}, + {0x0110U, 0x001008570000FFFFU}, + {0x0118U, 0x0000000000000000U}, + {0x0120U, 0x0000000000000000U}, + {0x0128U, 0x0000000000000000U}, + {0x0130U, 0x0000000000000000U}, + {0x0138U, 0x0000000000000000U}, + {0x0140U, 0x0000000000000000U}, + {0x0148U, 0x0000000000000000U}, + {0x0150U, 0x001008520000FFFFU}, + {0x0158U, 0x0000000000000000U}, + {0x0160U, 0x0000000000000000U}, + {0x0168U, 0x0000000000000000U}, + {0x0170U, 0x0000000000000000U}, + {0x0178U, 0x0000000000000000U}, + {0x0180U, 0x0000000000000000U}, + {0x0188U, 0x0000000000000000U}, + {0x0190U, 0x00100CA30000FFFFU}, + {0x0198U, 0x0000000000000000U}, + {0x01A0U, 0x0000000000000000U}, + {0x01A8U, 0x0000000000000000U}, + {0x01B0U, 0x0000000000000000U}, + {0x01B8U, 0x0000000000000000U}, + {0x01C0U, 0x0000000000000000U}, + {0x01C8U, 0x0000000000000000U}, + {0x01D0U, 0x0000000000000000U}, + {0x01D8U, 0x0000000000000000U}, + {0x01E0U, 0x0000000000000000U}, + {0x01E8U, 0x000C04020000FFFFU}, + {0x01F0U, 0x0000000000000000U}, + {0x01F8U, 0x0000000000000000U}, + {0x0200U, 0x0000000000000000U}, + {0x0208U, 0x000C04090000FFFFU}, + {0x0210U, 0x0000000000000000U}, + {0x0218U, 0x0000000000000000U}, + {0x0220U, 0x0000000000000000U}, + {0x0228U, 0x0000000000000000U}, + {0x0230U, 0x0000000000000000U}, + {0x0238U, 0x0000000000000000U}, + {0x0240U, 0x0000000000000000U}, + {0x0248U, 0x0000000000000000U}, + {0x0250U, 0x0000000000000000U}, + {0x0258U, 0x0000000000000000U}, + {0x0260U, 0x0000000000000000U}, + {0x0268U, 0x001410040000FFFFU}, + {0x0270U, 0x001404020000FFFFU}, + {0x0278U, 0x0000000000000000U}, + {0x0280U, 0x0000000000000000U}, + {0x0288U, 0x0000000000000000U}, + {0x0290U, 0x001410040000FFFFU}, + {0x0298U, 0x001404020000FFFFU}, + {0x02A0U, 0x000C04050000FFFFU}, + {0x02A8U, 0x000C04050000FFFFU}, + {0x02B0U, 0x0000000000000000U}, + {0x02B8U, 0x0000000000000000U}, + {0x02C0U, 0x0000000000000000U}, + {0x02C8U, 0x0000000000000000U}, + {0x02D0U, 0x000C04050000FFFFU}, + {0x02D8U, 0x000C04050000FFFFU}, + {0x02E0U, 0x0000000000000000U}, + {0x02E8U, 0x0000000000000000U}, + {0x02F0U, 0x0000000000000000U}, + {0x02F8U, 0x0000000000000000U}, + {0x0300U, 0x0000000000000000U}, + {0x0308U, 0x0000000000000000U}, + {0x0310U, 0x0000000000000000U}, + {0x0318U, 0x0000000000000000U}, + {0x0320U, 0x0000000000000000U}, + {0x0328U, 0x0000000000000000U}, + {0x0330U, 0x0000000000000000U}, + {0x0338U, 0x0000000000000000U}, + {0x0340U, 0x0000000000000000U}, + {0x0348U, 0x0000000000000000U}, + {0x0350U, 0x0000000000000000U}, + {0x0358U, 0x0000000000000000U}, + {0x0360U, 0x0000000000000000U}, + {0x0368U, 0x0000000000000000U}, + {0x0370U, 0x000C04020000FFFFU}, + {0x0378U, 0x000C04020000FFFFU}, + {0x0380U, 0x000C04090000FFFFU}, + {0x0388U, 0x000C04090000FFFFU}, + {0x0390U, 0x0000000000000000U}, +}; + +static const mstat_slot_t mstat_be[] = { + {0x0000U, 0x0000000000000000U}, + {0x0008U, 0x0000000000000000U}, + {0x0010U, 0x0000000000000000U}, + {0x0018U, 0x0000000000000000U}, + {0x0020U, 0x0000000000000000U}, + {0x0028U, 0x0000000000000000U}, + {0x0030U, 0x0000000000000000U}, + {0x0038U, 0x0000000000000000U}, + {0x0040U, 0x0000000000000000U}, + {0x0048U, 0x0000000000000000U}, + {0x0050U, 0x0000000000000000U}, + {0x0058U, 0x0000000000000000U}, + {0x0060U, 0x0000000000000000U}, + {0x0068U, 0x0000000000000000U}, + {0x0070U, 0x0000000000000000U}, + {0x0078U, 0x0000000000000000U}, + {0x0080U, 0x0000000000000000U}, + {0x0088U, 0x0000000000000000U}, + {0x0090U, 0x0000000000000000U}, + {0x0098U, 0x0000000000000000U}, + {0x00A0U, 0x0000000000000000U}, + {0x00A8U, 0x0000000000000000U}, + {0x00B0U, 0x0000000000000000U}, + {0x00B8U, 0x0000000000000000U}, + {0x00C0U, 0x0000000000000000U}, + {0x00C8U, 0x0000000000000000U}, + {0x00D0U, 0x0000000000000000U}, + {0x00D8U, 0x0000000000000000U}, + {0x00E0U, 0x0000000000000000U}, + {0x00E8U, 0x0000000000000000U}, + {0x00F0U, 0x0000000000000000U}, + {0x00F8U, 0x0000000000000000U}, + {0x0100U, 0x0000000000000000U}, + {0x0108U, 0x0000000000000000U}, + {0x0110U, 0x0000000000000000U}, + {0x0118U, 0x0000000000000000U}, + {0x0120U, 0x0000000000000000U}, + {0x0128U, 0x0000000000000000U}, + {0x0130U, 0x0000000000000000U}, + {0x0138U, 0x0000000000000000U}, + {0x0140U, 0x0000000000000000U}, + {0x0148U, 0x0000000000000000U}, + {0x0150U, 0x0000000000000000U}, + {0x0158U, 0x0000000000000000U}, + {0x0160U, 0x0000000000000000U}, + {0x0168U, 0x0000000000000000U}, + {0x0170U, 0x0000000000000000U}, + {0x0178U, 0x0000000000000000U}, + {0x0180U, 0x0000000000000000U}, + {0x0188U, 0x0000000000000000U}, + {0x0190U, 0x0000000000000000U}, + {0x0198U, 0x0000000000000000U}, + {0x01A0U, 0x0000000000000000U}, + {0x01A8U, 0x0000000000000000U}, + {0x01B0U, 0x0000000000000000U}, + {0x01B8U, 0x0000000000000000U}, + {0x01C0U, 0x00110090060FA001U}, + {0x01C8U, 0x00110090060FA001U}, + {0x01D0U, 0x0000000000000000U}, + {0x01D8U, 0x0000000000000000U}, + {0x01E0U, 0x0000000000000000U}, + {0x01E8U, 0x0000000000000000U}, + {0x01F0U, 0x0011001006004401U}, + {0x01F8U, 0x0000000000000000U}, + {0x0200U, 0x0000000000000000U}, + {0x0208U, 0x0000000000000000U}, + {0x0210U, 0x0011001006004401U}, + {0x0218U, 0x0011001006009801U}, + {0x0220U, 0x0011001006009801U}, + {0x0228U, 0x0000000000000000U}, + {0x0230U, 0x0011001006009801U}, + {0x0238U, 0x0011001006009801U}, + {0x0240U, 0x0000000000000000U}, + {0x0248U, 0x0000000000000000U}, + {0x0250U, 0x0000000000000000U}, + {0x0258U, 0x0000000000000000U}, + {0x0260U, 0x0000000000000000U}, + {0x0268U, 0x0000000000000000U}, + {0x0270U, 0x0000000000000000U}, + {0x0278U, 0x0000000000000000U}, + {0x0280U, 0x0000000000000000U}, + {0x0288U, 0x0000000000000000U}, + {0x0290U, 0x0000000000000000U}, + {0x0298U, 0x0000000000000000U}, + {0x02A0U, 0x0000000000000000U}, + {0x02A8U, 0x0000000000000000U}, + {0x02B0U, 0x0000000000000000U}, + {0x02B8U, 0x0011001006003401U}, + {0x02C0U, 0x0000000000000000U}, + {0x02C8U, 0x0000000000000000U}, + {0x02D0U, 0x0000000000000000U}, + {0x02D8U, 0x0000000000000000U}, + {0x02E0U, 0x0000000000000000U}, + {0x02E8U, 0x0011001006003401U}, + {0x02F0U, 0x00110090060FA001U}, + {0x02F8U, 0x00110090060FA001U}, + {0x0300U, 0x0000000000000000U}, + {0x0308U, 0x0000000000000000U}, + {0x0310U, 0x0000000000000000U}, + {0x0318U, 0x0012001006003401U}, + {0x0320U, 0x0000000000000000U}, + {0x0328U, 0x0000000000000000U}, + {0x0330U, 0x0000000000000000U}, + {0x0338U, 0x0000000000000000U}, + {0x0340U, 0x0000000000000000U}, + {0x0348U, 0x0000000000000000U}, + {0x0350U, 0x0000000000000000U}, + {0x0358U, 0x00120090060FA001U}, + {0x0360U, 0x00120090060FA001U}, + {0x0368U, 0x0012001006003401U}, + {0x0370U, 0x0000000000000000U}, + {0x0378U, 0x0000000000000000U}, + {0x0380U, 0x0000000000000000U}, + {0x0388U, 0x0000000000000000U}, + {0x0390U, 0x0012001006003401U}, +}; +#endif + +static void dbsc_setting(void) +{ + uint32_t md=0; + + /* BUFCAM settings */ + //DBSC_DBCAM0CNF0 not set + io_write_32(DBSC_DBCAM0CNF1, 0x00043218); //dbcam0cnf1 + io_write_32(DBSC_DBCAM0CNF2, 0x000000F4); //dbcam0cnf2 + io_write_32(DBSC_DBSCHCNT0, 0x000F0037); //dbschcnt0 + //DBSC_DBSCHCNT1 not set + io_write_32(DBSC_DBSCHSZ0, 0x00000001); //dbschsz0 + io_write_32(DBSC_DBSCHRW0, 0x22421111); //dbschrw0 + + md = (*((volatile uint32_t*)RST_MODEMR) & 0x00080000) >> 19; + + switch (md) { + case 0x0: //MD19=0 : DDR3L-1600, 4GByte(1GByte x4) + /* DDR1600 */ + io_write_32(DBSC_SCFCTST2, 0x012F1123); + break; + default: //MD19=1 : DDR3L-1856, 4GByte(1GByte x4) + /* DDR1856 */ + io_write_32(DBSC_SCFCTST2, 0x012F1123); + break; + } + + /* QoS Settings */ + io_write_32(DBSC_DBSCHQOS_0_0, 0x00000F00); + io_write_32(DBSC_DBSCHQOS_0_1, 0x00000B00); + io_write_32(DBSC_DBSCHQOS_0_2, 0x00000000); + io_write_32(DBSC_DBSCHQOS_0_3, 0x00000000); + //DBSC_DBSCHQOS_1_0 not set + //DBSC_DBSCHQOS_1_1 not set + //DBSC_DBSCHQOS_1_2 not set + //DBSC_DBSCHQOS_1_3 not set + //DBSC_DBSCHQOS_2_0 not set + //DBSC_DBSCHQOS_2_1 not set + //DBSC_DBSCHQOS_2_2 not set + //DBSC_DBSCHQOS_2_3 not set + //DBSC_DBSCHQOS_3_0 not set + //DBSC_DBSCHQOS_3_1 not set + //DBSC_DBSCHQOS_3_2 not set + //DBSC_DBSCHQOS_3_3 not set + io_write_32(DBSC_DBSCHQOS_4_0, 0x00000300); + io_write_32(DBSC_DBSCHQOS_4_1, 0x000002F0); + io_write_32(DBSC_DBSCHQOS_4_2, 0x00000200); + io_write_32(DBSC_DBSCHQOS_4_3, 0x00000100); + //DBSC_DBSCHQOS_5_0 not set + //DBSC_DBSCHQOS_5_1 not set + //DBSC_DBSCHQOS_5_2 not set + //DBSC_DBSCHQOS_5_3 not set + //DBSC_DBSCHQOS_6_0 not set + //DBSC_DBSCHQOS_6_1 not set + //DBSC_DBSCHQOS_6_2 not set + //DBSC_DBSCHQOS_6_3 not set + //DBSC_DBSCHQOS_7_0 not set + //DBSC_DBSCHQOS_7_1 not set + //DBSC_DBSCHQOS_7_2 not set + //DBSC_DBSCHQOS_7_3 not set + //DBSC_DBSCHQOS_8_0 not set + //DBSC_DBSCHQOS_8_1 not set + //DBSC_DBSCHQOS_8_2 not set + //DBSC_DBSCHQOS_8_3 not set + io_write_32(DBSC_DBSCHQOS_9_0, 0x00000300); + io_write_32(DBSC_DBSCHQOS_9_1, 0x000002F0); + io_write_32(DBSC_DBSCHQOS_9_2, 0x00000200); + io_write_32(DBSC_DBSCHQOS_9_3, 0x00000100); + //DBSC_DBSCHQOS_10_0 not set + //DBSC_DBSCHQOS_10_1 not set + //DBSC_DBSCHQOS_10_2 not set + //DBSC_DBSCHQOS_10_3 not set + //DBSC_DBSCHQOS_11_0 not set + //DBSC_DBSCHQOS_11_1 not set + //DBSC_DBSCHQOS_11_2 not set + //DBSC_DBSCHQOS_11_3 not set + //DBSC_DBSCHQOS_12_0 not set + //DBSC_DBSCHQOS_12_1 not set + //DBSC_DBSCHQOS_12_2 not set + //DBSC_DBSCHQOS_12_3 not set + io_write_32(DBSC_DBSCHQOS_13_0, 0x00000100); + io_write_32(DBSC_DBSCHQOS_13_1, 0x000000F0); + io_write_32(DBSC_DBSCHQOS_13_2, 0x000000A0); + io_write_32(DBSC_DBSCHQOS_13_3, 0x00000040); + io_write_32(DBSC_DBSCHQOS_14_0, 0x000000C0); + io_write_32(DBSC_DBSCHQOS_14_1, 0x000000B0); + io_write_32(DBSC_DBSCHQOS_14_2, 0x00000080); + io_write_32(DBSC_DBSCHQOS_14_3, 0x00000040); + io_write_32(DBSC_DBSCHQOS_15_0, 0x00000040); + io_write_32(DBSC_DBSCHQOS_15_1, 0x00000030); + io_write_32(DBSC_DBSCHQOS_15_2, 0x00000020); + io_write_32(DBSC_DBSCHQOS_15_3, 0x00000010); +} + +void qos_init_d3(void) +{ + io_write_32(DBSC_DBSYSCNT0, 0x00001234); + + dbsc_setting(); + + /* DRAM Split Address mapping */ +#if RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH + ERROR("DRAM Split 4ch not supported.(D3)"); + panic(); +#elif RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH + ERROR("DRAM Split 2ch not supported.(D3)"); + panic(); +#elif RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_AUTO + ERROR("DRAM Split Auto not supported.(D3)"); + panic(); +#elif RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_LINEAR +/* NOTICE("BL2: DRAM Split is OFF\n"); */ + /* Split setting(DDR 1ch) */ + io_write_32(AXI_ADSPLCR0, 0x00000000U); + io_write_32(AXI_ADSPLCR3, 0x00000000U); +#else + ERROR("DRAM split is an invalid value.(D3)"); + panic(); +#endif + +#if !(RCAR_QOS_TYPE == RCAR_QOS_NONE) +#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT + NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION); +#endif + + /* Resource Alloc setting */ + io_write_32(RALLOC_RAS, 0x00000020U); + io_write_32(RALLOC_FIXTH, 0x000F0005U); + io_write_32(RALLOC_RAEN, 0x00000001U); + io_write_32(RALLOC_REGGD, 0x00000000U); + io_write_64(RALLOC_DANN, 0x0404020002020201U); + io_write_32(RALLOC_DANT, 0x00100804U); + io_write_32(RALLOC_EC, 0x00000000U); + io_write_64(RALLOC_EMS, 0x0000000000000000U); + io_write_32(RALLOC_FSS, 0x0000000AU); + io_write_32(RALLOC_INSFC, 0xC7840001U); + io_write_32(RALLOC_BERR, 0x00000000U); + io_write_32(RALLOC_EARLYR, 0x00000000U); + io_write_32(RALLOC_RACNT0, 0x00010003U); + io_write_32(RALLOC_TICKDUPL, 0x00000000U); + + /* GPU setting */ + io_write_32(0xFD812030U, 0x00000000U); + + /* MSTAT setting */ + io_write_32(MSTAT_SL_INIT, 0x030500ACU); + io_write_32(MSTAT_REF_ARS, 0x00780000U); + + /* MSTAT SRAM setting */ + { + uint32_t i; + + for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) { + io_write_64(MSTAT_FIX_QOS_BANK0 + mstat_fix[i].addr, + mstat_fix[i].value); + io_write_64(MSTAT_FIX_QOS_BANK1 + mstat_fix[i].addr, + mstat_fix[i].value); + } + for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) { + io_write_64(MSTAT_BE_QOS_BANK0 + mstat_be[i].addr, + mstat_be[i].value); + io_write_64(MSTAT_BE_QOS_BANK1 + mstat_be[i].addr, + mstat_be[i].value); + } + } + + /* 3DG bus Leaf setting */ + io_write_32(0xFD820808U, 0x00001234U); + io_write_32(0xFD820800U, 0x00000000U); + io_write_32(0xFD821800U, 0x00000000U); + io_write_32(0xFD822800U, 0x00000000U); + io_write_32(0xFD823800U, 0x00000000U); + + /* RT bus Leaf setting */ + io_write_32(0xF1300800U, 0x00000003U); + io_write_32(0xF1340800U, 0x00000003U); + io_write_32(0xFFC50800U, 0x00000000U); + io_write_32(0xFFC51800U, 0x00000000U); + + /* Resource Alloc start */ + io_write_32(RALLOC_RAEN, 0x00000001U); + + /* MSTAT start */ + io_write_32(MSTAT_STATQC, 0x00000001U); +#else + NOTICE("BL2: QoS is None\n"); + + /* Resource Alloc setting */ + io_write_32(RALLOC_EC, 0x00000000U); + /* Resource Alloc start */ + io_write_32(RALLOC_RAEN, 0x00000001U); +#endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */ + io_write_32(DBSC_DBSYSCNT0, 0x00000000); +} diff --git a/drivers/staging/renesas/rcar/qos/D3/qos_init_d3.h b/drivers/staging/renesas/rcar/qos/D3/qos_init_d3.h new file mode 100644 index 00000000..968ee7a4 --- /dev/null +++ b/drivers/staging/renesas/rcar/qos/D3/qos_init_d3.h @@ -0,0 +1,13 @@ +/* + * Copyright (c) 2015-2017, Renesas Electronics Corporation + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef QOS_INIT_H_D3__ +#define QOS_INIT_H_D3__ + +void qos_init_d3(void); + +#endif /* QOS_INIT_H_D3__ */ diff --git a/drivers/staging/renesas/rcar/qos/qos.mk b/drivers/staging/renesas/rcar/qos/qos.mk index 9fabc56f..77b3c617 100644 --- a/drivers/staging/renesas/rcar/qos/qos.mk +++ b/drivers/staging/renesas/rcar/qos/qos.mk @@ -35,6 +35,9 @@ else ifdef RCAR_LSI_CUT_COMPAT ifeq (${RCAR_LSI},${RCAR_E3}) BL2_SOURCES += drivers/staging/renesas/rcar/qos/E3/qos_init_e3_v10.c endif + ifeq (${RCAR_LSI},${RCAR_D3}) + BL2_SOURCES += drivers/staging/renesas/rcar/qos/D3/qos_init_d3.c + endif else ifeq (${RCAR_LSI},${RCAR_H3}) ifeq (${LSI_CUT},10) @@ -88,6 +91,9 @@ else BL2_SOURCES += drivers/staging/renesas/rcar/qos/E3/qos_init_e3_v10.c endif endif + ifeq (${RCAR_LSI},${RCAR_D3}) + BL2_SOURCES += drivers/staging/renesas/rcar/qos/E3/qos_init_d3.c + endif endif BL2_SOURCES += drivers/staging/renesas/rcar/qos/qos_init.c diff --git a/drivers/staging/renesas/rcar/qos/qos_init.c b/drivers/staging/renesas/rcar/qos/qos_init.c index affd4250..895f43f5 100644 --- a/drivers/staging/renesas/rcar/qos/qos_init.c +++ b/drivers/staging/renesas/rcar/qos/qos_init.c @@ -40,6 +40,9 @@ #endif #if RCAR_LSI == RCAR_E3 /* E3 */ #include "E3/qos_init_e3_v10.h" +#endif +#if RCAR_LSI == RCAR_D3 /* D3 */ +#include "D3/qos_init_d3.h" #endif /* Product Register */ @@ -50,13 +53,14 @@ #define PRR_PRODUCT_M3 (0x00005200U) /* R-Car M3 */ #define PRR_PRODUCT_M3N (0x00005500U) /* R-Car M3N */ #define PRR_PRODUCT_E3 (0x00005700U) /* R-Car E3 */ +#define PRR_PRODUCT_D3 (0x00005800U) /* R-Car D3 */ #define PRR_PRODUCT_10 (0x00U) #define PRR_PRODUCT_11 (0x01U) #define PRR_PRODUCT_20 (0x10U) #define PRR_PRODUCT_21 (0x11U) #define PRR_PRODUCT_30 (0x20U) -#if !(RCAR_LSI == RCAR_E3) +#if (RCAR_LSI != RCAR_E3) && (RCAR_LSI != RCAR_D3) #define DRAM_CH_CNT 0x04 uint32_t qos_init_ddr_ch; @@ -81,7 +85,7 @@ uint8_t qos_init_ddr_phyvalid; void rcar_qos_init(void) { uint32_t reg; -#if !(RCAR_LSI == RCAR_E3) +#if (RCAR_LSI != RCAR_E3) && (RCAR_LSI != RCAR_D3) uint32_t i; qos_init_ddr_ch = 0; @@ -164,6 +168,18 @@ void rcar_qos_init(void) } #else PRR_PRODUCT_ERR(reg); +#endif + break; + case PRR_PRODUCT_D3: +#if (RCAR_LSI == RCAR_D3) + switch (reg & PRR_CUT_MASK) { + case PRR_PRODUCT_10: + default: + qos_init_d3(); + break; + } +#else + PRR_PRODUCT_ERR(reg); #endif break; default: @@ -245,6 +261,13 @@ void rcar_qos_init(void) PRR_PRODUCT_ERR(reg); } qos_init_m3n_v10(); +#elif RCAR_LSI == RCAR_D3 /* D3 */ + /* D3 Cut 10 or later */ + if ((PRR_PRODUCT_D3) + != (reg & (PRR_PRODUCT_MASK))) { + PRR_PRODUCT_ERR(reg); + } + qos_init_d3(); #elif RCAR_LSI == RCAR_E3 /* E3 */ /* E3 Cut 10 or later */ if ((PRR_PRODUCT_E3) @@ -258,7 +281,7 @@ void rcar_qos_init(void) #endif } -#if !(RCAR_LSI == RCAR_E3) +#if (RCAR_LSI != RCAR_E3) && (RCAR_LSI != RCAR_D3) uint32_t get_refperiod(void) { uint32_t refperiod = QOSWT_WTSET0_CYCLE; -- 2.30.2