From 0b36603c0dbb9b39d0bfe610afbc17c014aff9f4 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 20 Sep 2019 15:13:24 -0500 Subject: [PATCH] drm/amdgpu/display: fix 64 bit divide Use proper helper for 32 bit. Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- .../gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c index 36277bca0326..b1e657e137a9 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c @@ -197,7 +197,9 @@ void dce11_pplib_apply_display_requirements( */ if (ASICREV_IS_VEGA20_P(dc->ctx->asic_id.hw_internal_rev) && (context->stream_count >= 2)) { pp_display_cfg->min_memory_clock_khz = max(pp_display_cfg->min_memory_clock_khz, - (uint32_t) (dc->bw_vbios->high_yclk.value / memory_type_multiplier / 10000)); + (uint32_t) div64_s64( + div64_s64(dc->bw_vbios->high_yclk.value, + memory_type_multiplier), 10000)); } else { pp_display_cfg->min_memory_clock_khz = context->bw_ctx.bw.dce.yclk_khz / memory_type_multiplier; -- 2.30.2