From 09f3e09e9ebcfa7919ca8931a4b5504fadd1f1d3 Mon Sep 17 00:00:00 2001 From: Andy Fleming Date: Wed, 13 Sep 2006 10:34:18 -0500 Subject: [PATCH] Add support for eTSEC 3 & 4 on 8548 CDS * Added support for using eTSEC 3 and eTSEC 4 on the 8548 CDS. This will only work on rev 1.3 boards (but doesn't break older boards) * Cleaned up some comments to reflect the expanded role of tsec in other systems --- board/cds/mpc8548cds/mpc8548cds.c | 32 ++++++++++++++ drivers/tsec.c | 69 ++++++++++++++++++++++++++----- drivers/tsec.h | 17 ++++++++ include/configs/MPC8548CDS.h | 4 +- 4 files changed, 111 insertions(+), 11 deletions(-) diff --git a/board/cds/mpc8548cds/mpc8548cds.c b/board/cds/mpc8548cds/mpc8548cds.c index 6eedb4a209..66219e395b 100644 --- a/board/cds/mpc8548cds/mpc8548cds.c +++ b/board/cds/mpc8548cds/mpc8548cds.c @@ -27,6 +27,7 @@ #include #include #include +#include #include "../common/cadmus.h" #include "../common/eeprom.h" @@ -327,3 +328,34 @@ pci_init_board(void) pci_mpc85xx_init(&hose); #endif } + +int last_stage_init(void) +{ + unsigned int temp; + + /* Change the resistors for the PHY */ + /* This is needed to get the RGMII working for the 1.3+ + * CDS cards */ + if (get_board_version() == 0x13) { + miiphy_write(CONFIG_MPC85XX_TSEC1_NAME, + TSEC1_PHY_ADDR, 29, 18); + + miiphy_read(CONFIG_MPC85XX_TSEC1_NAME, + TSEC1_PHY_ADDR, 30, &temp); + + temp = (temp & 0xf03f); + temp |= 2 << 9; /* 36 ohm */ + temp |= 2 << 6; /* 39 ohm */ + + miiphy_write(CONFIG_MPC85XX_TSEC1_NAME, + TSEC1_PHY_ADDR, 30, temp); + + miiphy_write(CONFIG_MPC85XX_TSEC1_NAME, + TSEC1_PHY_ADDR, 29, 3); + + miiphy_write(CONFIG_MPC85XX_TSEC1_NAME, + TSEC1_PHY_ADDR, 30, 0x8000); + } + + return 0; +} diff --git a/drivers/tsec.c b/drivers/tsec.c index 7ec565ca67..bfc49c4629 100644 --- a/drivers/tsec.c +++ b/drivers/tsec.c @@ -44,9 +44,7 @@ struct tsec_info_struct { /* The tsec_info structure contains 3 values which the * driver uses to determine how to operate a given ethernet - * device. For now, the structure is initialized with the - * knowledge that all current implementations have 2 TSEC - * devices, and one FEC. The information needed is: + * device. The information needed is: * phyaddr - The address of the PHY which is attached to * the given device. * @@ -56,18 +54,16 @@ struct tsec_info_struct { * * phyregidx - This variable specifies which ethernet device * controls the MII Management registers which are connected - * to the PHY. For 8540/8560, only TSEC1 (index 0) has + * to the PHY. For now, only TSEC1 (index 0) has * access to the PHYs, so all of the entries have "0". * * The values specified in the table are taken from the board's * config file in include/configs/. When implementing a new * board with ethernet capability, it is necessary to define: - * TSEC1_PHY_ADDR - * TSEC1_PHYIDX - * TSEC2_PHY_ADDR - * TSEC2_PHYIDX + * TSECn_PHY_ADDR + * TSECn_PHYIDX * - * and for 8560: + * for n = 1,2,3, etc. And for FEC: * FEC_PHY_ADDR * FEC_PHYIDX */ @@ -91,7 +87,7 @@ static struct tsec_info_struct tsec_info[] = { { 0, 0, 0}, # endif # if defined(CONFIG_MPC85XX_TSEC4) || defined(CONFIG_MPC83XX_TSEC4) - {TSEC4_PHY_ADDR, TSEC_REDUCED, TSEC4_PHYIDX}, + {TSEC4_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC4_PHYIDX}, # else { 0, 0, 0}, # endif @@ -805,6 +801,58 @@ struct phy_info phy_info_M88E1111S = { }, }; +static unsigned int m88e1145_setmode(uint mii_reg, struct tsec_private *priv) +{ + unsigned int temp; + uint mii_data = read_phy_reg(priv, mii_reg); + + + /* Setting MIIM_88E1145_PHY_EXT_CR */ + if (priv->flags & TSEC_REDUCED) + return mii_data | + MIIM_M88E1145_RGMII_RX_DELAY | + MIIM_M88E1145_RGMII_TX_DELAY; + else + return mii_data; +} + +static struct phy_info phy_info_M88E1145 = { + 0x01410cd, + "Marvell 88E1145", + 4, + (struct phy_cmd[]) { /* config */ + /* Errata E0, E1 */ + {29, 0x001b, NULL}, + {30, 0x418f, NULL}, + {29, 0x0016, NULL}, + {30, 0xa2da, NULL}, + + /* Reset and configure the PHY */ + {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, + {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, + {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, + {MIIM_88E1011_PHY_SCR, MIIM_88E1011_PHY_MDI_X_AUTO, NULL}, + {MIIM_88E1145_PHY_EXT_CR, 0, &m88e1145_setmode}, + {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, + {MIIM_CONTROL, MIIM_CONTROL_INIT, NULL}, + {miim_end,} + }, + (struct phy_cmd[]) { /* startup */ + /* Status is read once to clear old link state */ + {MIIM_STATUS, miim_read, NULL}, + /* Auto-negotiate */ + {MIIM_STATUS, miim_read, &mii_parse_sr}, + {MIIM_88E1111_PHY_LED_CONTROL, MIIM_88E1111_PHY_LED_DIRECT, NULL}, + /* Read the Status */ + {MIIM_88E1011_PHY_STATUS, miim_read, &mii_parse_88E1011_psr}, + {miim_end,} + }, + (struct phy_cmd[]) { /* shutdown */ + {miim_end,} + }, +}; + + struct phy_info phy_info_cis8204 = { 0x3f11, "Cicada Cis8204", @@ -999,6 +1047,7 @@ struct phy_info *phy_info[] = { &phy_info_cis8204, &phy_info_M88E1011S, &phy_info_M88E1111S, + &phy_info_M88E1145, &phy_info_dm9161, &phy_info_lxt971, &phy_info_dp83865, diff --git a/drivers/tsec.h b/drivers/tsec.h index b55b2992b2..0bfca3a3df 100644 --- a/drivers/tsec.h +++ b/drivers/tsec.h @@ -142,6 +142,23 @@ #define MIIM_88E1011_PHYSTAT_SPDDONE 0x0800 #define MIIM_88E1011_PHYSTAT_LINK 0x0400 +#define MIIM_88E1011_PHY_SCR 0x10 +#define MIIM_88E1011_PHY_MDI_X_AUTO 0x0060 + +/* 88E1111 PHY LED Control Register */ +#define MIIM_88E1111_PHY_LED_CONTROL 24 +#define MIIM_88E1111_PHY_LED_DIRECT 0x4100 +#define MIIM_88E1111_PHY_LED_COMBINE 0x411C + +/* 88E1145 Extended PHY Specific Control Register */ +#define MIIM_88E1145_PHY_EXT_CR 20 +#define MIIM_M88E1145_RGMII_RX_DELAY 0x0080 +#define MIIM_M88E1145_RGMII_TX_DELAY 0x0002 + +#define MIIM_88E1145_PHY_PAGE 29 +#define MIIM_88E1145_PHY_CAL_OV 30 + + /* DM9161 Control register values */ #define MIIM_DM9161_CR_STOP 0x0400 #define MIIM_DM9161_CR_RSTAN 0x1200 diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 37b518cca5..767ab337b3 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -381,7 +381,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_MPC85XX_TSEC2_NAME "eTSEC1" #define CONFIG_MPC85XX_TSEC3 1 #define CONFIG_MPC85XX_TSEC3_NAME "eTSEC2" -#undef CONFIG_MPC85XX_TSEC4 +#define CONFIG_MPC85XX_TSEC4 1 #define CONFIG_MPC85XX_TSEC4_NAME "eTSEC3" #undef CONFIG_MPC85XX_FEC @@ -483,6 +483,8 @@ extern unsigned long get_clock_freq(void); #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD #define CONFIG_HAS_ETH2 #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD +#define CONFIG_HAS_ETH3 +#define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD #endif #define CONFIG_IPADDR 192.168.1.253 -- 2.30.2