From 09851afd33145dc293f0e2900a6f61d0c90f1980 Mon Sep 17 00:00:00 2001 From: John Crispin Date: Mon, 17 Aug 2015 06:15:44 +0000 Subject: [PATCH] ramips: Fix amount of MT7621 pins controlled by spi group The PINS conntrolled by the SPI bits in the GPIO_MODE register is always 7 and not 8 for nand mode. Signed-off-by: Sven Eckelmann SVN-Revision: 46644 --- .../patches-3.18/0012-MIPS-ralink-add-MT7621-support.patch | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/linux/ramips/patches-3.18/0012-MIPS-ralink-add-MT7621-support.patch b/target/linux/ramips/patches-3.18/0012-MIPS-ralink-add-MT7621-support.patch index f08ecb0326..7c29fbeedb 100644 --- a/target/linux/ramips/patches-3.18/0012-MIPS-ralink-add-MT7621-support.patch +++ b/target/linux/ramips/patches-3.18/0012-MIPS-ralink-add-MT7621-support.patch @@ -593,7 +593,7 @@ Signed-off-by: John Crispin +static struct rt2880_pmx_func rgmii2_grp[] = { FUNC("rgmii", 0, 22, 12) }; +static struct rt2880_pmx_func spi_grp[] = { + FUNC("spi", 0, 34, 7), -+ FUNC("nand", 2, 34, 8), ++ FUNC("nand", 2, 34, 7), +}; +static struct rt2880_pmx_func sdhci_grp[] = { + FUNC("sdhci", 0, 41, 8), -- 2.30.2