From 08ec622c465e2c6c0cc4ca577a794342882a0abd Mon Sep 17 00:00:00 2001 From: David Bauer Date: Sun, 6 Jun 2021 19:45:24 +0200 Subject: [PATCH] ramips: make PHY initialization more descriptive The basic mode control register of the ESW PHYs is modified in this codeblock. Use the respective macros to make this code more readable. Signed-off-by: David Bauer (cherry picked from commit 6a15abbc753ca728d798cec9153fc532fce3791d) --- .../ramips/files/drivers/net/ethernet/ralink/gsw_mt7620.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/target/linux/ramips/files/drivers/net/ethernet/ralink/gsw_mt7620.c b/target/linux/ramips/files/drivers/net/ethernet/ralink/gsw_mt7620.c index bd379e6c7d..451881fc73 100644 --- a/target/linux/ramips/files/drivers/net/ethernet/ralink/gsw_mt7620.c +++ b/target/linux/ramips/files/drivers/net/ethernet/ralink/gsw_mt7620.c @@ -13,6 +13,7 @@ */ #include +#include #include #include #include @@ -168,9 +169,9 @@ static void mt7620_hw_init(struct mt7620_gsw *gsw, int mdio_mode) /* turn on all PHYs */ for (i = 0; i <= 4; i++) { - val = _mt7620_mii_read(gsw, gsw->ephy_base + i, 0); - val &= ~BIT(11); - _mt7620_mii_write(gsw, gsw->ephy_base + i, 0, val); + val = _mt7620_mii_read(gsw, gsw->ephy_base + i, MII_BMCR); + val &= ~BMCR_PDOWN; + _mt7620_mii_write(gsw, gsw->ephy_base + i, MII_BMCR, val); } } -- 2.30.2