clk: Allow clock defaults to be set also during re-reloc state
authorAndreas Dannenberg <dannenberg@ti.com>
Wed, 17 Oct 2018 08:13:14 +0000 (13:43 +0530)
committerTom Rini <trini@konsulko.com>
Fri, 16 Nov 2018 18:34:36 +0000 (13:34 -0500)
commite5e06b65ad6563701a069f342ce35a5576f12fd5
tree2a05ed69173b0035068e9f0798d02181d5600868
parent786dc91492b3e759fb22aa88c5d9cc07dc7986f1
clk: Allow clock defaults to be set also during re-reloc state

The earlier commit f4fcba5c5ba ("clk: implement clk_set_defaults()")
which introduced the functionality for setting clock defaults such as
rates and parents will skip the processing when executing in a re-reloc
state. This for example can prevent the assigning of clock parents
when running in SPL code. Go ahead and remove this limitation.

Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
drivers/clk/clk-uclass.c