drm/i915: add support for per-pipe power sequencing on vlv
authorJani Nikula <jani.nikula@intel.com>
Fri, 6 Sep 2013 04:40:05 +0000 (07:40 +0300)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Fri, 6 Sep 2013 08:49:34 +0000 (10:49 +0200)
commitbf13e81b904a37d94d83dd6c3b53a147719a3ead
tree7502bd12e60bfe4a6aaafb31a422da254eb02317
parenta24c144cc92c0cb573677ebb67c2fb946562242e
drm/i915: add support for per-pipe power sequencing on vlv

VLV has per-pipe PP registers. Set up power sequencing on mode set. The
connector init time setup is problematic, since we don't have a pipe at
that time. Cook up something.

v2:
 - use vlv_power_sequencer_pipe() also in _pp_{ctrl,stat}_reg()
 - use PANEL_PORT_SELECT_DPC_VLV (Ville)

v3: make checkpatch happier

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
[danvet: Make checkpatch a bit more happier still ...]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/intel_dp.c