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1 // SPDX-License-Identifier: GPL-2.0-only

2 /*

3 * aQuantia Corporation Network Driver

5 */

7 /* File hw_atl_utils_fw2x.c: Definition of firmware 2.x functions for

8 * Atlantic hardware abstraction layer.

9 */

11 #include "../aq_hw.h"

12 #include "../aq_hw_utils.h"

13 #include "../aq_pci_func.h"

14 #include "../aq_ring.h"

15 #include "../aq_vec.h"

16 #include "../aq_nic.h"

17 #include "hw_atl_utils.h"

18 #include "hw_atl_llh.h"

20 #define HW_ATL_FW2X_MPI_RPC_ADDR 0x334

22 #define HW_ATL_FW2X_MPI_MBOX_ADDR 0x360

23 #define HW_ATL_FW2X_MPI_EFUSE_ADDR 0x364

24 #define HW_ATL_FW2X_MPI_CONTROL_ADDR 0x368

25 #define HW_ATL_FW2X_MPI_CONTROL2_ADDR 0x36C

26 #define HW_ATL_FW2X_MPI_STATE_ADDR 0x370

27 #define HW_ATL_FW2X_MPI_STATE2_ADDR 0x374

29 #define HW_ATL_FW3X_EXT_CONTROL_ADDR 0x378

30 #define HW_ATL_FW3X_EXT_STATE_ADDR 0x37c

32 #define HW_ATL_FW2X_CAP_PAUSE BIT(CAPS_HI_PAUSE)

33 #define HW_ATL_FW2X_CAP_ASYM_PAUSE BIT(CAPS_HI_ASYMMETRIC_PAUSE)

34 #define HW_ATL_FW2X_CAP_SLEEP_PROXY BIT(CAPS_HI_SLEEP_PROXY)

35 #define HW_ATL_FW2X_CAP_WOL BIT(CAPS_HI_WOL)

37 #define HW_ATL_FW2X_CTRL_WAKE_ON_LINK BIT(CTRL_WAKE_ON_LINK)

38 #define HW_ATL_FW2X_CTRL_SLEEP_PROXY BIT(CTRL_SLEEP_PROXY)

39 #define HW_ATL_FW2X_CTRL_WOL BIT(CTRL_WOL)

40 #define HW_ATL_FW2X_CTRL_LINK_DROP BIT(CTRL_LINK_DROP)

41 #define HW_ATL_FW2X_CTRL_PAUSE BIT(CTRL_PAUSE)

42 #define HW_ATL_FW2X_CTRL_TEMPERATURE BIT(CTRL_TEMPERATURE)

43 #define HW_ATL_FW2X_CTRL_ASYMMETRIC_PAUSE BIT(CTRL_ASYMMETRIC_PAUSE)

44 #define HW_ATL_FW2X_CTRL_FORCE_RECONNECT BIT(CTRL_FORCE_RECONNECT)

46 #define HW_ATL_FW2X_CAP_EEE_1G_MASK BIT(CAPS_HI_1000BASET_FD_EEE)

47 #define HW_ATL_FW2X_CAP_EEE_2G5_MASK BIT(CAPS_HI_2P5GBASET_FD_EEE)

48 #define HW_ATL_FW2X_CAP_EEE_5G_MASK BIT(CAPS_HI_5GBASET_FD_EEE)

49 #define HW_ATL_FW2X_CAP_EEE_10G_MASK BIT(CAPS_HI_10GBASET_FD_EEE)

51 #define HAL_ATLANTIC_WOL_FILTERS_COUNT 8

52 #define HAL_ATLANTIC_UTILS_FW2X_MSG_WOL 0x0E

54 struct __packed fw2x_msg_wol_pattern {

55 u8 mask[16];

56 u32 crc;

57 };

59 struct __packed fw2x_msg_wol {

60 u32 msg_id;

61 u8 hw_addr[ETH_ALEN];

62 u8 magic_packet_enabled;

63 u8 filter_count;

64 struct fw2x_msg_wol_pattern filter[HAL_ATLANTIC_WOL_FILTERS_COUNT];

65 u8 link_up_enabled;

66 u8 link_down_enabled;

67 u16 reserved;

68 u32 link_up_timeout;

69 u32 link_down_timeout;

70 };

72 static int aq_fw2x_set_link_speed(struct aq_hw_s *self, u32 speed);

73 static int aq_fw2x_set_state(struct aq_hw_s *self,

74 enum hal_atl_utils_fw_state_e state);

76 static u32 aq_fw2x_mbox_get(struct aq_hw_s *self);

77 static u32 aq_fw2x_rpc_get(struct aq_hw_s *self);

78 static u32 aq_fw2x_state2_get(struct aq_hw_s *self);

80 static int aq_fw2x_init(struct aq_hw_s *self)

81 {

82 int err = 0;

84 /* check 10 times by 1ms */

85 err = readx_poll_timeout_atomic(aq_fw2x_mbox_get,

86 self, self->mbox_addr,

87 self->mbox_addr != 0U,

88 1000U, 10000U);

90 err = readx_poll_timeout_atomic(aq_fw2x_rpc_get,

91 self, self->rpc_addr,

92 self->rpc_addr != 0U,

93 1000U, 100000U);

95 return err;

96 }

98 static int aq_fw2x_deinit(struct aq_hw_s *self)

99 {

100 int err = aq_fw2x_set_link_speed(self, 0);

101

102 if (!err)

103 err = aq_fw2x_set_state(self, MPI_DEINIT);

104

105 return err;

106 }

107

108 static enum hw_atl_fw2x_rate link_speed_mask_2fw2x_ratemask(u32 speed)

109 {

110 enum hw_atl_fw2x_rate rate = 0;

111

112 if (speed & AQ_NIC_RATE_10G)

113 rate |= FW2X_RATE_10G;

114

115 if (speed & AQ_NIC_RATE_5G)

116 rate |= FW2X_RATE_5G;

117

118 if (speed & AQ_NIC_RATE_5GSR)

119 rate |= FW2X_RATE_5G;

120

121 if (speed & AQ_NIC_RATE_2GS)

122 rate |= FW2X_RATE_2G5;

123

124 if (speed & AQ_NIC_RATE_1G)

125 rate |= FW2X_RATE_1G;

126

127 if (speed & AQ_NIC_RATE_100M)

128 rate |= FW2X_RATE_100M;

129

130 return rate;

131 }

132

133 static u32 fw2x_to_eee_mask(u32 speed)

134 {

135 u32 rate = 0;

136

137 if (speed & HW_ATL_FW2X_CAP_EEE_10G_MASK)

138 rate |= AQ_NIC_RATE_EEE_10G;

139 if (speed & HW_ATL_FW2X_CAP_EEE_5G_MASK)

140 rate |= AQ_NIC_RATE_EEE_5G;

141 if (speed & HW_ATL_FW2X_CAP_EEE_2G5_MASK)

142 rate |= AQ_NIC_RATE_EEE_2GS;

143 if (speed & HW_ATL_FW2X_CAP_EEE_1G_MASK)

144 rate |= AQ_NIC_RATE_EEE_1G;

145

146 return rate;

147 }

148

149 static u32 eee_mask_to_fw2x(u32 speed)

150 {

151 u32 rate = 0;

152

153 if (speed & AQ_NIC_RATE_EEE_10G)

154 rate |= HW_ATL_FW2X_CAP_EEE_10G_MASK;

155 if (speed & AQ_NIC_RATE_EEE_5G)

156 rate |= HW_ATL_FW2X_CAP_EEE_5G_MASK;

157 if (speed & AQ_NIC_RATE_EEE_2GS)

158 rate |= HW_ATL_FW2X_CAP_EEE_2G5_MASK;

159 if (speed & AQ_NIC_RATE_EEE_1G)

160 rate |= HW_ATL_FW2X_CAP_EEE_1G_MASK;

161

162 return rate;

163 }

164

165 static int aq_fw2x_set_link_speed(struct aq_hw_s *self, u32 speed)

166 {

167 u32 val = link_speed_mask_2fw2x_ratemask(speed);

168

169 aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL_ADDR, val);

170

171 return 0;

172 }

173

174 static void aq_fw2x_set_mpi_flow_control(struct aq_hw_s *self, u32 *mpi_state)

175 {

176 if (self->aq_nic_cfg->flow_control & AQ_NIC_FC_RX)

177 *mpi_state |= BIT(CAPS_HI_PAUSE);

178 else

179 *mpi_state &= ~BIT(CAPS_HI_PAUSE);

180

181 if (self->aq_nic_cfg->flow_control & AQ_NIC_FC_TX)

182 *mpi_state |= BIT(CAPS_HI_ASYMMETRIC_PAUSE);

183 else

184 *mpi_state &= ~BIT(CAPS_HI_ASYMMETRIC_PAUSE);

185 }

186

187 static void aq_fw2x_upd_eee_rate_bits(struct aq_hw_s *self, u32 *mpi_opts,

188 u32 eee_speeds)

189 {

190 *mpi_opts &= ~(HW_ATL_FW2X_CAP_EEE_1G_MASK |

191 HW_ATL_FW2X_CAP_EEE_2G5_MASK |

192 HW_ATL_FW2X_CAP_EEE_5G_MASK |

193 HW_ATL_FW2X_CAP_EEE_10G_MASK);

194

195 *mpi_opts |= eee_mask_to_fw2x(eee_speeds);

196 }

197

198 static int aq_fw2x_set_state(struct aq_hw_s *self,

199 enum hal_atl_utils_fw_state_e state)

200 {

201 u32 mpi_state = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);

202 struct aq_nic_cfg_s *cfg = self->aq_nic_cfg;

203

204 switch (state) {

205 case MPI_INIT:

206 mpi_state &= ~BIT(CAPS_HI_LINK_DROP);

207 aq_fw2x_upd_eee_rate_bits(self, &mpi_state, cfg->eee_speeds);

208 aq_fw2x_set_mpi_flow_control(self, &mpi_state);

209 break;

210 case MPI_DEINIT:

211 mpi_state |= BIT(CAPS_HI_LINK_DROP);

212 break;

213 case MPI_RESET:

214 case MPI_POWER:

215 /* No actions */

216 break;

217 }

218 aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_state);

219 return 0;

220 }

221

222 static int aq_fw2x_update_link_status(struct aq_hw_s *self)

223 {

224 u32 mpi_state = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_STATE_ADDR);

225 u32 speed = mpi_state & (FW2X_RATE_100M | FW2X_RATE_1G |

226 FW2X_RATE_2G5 | FW2X_RATE_5G | FW2X_RATE_10G);

227 struct aq_hw_link_status_s *link_status = &self->aq_link_status;

228

229 if (speed) {

230 if (speed & FW2X_RATE_10G)

231 link_status->mbps = 10000;

232 else if (speed & FW2X_RATE_5G)

233 link_status->mbps = 5000;

234 else if (speed & FW2X_RATE_2G5)

235 link_status->mbps = 2500;

236 else if (speed & FW2X_RATE_1G)

237 link_status->mbps = 1000;

238 else if (speed & FW2X_RATE_100M)

239 link_status->mbps = 100;

240 else

241 link_status->mbps = 10000;

242 } else {

243 link_status->mbps = 0;

244 }

245

246 return 0;

247 }

248

249 static int aq_fw2x_get_mac_permanent(struct aq_hw_s *self, u8 *mac)

250 {

251 int err = 0;

252 u32 h = 0U;

253 u32 l = 0U;

254 u32 mac_addr[2] = { 0 };

255 u32 efuse_addr = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_EFUSE_ADDR);

256

257 if (efuse_addr != 0) {

258 err = hw_atl_utils_fw_downld_dwords(self,

259 efuse_addr + (40U * 4U),

260 mac_addr,

261 ARRAY_SIZE(mac_addr));

262 if (err)

263 return err;

264 mac_addr[0] = __swab32(mac_addr[0]);

265 mac_addr[1] = __swab32(mac_addr[1]);

266 }

267

268 ether_addr_copy(mac, (u8 *)mac_addr);

269

270 if ((mac[0] & 0x01U) || ((mac[0] | mac[1] | mac[2]) == 0x00U)) {

271 unsigned int rnd = 0;

272

273 get_random_bytes(&rnd, sizeof(unsigned int));

274

275 l = 0xE3000000U | (0xFFFFU & rnd) | (0x00 << 16);

276 h = 0x8001300EU;

277

278 mac[5] = (u8)(0xFFU & l);

279 l >>= 8;

280 mac[4] = (u8)(0xFFU & l);

281 l >>= 8;

282 mac[3] = (u8)(0xFFU & l);

283 l >>= 8;

284 mac[2] = (u8)(0xFFU & l);

285 mac[1] = (u8)(0xFFU & h);

286 h >>= 8;

287 mac[0] = (u8)(0xFFU & h);

288 }

289 return err;

290 }

291

292 static int aq_fw2x_update_stats(struct aq_hw_s *self)

293 {

294 int err = 0;

295 u32 mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);

296 u32 orig_stats_val = mpi_opts & BIT(CAPS_HI_STATISTICS);

297 u32 stats_val;

298

299 /* Toggle statistics bit for FW to update */

300 mpi_opts = mpi_opts ^ BIT(CAPS_HI_STATISTICS);

301 aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts);

302

303 /* Wait FW to report back */

304 err = readx_poll_timeout_atomic(aq_fw2x_state2_get,

305 self, stats_val,

306 orig_stats_val != (stats_val &

307 BIT(CAPS_HI_STATISTICS)),

308 1U, 10000U);

309 if (err)

310 return err;

311

312 return hw_atl_utils_update_stats(self);

313 }

314

315 static int aq_fw2x_get_phy_temp(struct aq_hw_s *self, int *temp)

316 {

317 u32 mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);

318 u32 temp_val = mpi_opts & HW_ATL_FW2X_CTRL_TEMPERATURE;

319 u32 phy_temp_offset;

320 u32 temp_res;

321 int err = 0;

322 u32 val;

323

324 phy_temp_offset = self->mbox_addr +

325 offsetof(struct hw_atl_utils_mbox, info) +

326 offsetof(struct hw_aq_info, phy_temperature);

327 /* Toggle statistics bit for FW to 0x36C.18 (CTRL_TEMPERATURE) */

328 mpi_opts = mpi_opts ^ HW_ATL_FW2X_CTRL_TEMPERATURE;

329 aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts);

330 /* Wait FW to report back */

331 err = readx_poll_timeout_atomic(aq_fw2x_state2_get, self, val,

332 temp_val !=

333 (val & HW_ATL_FW2X_CTRL_TEMPERATURE),

334 1U, 10000U);

335 err = hw_atl_utils_fw_downld_dwords(self, phy_temp_offset,

336 &temp_res, 1);

337

338 if (err)

339 return err;

340

341 /* Convert PHY temperature from 1/256 degree Celsius

342 * to 1/1000 degree Celsius.

343 */

344 *temp = (temp_res & 0xFFFF) * 1000 / 256;

345

346 return 0;

347 }

348

349 static int aq_fw2x_set_wol(struct aq_hw_s *self, u8 *mac)

350 {

351 struct hw_atl_utils_fw_rpc *rpc = NULL;

352 struct offload_info *info = NULL;

353 u32 wol_bits = 0;

354 u32 rpc_size;

355 int err = 0;

356 u32 val;

357

358 if (self->aq_nic_cfg->wol & WAKE_PHY) {

359 aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR,

360 HW_ATL_FW2X_CTRL_LINK_DROP);

361 readx_poll_timeout_atomic(aq_fw2x_state2_get, self, val,

362 (val &

363 HW_ATL_FW2X_CTRL_LINK_DROP) != 0,

364 1000, 100000);

365 wol_bits |= HW_ATL_FW2X_CTRL_WAKE_ON_LINK;

366 }

367

368 if (self->aq_nic_cfg->wol & WAKE_MAGIC) {

369 wol_bits |= HW_ATL_FW2X_CTRL_SLEEP_PROXY |

370 HW_ATL_FW2X_CTRL_WOL;

371

372 err = hw_atl_utils_fw_rpc_wait(self, &rpc);

373 if (err < 0)

374 goto err_exit;

375

376 rpc_size = sizeof(*info) +

377 offsetof(struct hw_atl_utils_fw_rpc, fw2x_offloads);

378 memset(rpc, 0, rpc_size);

379 info = &rpc->fw2x_offloads;

380 memcpy(info->mac_addr, mac, ETH_ALEN);

381 info->len = sizeof(*info);

382

383 err = hw_atl_utils_fw_rpc_call(self, rpc_size);

384 if (err < 0)

385 goto err_exit;

386 }

387

388 aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, wol_bits);

389

390 err_exit:

391 return err;

392 }

393

394 static int aq_fw2x_set_power(struct aq_hw_s *self, unsigned int power_state,

395 u8 *mac)

396 {

397 int err = 0;

398

399 if (self->aq_nic_cfg->wol)

400 err = aq_fw2x_set_wol(self, mac);

401

402 return err;

403 }

404

405 static int aq_fw2x_send_fw_request(struct aq_hw_s *self,

406 const struct hw_fw_request_iface *fw_req,

407 size_t size)

408 {

409 u32 ctrl2, orig_ctrl2;

410 u32 dword_cnt;

411 int err = 0;

412 u32 val;

413

414 /* Write data to drvIface Mailbox */

415 dword_cnt = size / sizeof(u32);

416 if (size % sizeof(u32))

417 dword_cnt++;

418 err = hw_atl_utils_fw_upload_dwords(self, aq_fw2x_rpc_get(self),

419 (void *)fw_req, dword_cnt);

420 if (err < 0)

421 goto err_exit;

422

423 /* Toggle statistics bit for FW to update */

424 ctrl2 = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);

425 orig_ctrl2 = ctrl2 & BIT(CAPS_HI_FW_REQUEST);

426 ctrl2 = ctrl2 ^ BIT(CAPS_HI_FW_REQUEST);

427 aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, ctrl2);

428

429 /* Wait FW to report back */

430 err = readx_poll_timeout_atomic(aq_fw2x_state2_get, self, val,

431 orig_ctrl2 != (val &

432 BIT(CAPS_HI_FW_REQUEST)),

433 1U, 10000U);

434

435 err_exit:

436 return err;

437 }

438

439 static void aq_fw3x_enable_ptp(struct aq_hw_s *self, int enable)

440 {

441 u32 ptp_opts = aq_hw_read_reg(self, HW_ATL_FW3X_EXT_STATE_ADDR);

442 u32 all_ptp_features = BIT(CAPS_EX_PHY_PTP_EN) |

443 BIT(CAPS_EX_PTP_GPIO_EN);

444

445 if (enable)

446 ptp_opts |= all_ptp_features;

447 else

448 ptp_opts &= ~all_ptp_features;

449

450 aq_hw_write_reg(self, HW_ATL_FW3X_EXT_CONTROL_ADDR, ptp_opts);

451 }

452

453 static int aq_fw2x_set_eee_rate(struct aq_hw_s *self, u32 speed)

454 {

455 u32 mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);

456

457 aq_fw2x_upd_eee_rate_bits(self, &mpi_opts, speed);

458

459 aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts);

460

461 return 0;

462 }

463

464 static int aq_fw2x_get_eee_rate(struct aq_hw_s *self, u32 *rate,

465 u32 *supported_rates)

466 {

467 u32 mpi_state;

468 u32 caps_hi;

469 int err = 0;

470 u32 addr = self->mbox_addr + offsetof(struct hw_atl_utils_mbox, info) +

471 offsetof(struct hw_aq_info, caps_hi);

472

473 err = hw_atl_utils_fw_downld_dwords(self, addr, &caps_hi,

474 sizeof(caps_hi) / sizeof(u32));

475

476 if (err)

477 return err;

478

479 *supported_rates = fw2x_to_eee_mask(caps_hi);

480

481 mpi_state = aq_fw2x_state2_get(self);

482 *rate = fw2x_to_eee_mask(mpi_state);

483

484 return err;

485 }

486

487 static int aq_fw2x_renegotiate(struct aq_hw_s *self)

488 {

489 u32 mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);

490

491 mpi_opts |= BIT(CTRL_FORCE_RECONNECT);

492

493 aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts);

494

495 return 0;

496 }

497

498 static int aq_fw2x_set_flow_control(struct aq_hw_s *self)

499 {

500 u32 mpi_state = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);

501

502 aq_fw2x_set_mpi_flow_control(self, &mpi_state);

503

504 aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_state);

505

506 return 0;

507 }

508

509 static u32 aq_fw2x_get_flow_control(struct aq_hw_s *self, u32 *fcmode)

510 {

511 u32 mpi_state = aq_fw2x_state2_get(self);

512

513 if (mpi_state & HW_ATL_FW2X_CAP_PAUSE)

514 if (mpi_state & HW_ATL_FW2X_CAP_ASYM_PAUSE)

515 *fcmode = AQ_NIC_FC_RX;

516 else

517 *fcmode = AQ_NIC_FC_RX | AQ_NIC_FC_TX;

518 else

519 if (mpi_state & HW_ATL_FW2X_CAP_ASYM_PAUSE)

520 *fcmode = AQ_NIC_FC_TX;

521 else

522 *fcmode = 0;

523

524 return 0;

525 }

526

527 static u32 aq_fw2x_mbox_get(struct aq_hw_s *self)

528 {

529 return aq_hw_read_reg(self, HW_ATL_FW2X_MPI_MBOX_ADDR);

530 }

531

532 static u32 aq_fw2x_rpc_get(struct aq_hw_s *self)

533 {

534 return aq_hw_read_reg(self, HW_ATL_FW2X_MPI_RPC_ADDR);

535 }

536

537 static u32 aq_fw2x_state2_get(struct aq_hw_s *self)

538 {

539 return aq_hw_read_reg(self, HW_ATL_FW2X_MPI_STATE2_ADDR);

540 }

541

542 const struct aq_fw_ops aq_fw_2x_ops = {

543 .init = aq_fw2x_init,

544 .deinit = aq_fw2x_deinit,

545 .reset = NULL,

546 .renegotiate = aq_fw2x_renegotiate,

547 .get_mac_permanent = aq_fw2x_get_mac_permanent,

548 .set_link_speed = aq_fw2x_set_link_speed,

549 .set_state = aq_fw2x_set_state,

550 .update_link_status = aq_fw2x_update_link_status,

551 .update_stats = aq_fw2x_update_stats,

552 .get_phy_temp = aq_fw2x_get_phy_temp,

553 .set_power = aq_fw2x_set_power,

554 .set_eee_rate = aq_fw2x_set_eee_rate,

555 .get_eee_rate = aq_fw2x_get_eee_rate,

556 .set_flow_control = aq_fw2x_set_flow_control,

557 .get_flow_control = aq_fw2x_get_flow_control,

558 .send_fw_request = aq_fw2x_send_fw_request,

559 .enable_ptp = aq_fw3x_enable_ptp,

560 };