git.openwrt.org Git - openwrt/staging/blogic.git/blob

1 /* Driver for Realtek RTS51xx USB card reader

2 *

4 *

5 * This program is free software; you can redistribute it and/or modify it

6 * under the terms of the GNU General Public License as published by the

7 * Free Software Foundation; either version 2, or (at your option) any

8 * later version.

9 *

10 * This program is distributed in the hope that it will be useful, but

11 * WITHOUT ANY WARRANTY; without even the implied warranty of

12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU

13 * General Public License for more details.

14 *

15 * You should have received a copy of the GNU General Public License along

16 * with this program; if not, see <http://www.gnu.org/licenses/>.

17 *

18 * Author:

19 * wwang (wei_wang@realsil.com.cn)

20 * No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China

21 * Maintainer:

22 * Edwin Rong (edwin_rong@realsil.com.cn)

23 * No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China

24 */

26 #include <linux/blkdev.h>

27 #include <linux/kthread.h>

28 #include <linux/sched.h>

29 #include <linux/slab.h>

30 #include <linux/vmalloc.h>

32 #include "debug.h"

33 #include "trace.h"

34 #include "rts51x.h"

35 #include "rts51x_transport.h"

36 #include "rts51x_scsi.h"

37 #include "rts51x_card.h"

38 #include "ms.h"

40 static inline void ms_set_err_code(struct rts51x_chip *chip, u8 err_code)

41 {

42 struct ms_info *ms_card = &(chip->ms_card);

44 ms_card->err_code = err_code;

45 }

47 static inline int ms_check_err_code(struct rts51x_chip *chip, u8 err_code)

48 {

49 struct ms_info *ms_card = &(chip->ms_card);

51 return (ms_card->err_code == err_code);

52 }

54 static int ms_parse_err_code(struct rts51x_chip *chip)

55 {

56 TRACE_RET(chip, STATUS_FAIL);

57 }

59 static int ms_transfer_tpc(struct rts51x_chip *chip, u8 trans_mode, u8 tpc,

60 u8 cnt, u8 cfg)

61 {

62 struct ms_info *ms_card = &(chip->ms_card);

63 int retval;

65 RTS51X_DEBUGP("ms_transfer_tpc: tpc = 0x%x\n", tpc);

67 rts51x_init_cmd(chip);

69 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, tpc);

70 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_BYTE_CNT, 0xFF, cnt);

71 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, cfg);

72 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01,

73 PINGPONG_BUFFER);

75 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 0xFF,

76 MS_TRANSFER_START | trans_mode);

77 rts51x_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER, MS_TRANSFER_END,

78 MS_TRANSFER_END);

80 rts51x_add_cmd(chip, READ_REG_CMD, MS_TRANS_CFG, 0, 0);

82 retval = rts51x_send_cmd(chip, MODE_CR, 100);

83 if (retval != STATUS_SUCCESS)

84 TRACE_RET(chip, retval);

86 retval = rts51x_get_rsp(chip, 2, 5000);

87 if (CHECK_MS_TRANS_FAIL(chip, retval)) {

88 rts51x_clear_ms_error(chip);

89 ms_set_err_code(chip, MS_TO_ERROR);

90 TRACE_RET(chip, ms_parse_err_code(chip));

91 }

93 if (!(tpc & 0x08)) { /* Read Packet */

94 /* Check CRC16 & Ready Timeout */

95 if (chip->rsp_buf[1] & MS_CRC16_ERR) {

96 ms_set_err_code(chip, MS_CRC16_ERROR);

97 TRACE_RET(chip, ms_parse_err_code(chip));

98 }

99 } else { /* Write Packet */

100 if (CHK_MSPRO(ms_card) && !(chip->rsp_buf[1] & 0x80)) {

101 if (chip->rsp_buf[1] & (MS_INT_ERR | MS_INT_CMDNK)) {

102 ms_set_err_code(chip, MS_CMD_NK);

103 TRACE_RET(chip, ms_parse_err_code(chip));

104 }

105 }

106 }

107

108 /* Check Timeout of Ready Signal */

109 if (chip->rsp_buf[1] & MS_RDY_TIMEOUT) {

110 rts51x_clear_ms_error(chip);

111 ms_set_err_code(chip, MS_TO_ERROR);

112 TRACE_RET(chip, ms_parse_err_code(chip));

113 }

114

115 return STATUS_SUCCESS;

116 }

117

118 int ms_transfer_data(struct rts51x_chip *chip, u8 trans_mode, u8 tpc,

119 u16 sec_cnt, u8 cfg, int mode_2k, int use_sg, void *buf,

120 int buf_len)

121 {

122 struct ms_info *ms_card = &(chip->ms_card);

123 int retval;

124 u8 val, err_code = 0, flag = 0;

125 enum dma_data_direction dir;

126 unsigned int pipe;

127

128 if (!buf || !buf_len)

129 TRACE_RET(chip, STATUS_FAIL);

130

131 if (trans_mode == MS_TM_AUTO_READ) {

132 pipe = RCV_BULK_PIPE(chip);

133 dir = DMA_FROM_DEVICE;

134 flag = MODE_CDIR;

135 err_code = MS_FLASH_READ_ERROR;

136 } else if (trans_mode == MS_TM_AUTO_WRITE) {

137 pipe = SND_BULK_PIPE(chip);

138 dir = DMA_TO_DEVICE;

139 flag = MODE_CDOR;

140 err_code = MS_FLASH_WRITE_ERROR;

141 } else {

142 TRACE_RET(chip, STATUS_FAIL);

143 }

144

145 rts51x_init_cmd(chip);

146

147 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, tpc);

148 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_SECTOR_CNT_H, 0xFF,

149 (u8) (sec_cnt >> 8));

150 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_SECTOR_CNT_L, 0xFF,

151 (u8) sec_cnt);

152 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, cfg);

153 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01,

154 RING_BUFFER);

155

156 if (mode_2k)

157 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_CFG, MS_2K_SECTOR_MODE,

158 MS_2K_SECTOR_MODE);

159 else

160 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_CFG, MS_2K_SECTOR_MODE,

161 0);

162

163 trans_dma_enable(dir, chip, sec_cnt * 512, DMA_512);

164

165 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 0xFF,

166 MS_TRANSFER_START | trans_mode);

167 rts51x_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER, MS_TRANSFER_END,

168 MS_TRANSFER_END);

169

170 retval = rts51x_send_cmd(chip, flag | STAGE_MS_STATUS, 100);

171 if (retval != STATUS_SUCCESS)

172 TRACE_RET(chip, retval);

173

174 retval =

175 rts51x_transfer_data_rcc(chip, pipe, buf, buf_len, use_sg, NULL,

176 15000, flag);

177 if (retval != STATUS_SUCCESS) {

178 ms_set_err_code(chip, err_code);

179 rts51x_clear_ms_error(chip);

180 TRACE_RET(chip, retval);

181 }

182

183 retval = rts51x_get_rsp(chip, 3, 15000);

184 if (CHECK_MS_TRANS_FAIL(chip, retval)) {

185 ms_set_err_code(chip, err_code);

186 rts51x_clear_ms_error(chip);

187 TRACE_RET(chip, STATUS_FAIL);

188 }

189

190 ms_card->last_rw_int = val = chip->rsp_buf[1];

191 if (val & (MS_INT_CMDNK | MS_INT_ERR | MS_CRC16_ERR | MS_RDY_TIMEOUT))

192 TRACE_RET(chip, STATUS_FAIL);

193

194 return STATUS_SUCCESS;

195 }

196

197 int ms_write_bytes(struct rts51x_chip *chip, u8 tpc, u8 cnt, u8 cfg, u8 *data,

198 int data_len)

199 {

200 struct ms_info *ms_card = &(chip->ms_card);

201 int retval, i;

202

203 if (!data || (data_len < cnt))

204 TRACE_RET(chip, STATUS_ERROR);

205

206 rts51x_init_cmd(chip);

207

208 for (i = 0; i < cnt; i++) {

209 rts51x_add_cmd(chip, WRITE_REG_CMD, PPBUF_BASE2 + i, 0xFF,

210 data[i]);

211 }

212 if (cnt % 2)

213 rts51x_add_cmd(chip, WRITE_REG_CMD, PPBUF_BASE2 + i,

214 0xFF, 0xFF);

215

216 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, tpc);

217 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_BYTE_CNT, 0xFF, cnt);

218 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, cfg);

219 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01,

220 PINGPONG_BUFFER);

221

222 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 0xFF,

223 MS_TRANSFER_START | MS_TM_WRITE_BYTES);

224 rts51x_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER, MS_TRANSFER_END,

225 MS_TRANSFER_END);

226

227 retval = rts51x_send_cmd(chip, MODE_CR, 100);

228 if (retval != STATUS_SUCCESS)

229 TRACE_RET(chip, retval);

230

231 retval = rts51x_get_rsp(chip, 1, 5000);

232 if (CHECK_MS_TRANS_FAIL(chip, retval)) {

233 u8 val = 0;

234

235 rts51x_ep0_read_register(chip, MS_TRANS_CFG, &val);

236 RTS51X_DEBUGP("MS_TRANS_CFG: 0x%02x\n", val);

237

238 rts51x_clear_ms_error(chip);

239

240 if (!(tpc & 0x08)) { /* Read Packet */

241 /* Check CRC16 & Ready Timeout */

242 if (val & MS_CRC16_ERR) {

243 ms_set_err_code(chip, MS_CRC16_ERROR);

244 TRACE_RET(chip, ms_parse_err_code(chip));

245 }

246 } else { /* Write Packet */

247 if (CHK_MSPRO(ms_card) && !(val & 0x80)) {

248 if (val & (MS_INT_ERR | MS_INT_CMDNK)) {

249 ms_set_err_code(chip, MS_CMD_NK);

250 TRACE_RET(chip,

251 ms_parse_err_code(chip));

252 }

253 }

254 }

255

256 /* Check Timeout of Ready Signal */

257 if (val & MS_RDY_TIMEOUT) {

258 ms_set_err_code(chip, MS_TO_ERROR);

259 TRACE_RET(chip, ms_parse_err_code(chip));

260 }

261

262 ms_set_err_code(chip, MS_TO_ERROR);

263 TRACE_RET(chip, ms_parse_err_code(chip));

264 }

265

266 return STATUS_SUCCESS;

267 }

268

269 int ms_read_bytes(struct rts51x_chip *chip, u8 tpc, u8 cnt, u8 cfg, u8 *data,

270 int data_len)

271 {

272 struct ms_info *ms_card = &(chip->ms_card);

273 int retval, i;

274

275 if (!data)

276 TRACE_RET(chip, STATUS_ERROR);

277

278 rts51x_init_cmd(chip);

279

280 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, tpc);

281 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_BYTE_CNT, 0xFF, cnt);

282 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, cfg);

283 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01,

284 PINGPONG_BUFFER);

285

286 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 0xFF,

287 MS_TRANSFER_START | MS_TM_READ_BYTES);

288 rts51x_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER, MS_TRANSFER_END,

289 MS_TRANSFER_END);

290

291 for (i = 0; i < data_len - 1; i++)

292 rts51x_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + i, 0, 0);

293

294 if (data_len % 2)

295 rts51x_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + data_len, 0,

296 0);

297 else

298 rts51x_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + data_len - 1,

299 0, 0);

300

301 retval = rts51x_send_cmd(chip, MODE_CR, 100);

302 if (retval != STATUS_SUCCESS)

303 TRACE_RET(chip, retval);

304

305 retval = rts51x_get_rsp(chip, data_len + 1, 5000);

306 if (CHECK_MS_TRANS_FAIL(chip, retval)) {

307 u8 val = 0;

308

309 rts51x_ep0_read_register(chip, MS_TRANS_CFG, &val);

310 RTS51X_DEBUGP("MS_TRANS_CFG: 0x%02x\n", val);

311

312 rts51x_clear_ms_error(chip);

313

314 if (!(tpc & 0x08)) { /* Read Packet */

315 /* Check CRC16 & Ready Timeout */

316 if (val & MS_CRC16_ERR) {

317 ms_set_err_code(chip, MS_CRC16_ERROR);

318 TRACE_RET(chip, ms_parse_err_code(chip));

319 }

320 } else { /* Write Packet */

321 if (CHK_MSPRO(ms_card) && !(val & 0x80)) {

322 if (val & (MS_INT_ERR | MS_INT_CMDNK)) {

323 ms_set_err_code(chip, MS_CMD_NK);

324 TRACE_RET(chip,

325 ms_parse_err_code(chip));

326 }

327 }

328 }

329

330 /* Check Timeout of Ready Signal */

331 if (val & MS_RDY_TIMEOUT) {

332 ms_set_err_code(chip, MS_TO_ERROR);

333 TRACE_RET(chip, ms_parse_err_code(chip));

334 }

335

336 ms_set_err_code(chip, MS_TO_ERROR);

337 TRACE_RET(chip, ms_parse_err_code(chip));

338 }

339

340 rts51x_read_rsp_buf(chip, 1, data, data_len);

341

342 return STATUS_SUCCESS;

343 }

344

345 int ms_set_rw_reg_addr(struct rts51x_chip *chip,

346 u8 read_start, u8 read_cnt, u8 write_start, u8 write_cnt)

347 {

348 int retval, i;

349 u8 data[4];

350

351 data[0] = read_start;

352 data[1] = read_cnt;

353 data[2] = write_start;

354 data[3] = write_cnt;

355

356 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {

357 retval =

358 ms_write_bytes(chip, SET_RW_REG_ADRS, 4, NO_WAIT_INT, data,

359 4);

360 if (retval == STATUS_SUCCESS)

361 return STATUS_SUCCESS;

362 rts51x_clear_ms_error(chip);

363 }

364

365 TRACE_RET(chip, STATUS_FAIL);

366 }

367

368 static int ms_send_cmd(struct rts51x_chip *chip, u8 cmd, u8 cfg)

369 {

370 u8 data[2];

371

372 data[0] = cmd;

373 data[1] = 0;

374

375 return ms_write_bytes(chip, PRO_SET_CMD, 1, cfg, data, 1);

376 }

377

378 static int ms_set_cmd(struct rts51x_chip *chip,

379 u8 read_start, u8 read_count,

380 u8 write_start, u8 write_count,

381 u8 cmd, u8 cfg, u8 *data, int data_len, u8 *int_stat)

382 {

383 int retval, i;

384 u8 val;

385

386 if (!data || (data_len <= 0) || (data_len > 128)) {

387 RTS51X_DEBUGP("ms_set_cmd (data_len = %d)\n", data_len);

388 TRACE_RET(chip, STATUS_FAIL);

389 }

390

391 retval =

392 ms_set_rw_reg_addr(chip, read_start, read_count, write_start,

393 write_count);

394 if (retval != STATUS_SUCCESS)

395 TRACE_RET(chip, retval);

396

397 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {

398 retval =

399 ms_write_bytes(chip, WRITE_REG, write_count, NO_WAIT_INT,

400 data, data_len);

401 if (retval == STATUS_SUCCESS)

402 break;

403 }

404 if (i == MS_MAX_RETRY_COUNT)

405 TRACE_RET(chip, STATUS_FAIL);

406

407 ms_set_err_code(chip, MS_NO_ERROR);

408

409 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {

410 retval = ms_send_cmd(chip, cmd, WAIT_INT);

411 if (retval == STATUS_SUCCESS)

412 break;

413 }

414 if (i == MS_MAX_RETRY_COUNT)

415 TRACE_RET(chip, STATUS_FAIL);

416 /* GET_INT Register */

417 ms_set_err_code(chip, MS_NO_ERROR);

418 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);

419 if (retval != STATUS_SUCCESS)

420 TRACE_RET(chip, retval);

421

422 if (int_stat)

423 *int_stat = val;

424

425 return STATUS_SUCCESS;

426 }

427

428 #ifdef MS_SPEEDUP

429 static int ms_auto_set_cmd(struct rts51x_chip *chip,

430 u8 read_start, u8 read_count,

431 u8 write_start, u8 write_count,

432 u8 cmd, u8 cfg, u8 *data, int data_len,

433 u8 *int_stat)

434 {

435 int retval;

436 int i;

437

438 if (!data || (data_len <= 0) || (data_len > 128)) {

439 RTS51X_DEBUGP("ms_auto_set_cmd (data_len = %d)\n", data_len);

440 TRACE_RET(chip, STATUS_FAIL);

441 }

442

443 rts51x_init_cmd(chip);

444

445 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_READ_START, 0xFF, read_start);

446 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_READ_COUNT, 0xFF, read_count);

447 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_WRITE_START, 0xFF, write_start);

448 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_WRITE_COUNT, 0xFF, write_count);

449 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_COMMAND, 0xFF, cmd);

450

451 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, cfg);

452 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01,

453 PINGPONG_BUFFER);

454

455 for (i = 0; i < data_len; i++) {

456 rts51x_add_cmd(chip, WRITE_REG_CMD, PPBUF_BASE2 + i, 0xFF,

457 data[i]);

458 }

459

460 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 0xFF,

461 MS_TRANSFER_START | MS_TM_SET_CMD);

462 rts51x_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER, MS_TRANSFER_END,

463 MS_TRANSFER_END);

464

465 retval = rts51x_send_cmd(chip, MODE_CR | STAGE_MS_STATUS, 100);

466 if (retval != STATUS_SUCCESS)

467 TRACE_RET(chip, retval);

468

469 retval = rts51x_get_rsp(chip, 3, 5000);

470

471 if (CHECK_MS_TRANS_FAIL(chip, retval)) {

472 rts51x_clear_ms_error(chip);

473 TRACE_RET(chip, STATUS_FAIL);

474 }

475

476 if (int_stat)

477 *int_stat = chip->rsp_buf[2];

478

479 return STATUS_SUCCESS;

480 }

481 #endif

482

483 static int ms_set_init_para(struct rts51x_chip *chip)

484 {

485 struct ms_info *ms_card = &(chip->ms_card);

486 int retval;

487

488 if (CHK_HG8BIT(ms_card)) {

489 if (chip->asic_code)

490 ms_card->ms_clock = chip->option.asic_ms_hg_clk;

491 else

492 ms_card->ms_clock = chip->option.fpga_ms_hg_clk;

493 } else if (CHK_MSPRO(ms_card) || CHK_MS4BIT(ms_card)) {

494 if (chip->asic_code)

495 ms_card->ms_clock = chip->option.asic_ms_4bit_clk;

496 else

497 ms_card->ms_clock = chip->option.fpga_ms_4bit_clk;

498 } else {

499 if (chip->asic_code)

500 ms_card->ms_clock = 38;

501 else

502 ms_card->ms_clock = CLK_40;

503 }

504

505 retval = switch_clock(chip, ms_card->ms_clock);

506 if (retval != STATUS_SUCCESS)

507 TRACE_RET(chip, retval);

508

509 retval = rts51x_select_card(chip, MS_CARD);

510 if (retval != STATUS_SUCCESS)

511 TRACE_RET(chip, retval);

512

513 return STATUS_SUCCESS;

514 }

515

516 int ms_switch_clock(struct rts51x_chip *chip)

517 {

518 struct ms_info *ms_card = &(chip->ms_card);

519 int retval;

520

521 retval = rts51x_select_card(chip, MS_CARD);

522 if (retval != STATUS_SUCCESS)

523 TRACE_RET(chip, retval);

524

525 retval = switch_clock(chip, ms_card->ms_clock);

526 if (retval != STATUS_SUCCESS)

527 TRACE_RET(chip, retval);

528

529 return STATUS_SUCCESS;

530 }

531

532 static void ms_pull_ctl_disable(struct rts51x_chip *chip)

533 {

534 if (CHECK_PKG(chip, LQFP48)) {

535 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, 0x55);

536 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, 0x55);

537 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, 0x95);

538 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF, 0x55);

539 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF, 0x55);

540 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF, 0xA5);

541 } else {

542 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, 0x65);

543 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, 0x55);

544 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, 0x95);

545 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF, 0x55);

546 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF, 0x56);

547 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF, 0x59);

548 }

549 }

550

551 static void ms_pull_ctl_enable(struct rts51x_chip *chip)

552 {

553 if (CHECK_PKG(chip, LQFP48)) {

554 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, 0x55);

555 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, 0x55);

556 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, 0x95);

557 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF, 0x55);

558 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF, 0x55);

559 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF, 0xA5);

560 } else {

561 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, 0x65);

562 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, 0x55);

563 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, 0x95);

564 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF, 0x55);

565 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF, 0x55);

566 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF, 0x59);

567 }

568 }

569

570 static int ms_prepare_reset(struct rts51x_chip *chip)

571 {

572 struct ms_info *ms_card = &(chip->ms_card);

573 int retval;

574

575 ms_card->ms_type = 0;

576 ms_card->check_ms_flow = 0;

577 ms_card->switch_8bit_fail = 0;

578 ms_card->delay_write.delay_write_flag = 0;

579

580 ms_card->pro_under_formatting = 0;

581

582 rts51x_init_cmd(chip);

583

584 if (chip->asic_code) {

585 ms_pull_ctl_enable(chip);

586 } else {

587 rts51x_add_cmd(chip, WRITE_REG_CMD, FPGA_PULL_CTL,

588 FPGA_MS_PULL_CTL_BIT | 0x20, 0);

589 }

590 /* Tri-state MS output */

591 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_OE, MS_OUTPUT_EN, 0);

592

593 if (!chip->option.FT2_fast_mode) {

594 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PWR_CTL, POWER_MASK,

595 POWER_OFF);

596 }

597

598 retval = rts51x_send_cmd(chip, MODE_C, 100);

599 if (retval != STATUS_SUCCESS)

600 TRACE_RET(chip, retval);

601

602 if (!chip->option.FT2_fast_mode) {

603 wait_timeout(250);

604

605 card_power_on(chip, MS_CARD);

606 wait_timeout(150);

607

608 #ifdef SUPPORT_OCP

609 rts51x_get_card_status(chip, &(chip->card_status));

610 /* get OCP status */

611 chip->ocp_stat = (chip->card_status >> 4) & 0x03;

612

613 if (chip->ocp_stat & (MS_OCP_NOW | MS_OCP_EVER)) {

614 RTS51X_DEBUGP("Over current, OCPSTAT is 0x%x\n",

615 chip->ocp_stat);

616 TRACE_RET(chip, STATUS_FAIL);

617 }

618 #endif

619 }

620

621 rts51x_init_cmd(chip);

622

623 /* Enable MS Output */

624 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_OE, MS_OUTPUT_EN,

625 MS_OUTPUT_EN);

626

627 /* Reset Registers */

628 if (chip->asic_code)

629 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_CFG, 0xFF,

630 SAMPLE_TIME_RISING | PUSH_TIME_DEFAULT |

631 NO_EXTEND_TOGGLE | MS_BUS_WIDTH_1);

632 else

633 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_CFG, 0xFF,

634 SAMPLE_TIME_FALLING | PUSH_TIME_DEFAULT |

635 NO_EXTEND_TOGGLE | MS_BUS_WIDTH_1);

636 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF,

637 NO_WAIT_INT | NO_AUTO_READ_INT_REG);

638

639 retval = rts51x_send_cmd(chip, MODE_C, 100);

640 if (retval != STATUS_SUCCESS)

641 TRACE_RET(chip, retval);

642

643 return ms_set_init_para(chip);

644 }

645

646 static int ms_identify_media_type(struct rts51x_chip *chip, int switch_8bit_bus)

647 {

648 struct ms_info *ms_card = &(chip->ms_card);

649 int retval, i;

650 u8 val;

651

652 retval = ms_set_rw_reg_addr(chip, Pro_StatusReg, 6, SystemParm, 1);

653 if (retval != STATUS_SUCCESS)

654 TRACE_RET(chip, retval);

655

656 /* Get Register form MS-PRO card */

657 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {

658 retval =

659 ms_transfer_tpc(chip, MS_TM_READ_BYTES, READ_REG, 6,

660 NO_WAIT_INT);

661 if (retval == STATUS_SUCCESS)

662 break;

663 }

664 if (i == MS_MAX_RETRY_COUNT)

665 TRACE_RET(chip, STATUS_FAIL);

666

667 RTS51X_READ_REG(chip, PPBUF_BASE2 + 2, &val);

668 RTS51X_DEBUGP("Type register: 0x%x\n", val);

669 if (val != 0x01) {

670 if (val != 0x02)

671 ms_card->check_ms_flow = 1;

672 TRACE_RET(chip, STATUS_FAIL);

673 }

674 /* Category Register */

675 RTS51X_READ_REG(chip, PPBUF_BASE2 + 4, &val);

676 RTS51X_DEBUGP("Category register: 0x%x\n", val);

677 if (val != 0) {

678 ms_card->check_ms_flow = 1;

679 TRACE_RET(chip, STATUS_FAIL);

680 }

681 /* Class Register */

682 RTS51X_READ_REG(chip, PPBUF_BASE2 + 5, &val);

683 RTS51X_DEBUGP("Class register: 0x%x\n", val);

684 if (val == 0) {

685 RTS51X_READ_REG(chip, PPBUF_BASE2, &val);

686 if (val & WRT_PRTCT)

687 chip->card_wp |= MS_CARD;

688 else

689 chip->card_wp &= ~MS_CARD;

690 } else if ((val == 0x01) || (val == 0x02) || (val == 0x03)) {

691 chip->card_wp |= MS_CARD;

692 } else {

693 ms_card->check_ms_flow = 1;

694 TRACE_RET(chip, STATUS_FAIL);

695 }

696

697 ms_card->ms_type |= TYPE_MSPRO;

698

699 /* Check MSPro-HG Card, use IF Mode Register to distinguish */

700 RTS51X_READ_REG(chip, PPBUF_BASE2 + 3, &val);

701 RTS51X_DEBUGP("IF Mode register: 0x%x\n", val);

702 if (val == 0) {

703 ms_card->ms_type &= 0x0F;

704 } else if (val == 7) {

705 if (switch_8bit_bus)

706 ms_card->ms_type |= MS_HG;

707 else

708 ms_card->ms_type &= 0x0F;

709 } else {

710 TRACE_RET(chip, STATUS_FAIL);

711 }

712

713 /* end Procedure to identify Media Type */

714 return STATUS_SUCCESS;

715 }

716

717 static int ms_confirm_cpu_startup(struct rts51x_chip *chip)

718 {

719 int retval, i, k;

720 u8 val;

721

722 /* Confirm CPU StartUp */

723 k = 0;

724 do {

725 if (monitor_card_cd(chip, MS_CARD) == CD_NOT_EXIST)

726 TRACE_RET(chip, STATUS_FAIL);

727

728 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {

729 retval =

730 ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val,

731 1);

732 if (retval == STATUS_SUCCESS)

733 break;

734 }

735 if (i == MS_MAX_RETRY_COUNT)

736 TRACE_RET(chip, STATUS_FAIL);

737

738 if (k > 100)

739 TRACE_RET(chip, STATUS_FAIL);

740 k++;

741 wait_timeout(100);

742 } while (!(val & INT_REG_CED));

743

744 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {

745 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);

746 if (retval == STATUS_SUCCESS)

747 break;

748 }

749 if (i == MS_MAX_RETRY_COUNT)

750 TRACE_RET(chip, STATUS_FAIL);

751

752 if (val & INT_REG_ERR) {

753 if (val & INT_REG_CMDNK) { /* CMDNK = 1 */

754 chip->card_wp |= (MS_CARD);

755 } else { /* CMDNK = 0 */

756 TRACE_RET(chip, STATUS_FAIL);

757 }

758 }

759 /*-- end confirm CPU startup */

760

761 return STATUS_SUCCESS;

762 }

763

764 static int ms_switch_parallel_bus(struct rts51x_chip *chip)

765 {

766 int retval, i;

767 u8 data[2];

768

769 data[0] = PARALLEL_4BIT_IF;

770 data[1] = 0;

771 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {

772 retval =

773 ms_write_bytes(chip, WRITE_REG, 1, NO_WAIT_INT, data, 2);

774 if (retval == STATUS_SUCCESS)

775 break;

776 }

777 if (retval != STATUS_SUCCESS)

778 TRACE_RET(chip, retval);

779

780 return STATUS_SUCCESS;

781 }

782

783 static int ms_switch_8bit_bus(struct rts51x_chip *chip)

784 {

785 struct ms_info *ms_card = &(chip->ms_card);

786 int retval, i;

787 u8 data[2];

788

789 data[0] = PARALLEL_8BIT_IF;

790 data[1] = 0;

791 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {

792 retval =

793 ms_write_bytes(chip, WRITE_REG, 1, NO_WAIT_INT, data, 2);

794 if (retval == STATUS_SUCCESS)

795 break;

796 }

797 if (retval != STATUS_SUCCESS)

798 TRACE_RET(chip, STATUS_FAIL);

799

800 RTS51X_WRITE_REG(chip, MS_CFG, 0x98,

801 MS_BUS_WIDTH_8 | SAMPLE_TIME_FALLING);

802 ms_card->ms_type |= MS_8BIT;

803

804 retval = ms_set_init_para(chip);

805 if (retval != STATUS_SUCCESS)

806 TRACE_RET(chip, retval);

807

808 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {

809 retval =

810 ms_transfer_tpc(chip, MS_TM_READ_BYTES, GET_INT, 1,

811 NO_WAIT_INT);

812 if (retval != STATUS_SUCCESS)

813 TRACE_RET(chip, retval);

814 }

815

816 return STATUS_SUCCESS;

817 }

818

819 static int ms_pro_reset_flow(struct rts51x_chip *chip, int switch_8bit_bus)

820 {

821 struct ms_info *ms_card = &(chip->ms_card);

822 int retval, i;

823

824 for (i = 0; i < 3; i++) {

825 retval = ms_prepare_reset(chip);

826 if (retval != STATUS_SUCCESS)

827 TRACE_RET(chip, retval);

828

829 retval = ms_identify_media_type(chip, switch_8bit_bus);

830 if (retval != STATUS_SUCCESS)

831 TRACE_RET(chip, retval);

832

833 retval = ms_confirm_cpu_startup(chip);

834 if (retval != STATUS_SUCCESS)

835 TRACE_RET(chip, retval);

836

837 retval = ms_switch_parallel_bus(chip);

838 if (retval != STATUS_SUCCESS) {

839 if (monitor_card_cd(chip, MS_CARD) == CD_NOT_EXIST)

840 TRACE_RET(chip, STATUS_FAIL);

841 continue;

842 } else {

843 break;

844 }

845 }

846

847 if (retval != STATUS_SUCCESS)

848 TRACE_RET(chip, retval);

849

850 RTS51X_WRITE_REG(chip, MS_CFG, 0x18, MS_BUS_WIDTH_4);

851

852 RTS51X_WRITE_REG(chip, MS_CFG, PUSH_TIME_ODD, PUSH_TIME_ODD);

853

854 retval = ms_set_init_para(chip);

855 if (retval != STATUS_SUCCESS)

856 TRACE_RET(chip, retval);

857

858 if (CHK_MSHG(ms_card) && switch_8bit_bus) {

859 retval = ms_switch_8bit_bus(chip);

860 if (retval != STATUS_SUCCESS) {

861 ms_card->switch_8bit_fail = 1;

862 TRACE_RET(chip, retval);

863 }

864 }

865

866 return STATUS_SUCCESS;

867 }

868

869 #ifdef XC_POWERCLASS

870 static int msxc_change_power(struct rts51x_chip *chip, u8 mode)

871 {

872 int retval;

873 u8 buf[6];

874

875 ms_cleanup_work(chip);

876

877 /* Set Parameter Register */

878 retval = ms_set_rw_reg_addr(chip, 0, 0, Pro_DataCount1, 6);

879 if (retval != STATUS_SUCCESS)

880 TRACE_RET(chip, retval);

881

882 buf[0] = 0;

883 buf[1] = mode;

884 buf[2] = 0;

885 buf[3] = 0;

886 buf[4] = 0;

887 buf[5] = 0;

888

889 retval = ms_write_bytes(chip, PRO_WRITE_REG, 6, NO_WAIT_INT, buf, 6);

890 if (retval != STATUS_SUCCESS)

891 TRACE_RET(chip, retval);

892

893 retval = ms_send_cmd(chip, XC_CHG_POWER, WAIT_INT);

894 if (retval != STATUS_SUCCESS)

895 TRACE_RET(chip, retval);

896

897 RTS51X_READ_REG(chip, MS_TRANS_CFG, buf);

898 if (buf[0] & (MS_INT_CMDNK | MS_INT_ERR))

899 TRACE_RET(chip, STATUS_FAIL);

900

901 return STATUS_SUCCESS;

902 }

903 #endif

904

905 static int ms_read_attribute_info(struct rts51x_chip *chip)

906 {

907 struct ms_info *ms_card = &(chip->ms_card);

908 int retval, i;

909 u8 val, *buf, class_code, device_type, sub_class, data[16];

910 u16 total_blk = 0, blk_size = 0;

911 #ifdef SUPPORT_MSXC

912 u32 xc_total_blk = 0, xc_blk_size = 0;

913 #endif

914 u32 sys_info_addr = 0, sys_info_size;

915 #ifdef SUPPORT_PCGL_1P18

916 u32 model_name_addr = 0, model_name_size;

917 int found_sys_info = 0, found_model_name = 0;

918 #endif

919

920 retval = ms_set_rw_reg_addr(chip, Pro_IntReg, 2, Pro_SystemParm, 7);

921 if (retval != STATUS_SUCCESS)

922 TRACE_RET(chip, retval);

923

924 if (CHK_MS8BIT(ms_card))

925 data[0] = PARALLEL_8BIT_IF;

926 else

927 data[0] = PARALLEL_4BIT_IF;

928 data[1] = 0;

929

930 data[2] = 0x40;

931 data[3] = 0;

932 data[4] = 0;

933 data[5] = 0;

934 /* Start address 0 */

935 data[6] = 0;

936 data[7] = 0;

937

938 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {

939 retval =

940 ms_write_bytes(chip, PRO_WRITE_REG, 7, NO_WAIT_INT, data,

941 8);

942 if (retval == STATUS_SUCCESS)

943 break;

944 }

945 if (retval != STATUS_SUCCESS)

946 TRACE_RET(chip, retval);

947

948 buf = kmalloc(64 * 512, GFP_KERNEL);

949 if (buf == NULL)

950 TRACE_RET(chip, STATUS_NOMEM);

951

952 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {

953 retval = ms_send_cmd(chip, PRO_READ_ATRB, WAIT_INT);

954 if (retval != STATUS_SUCCESS)

955 continue;

956

957 retval = rts51x_read_register(chip, MS_TRANS_CFG, &val);

958 if (retval != STATUS_SUCCESS) {

959 kfree(buf);

960 TRACE_RET(chip, STATUS_FAIL);

961 }

962 if (!(val & MS_INT_BREQ)) {

963 kfree(buf);

964 TRACE_RET(chip, STATUS_FAIL);

965 }

966

967 retval =

968 ms_transfer_data(chip, MS_TM_AUTO_READ, PRO_READ_LONG_DATA,

969 0x40, WAIT_INT, 0, 0, buf, 64 * 512);

970 if (retval == STATUS_SUCCESS)

971 break;

972 else

973 rts51x_clear_ms_error(chip);

974 }

975 if (retval != STATUS_SUCCESS) {

976 kfree(buf);

977 TRACE_RET(chip, retval);

978 }

979

980 i = 0;

981 do {

982 retval = rts51x_read_register(chip, MS_TRANS_CFG, &val);

983 if (retval != STATUS_SUCCESS) {

984 kfree(buf);

985 TRACE_RET(chip, retval);

986 }

987

988 if ((val & MS_INT_CED) || !(val & MS_INT_BREQ))

989 break;

990

991 retval =

992 ms_transfer_tpc(chip, MS_TM_NORMAL_READ, PRO_READ_LONG_DATA,

993 0, WAIT_INT);

994 if (retval != STATUS_SUCCESS) {

995 kfree(buf);

996 TRACE_RET(chip, retval);

997 }

998

999 i++;

1000 } while (i < 1024);

1001

1002 if (retval != STATUS_SUCCESS) {

1003 kfree(buf);

1004 TRACE_RET(chip, retval);

1005 }

1006

1007 if ((buf[0] != 0xa5) && (buf[1] != 0xc3)) {

1008 /* Signature code is wrong */

1009 kfree(buf);

1010 TRACE_RET(chip, STATUS_FAIL);

1011 }

1012

1013 if ((buf[4] < 1) || (buf[4] > 12)) {

1014 kfree(buf);

1015 TRACE_RET(chip, STATUS_FAIL);

1016 }

1017

1018 for (i = 0; i < buf[4]; i++) {

1019 int cur_addr_off = 16 + i * 12;

1020

1021 #ifdef SUPPORT_MSXC

1022 if ((buf[cur_addr_off + 8] == 0x10)

1023 || (buf[cur_addr_off + 8] == 0x13)) {

1024 #else

1025 if (buf[cur_addr_off + 8] == 0x10) {

1026 #endif

1027 sys_info_addr = ((u32) buf[cur_addr_off + 0] << 24) |

1028 ((u32) buf[cur_addr_off + 1] << 16) |

1029 ((u32) buf[cur_addr_off + 2] << 8) |

1030 buf[cur_addr_off + 3];

1031 sys_info_size =

1032 ((u32) buf[cur_addr_off + 4] << 24) |

1033 ((u32) buf[cur_addr_off + 5] << 16) |

1034 ((u32) buf[cur_addr_off + 6] << 8) |

1035 buf[cur_addr_off + 7];

1036 RTS51X_DEBUGP("sys_info_addr = 0x%x,"

1037 "sys_info_size = 0x%x\n",

1038 sys_info_addr, sys_info_size);

1039 if (sys_info_size != 96) {

1040 kfree(buf);

1041 TRACE_RET(chip, STATUS_FAIL);

1042 }

1043 if (sys_info_addr < 0x1A0) {

1044 kfree(buf);

1045 TRACE_RET(chip, STATUS_FAIL);

1046 }

1047 if ((sys_info_size + sys_info_addr) > 0x8000) {

1048 kfree(buf);

1049 TRACE_RET(chip, STATUS_FAIL);

1050 }

1051 #ifdef SUPPORT_MSXC

1052 if (buf[cur_addr_off + 8] == 0x13)

1053 ms_card->ms_type |= MS_XC;

1054 #endif

1055 #ifdef SUPPORT_PCGL_1P18

1056 found_sys_info = 1;

1057 #else

1058 break;

1059 #endif

1060 }

1061 #ifdef SUPPORT_PCGL_1P18

1062 if (buf[cur_addr_off + 8] == 0x15) {

1063 model_name_addr = ((u32) buf[cur_addr_off + 0] << 24) |

1064 ((u32) buf[cur_addr_off + 1] << 16) |

1065 ((u32) buf[cur_addr_off + 2] << 8) |

1066 buf[cur_addr_off + 3];

1067 model_name_size =

1068 ((u32) buf[cur_addr_off + 4] << 24) |

1069 ((u32) buf[cur_addr_off + 5] << 16) |

1070 ((u32) buf[cur_addr_off + 6] << 8) |

1071 buf[cur_addr_off + 7];

1072 RTS51X_DEBUGP("model_name_addr = 0x%x,"

1073 "model_name_size = 0x%x\n",

1074 model_name_addr, model_name_size);

1075 if (model_name_size != 48) {

1076 kfree(buf);

1077 TRACE_RET(chip, STATUS_FAIL);

1078 }

1079 if (model_name_addr < 0x1A0) {

1080 kfree(buf);

1081 TRACE_RET(chip, STATUS_FAIL);

1082 }

1083 if ((model_name_size + model_name_addr) > 0x8000) {

1084 kfree(buf);

1085 TRACE_RET(chip, STATUS_FAIL);

1086 }

1087

1088 found_model_name = 1;

1089 }

1090

1091 if (found_sys_info && found_model_name)

1092 break;

1093 #endif

1094 }

1095

1096 if (i == buf[4]) {

1097 kfree(buf);

1098 TRACE_RET(chip, STATUS_FAIL);

1099 }

1100

1101 class_code = buf[sys_info_addr + 0];

1102 device_type = buf[sys_info_addr + 56];

1103 sub_class = buf[sys_info_addr + 46];

1104 #ifdef SUPPORT_MSXC

1105 if (CHK_MSXC(ms_card)) {

1106 xc_total_blk = ((u32) buf[sys_info_addr + 6] << 24) |

1107 ((u32) buf[sys_info_addr + 7] << 16) |

1108 ((u32) buf[sys_info_addr + 8] << 8) |

1109 buf[sys_info_addr + 9];

1110 xc_blk_size = ((u32) buf[sys_info_addr + 32] << 24) |

1111 ((u32) buf[sys_info_addr + 33] << 16) |

1112 ((u32) buf[sys_info_addr + 34] << 8) |

1113 buf[sys_info_addr + 35];

1114 RTS51X_DEBUGP("xc_total_blk = 0x%x, xc_blk_size = 0x%x\n",

1115 xc_total_blk, xc_blk_size);

1116 } else {

1117 total_blk =

1118 ((u16) buf[sys_info_addr + 6] << 8) | buf[sys_info_addr +

1119 7];

1120 blk_size =

1121 ((u16) buf[sys_info_addr + 2] << 8) | buf[sys_info_addr +

1122 3];

1123 RTS51X_DEBUGP("total_blk = 0x%x, blk_size = 0x%x\n", total_blk,

1124 blk_size);

1125 }

1126 #else

1127 total_blk =

1128 ((u16) buf[sys_info_addr + 6] << 8) | buf[sys_info_addr + 7];

1129 blk_size = ((u16) buf[sys_info_addr + 2] << 8) | buf[sys_info_addr + 3];

1130 RTS51X_DEBUGP("total_blk = 0x%x, blk_size = 0x%x\n", total_blk,

1131 blk_size);

1132 #endif

1133

1134 RTS51X_DEBUGP("class_code = 0x%x, device_type = 0x%x,"

1135 "sub_class = 0x%x\n",

1136 class_code, device_type, sub_class);

1137

1138 memcpy(ms_card->raw_sys_info, buf + sys_info_addr, 96);

1139 #ifdef SUPPORT_PCGL_1P18

1140 memcpy(ms_card->raw_model_name, buf + model_name_addr, 48);

1141 #endif

1142

1143 kfree(buf);

1144

1145 /* Confirm System Information */

1146 #ifdef SUPPORT_MSXC

1147 if (CHK_MSXC(ms_card)) {

1148 if (class_code != 0x03)

1149 TRACE_RET(chip, STATUS_FAIL);

1150 } else {

1151 if (class_code != 0x02)

1152 TRACE_RET(chip, STATUS_FAIL);

1153 }

1154 #else

1155 if (class_code != 0x02)

1156 TRACE_RET(chip, STATUS_FAIL);

1157 #endif

1158

1159 if (device_type != 0x00) {

1160 if ((device_type == 0x01) || (device_type == 0x02)

1161 || (device_type == 0x03))

1162 chip->card_wp |= MS_CARD;

1163 else

1164 TRACE_RET(chip, STATUS_FAIL);

1165 }

1166 if (sub_class & 0xC0)

1167 TRACE_RET(chip, STATUS_FAIL);

1168

1169 RTS51X_DEBUGP("class_code: 0x%x, device_type: 0x%x, sub_class: 0x%x\n",

1170 class_code, device_type, sub_class);

1171

1172 #ifdef SUPPORT_MSXC

1173 if (CHK_MSXC(ms_card)) {

1174 chip->capacity[chip->card2lun[MS_CARD]] = ms_card->capacity =

1175 xc_total_blk * xc_blk_size;

1176 } else {

1177 chip->capacity[chip->card2lun[MS_CARD]] = ms_card->capacity =

1178 total_blk * blk_size;

1179 }

1180 #else

1181 chip->capacity[chip->card2lun[MS_CARD]] = ms_card->capacity =

1182 total_blk * blk_size;

1183 #endif

1184

1185 return STATUS_SUCCESS;

1186 }

1187

1188 #ifdef SUPPORT_MAGIC_GATE

1189 int mg_set_tpc_para_sub(struct rts51x_chip *chip, int type, u8 mg_entry_num);

1190 #endif

1191

1192 static int reset_ms_pro(struct rts51x_chip *chip)

1193 {

1194 struct ms_info *ms_card = &(chip->ms_card);

1195 int retval;

1196 #ifdef XC_POWERCLASS

1197 u8 change_power_class = 2;

1198 #endif

1199

1200 #ifdef XC_POWERCLASS

1201 Retry:

1202 #endif

1203 retval = ms_pro_reset_flow(chip, 1);

1204 if (retval != STATUS_SUCCESS) {

1205 if (ms_card->switch_8bit_fail) {

1206 retval = ms_pro_reset_flow(chip, 0);

1207 if (retval != STATUS_SUCCESS)

1208 TRACE_RET(chip, retval);

1209 } else {

1210 TRACE_RET(chip, retval);

1211 }

1212 }

1213

1214 retval = ms_read_attribute_info(chip);

1215 if (retval != STATUS_SUCCESS)

1216 TRACE_RET(chip, retval);

1217 #ifdef XC_POWERCLASS

1218 if (CHK_HG8BIT(ms_card))

1219 change_power_class = 0;

1220

1221 if (change_power_class && CHK_MSXC(ms_card)) {

1222 u8 power_class_mode = (ms_card->raw_sys_info[46] & 0x18) >> 3;

1223 RTS51X_DEBUGP("power_class_mode = 0x%x", power_class_mode);

1224 if (change_power_class > power_class_mode)

1225 change_power_class = power_class_mode;

1226 if (change_power_class) {

1227 retval = msxc_change_power(chip, change_power_class);

1228 if (retval != STATUS_SUCCESS) {

1229 change_power_class--;

1230 goto Retry;

1231 }

1232 }

1233 }

1234 #endif

1235

1236 #ifdef SUPPORT_MAGIC_GATE

1237 retval = mg_set_tpc_para_sub(chip, 0, 0);

1238 if (retval != STATUS_SUCCESS)

1239 TRACE_RET(chip, retval);

1240 #endif

1241

1242 if (CHK_HG8BIT(ms_card))

1243 chip->card_bus_width[chip->card2lun[MS_CARD]] = 8;

1244 else

1245 chip->card_bus_width[chip->card2lun[MS_CARD]] = 4;

1246

1247 return STATUS_SUCCESS;

1248 }

1249

1250 static int ms_read_status_reg(struct rts51x_chip *chip)

1251 {

1252 int retval;

1253 u8 val[2];

1254

1255 retval = ms_set_rw_reg_addr(chip, StatusReg0, 2, 0, 0);

1256 if (retval != STATUS_SUCCESS)

1257 TRACE_RET(chip, retval);

1258

1259 retval = ms_read_bytes(chip, READ_REG, 2, NO_WAIT_INT, val, 2);

1260 if (retval != STATUS_SUCCESS)

1261 TRACE_RET(chip, retval);

1262 if (val[1] & (STS_UCDT | STS_UCEX | STS_UCFG)) {

1263 ms_set_err_code(chip, MS_FLASH_READ_ERROR);

1264 TRACE_RET(chip, STATUS_FAIL);

1265 }

1266

1267 return STATUS_SUCCESS;

1268 }

1269

1270 static int ms_check_boot_block(struct rts51x_chip *chip, u16 block_addr)

1271 {

1272 struct ms_info *ms_card = &(chip->ms_card);

1273 int retval;

1274 u8 extra[MS_EXTRA_SIZE], data[10], val = 0;

1275

1276 if (CHK_MS4BIT(ms_card)) {

1277 /* Parallel interface */

1278 data[0] = 0x88;

1279 } else {

1280 /* Serial interface */

1281 data[0] = 0x80;

1282 }

1283 /* Block Address */

1284 data[1] = 0;

1285 data[2] = (u8) (block_addr >> 8);

1286 data[3] = (u8) block_addr;

1287 /* Page Number

1288 * Extra data access mode */

1289 data[4] = 0x40;

1290 data[5] = 0;

1291

1292 retval = ms_set_cmd(chip, OverwriteFlag, MS_EXTRA_SIZE, SystemParm, 6,

1293 BLOCK_READ, WAIT_INT, data, 6, &val);

1294 if (retval != STATUS_SUCCESS)

1295 TRACE_RET(chip, retval);

1296

1297 if (val & INT_REG_CMDNK) {

1298 ms_set_err_code(chip, MS_CMD_NK);

1299 TRACE_RET(chip, STATUS_FAIL);

1300 }

1301 if (val & INT_REG_CED) {

1302 if (val & INT_REG_ERR) {

1303 retval = ms_read_status_reg(chip);

1304 if (retval != STATUS_SUCCESS)

1305 TRACE_RET(chip, retval);

1306 retval =

1307 ms_set_rw_reg_addr(chip, OverwriteFlag,

1308 MS_EXTRA_SIZE, SystemParm, 6);

1309 if (retval != STATUS_SUCCESS)

1310 TRACE_RET(chip, retval);

1311 }

1312 }

1313

1314 retval =

1315 ms_read_bytes(chip, READ_REG, MS_EXTRA_SIZE, NO_WAIT_INT, extra,

1316 MS_EXTRA_SIZE);

1317 if (retval != STATUS_SUCCESS)

1318 TRACE_RET(chip, retval);

1319

1320 if (!(extra[0] & BLOCK_OK) || (extra[1] & NOT_BOOT_BLOCK))

1321 TRACE_RET(chip, STATUS_FAIL);

1322

1323 return STATUS_SUCCESS;

1324 }

1325

1326 static int ms_read_extra_data(struct rts51x_chip *chip,

1327 u16 block_addr, u8 page_num, u8 *buf,

1328 int buf_len)

1329 {

1330 struct ms_info *ms_card = &(chip->ms_card);

1331 int retval;

1332 u8 val = 0, data[10];

1333

1334 if (CHK_MS4BIT(ms_card)) {

1335 /* Parallel interface */

1336 data[0] = 0x88;

1337 } else {

1338 /* Serial interface */

1339 data[0] = 0x80;

1340 }

1341 /* Block Address */

1342 data[1] = 0;

1343 data[2] = (u8) (block_addr >> 8);

1344 data[3] = (u8) block_addr;

1345 /* Page Number

1346 * Extra data access mode */

1347 data[4] = 0x40;

1348 data[5] = page_num;

1349

1350 #ifdef MS_SPEEDUP

1351 retval =

1352 ms_auto_set_cmd(chip, OverwriteFlag, MS_EXTRA_SIZE, SystemParm, 6,

1353 BLOCK_READ, WAIT_INT, data, 6, &val);

1354 #else

1355 retval = ms_set_cmd(chip, OverwriteFlag, MS_EXTRA_SIZE, SystemParm, 6,

1356 BLOCK_READ, WAIT_INT, data, 6, &val);

1357 #endif

1358 if (retval != STATUS_SUCCESS)

1359 TRACE_RET(chip, retval);

1360

1361 if (val & INT_REG_CMDNK) {

1362 ms_set_err_code(chip, MS_CMD_NK);

1363 TRACE_RET(chip, STATUS_FAIL);

1364 }

1365 if (val & INT_REG_CED) {

1366 if (val & INT_REG_ERR) {

1367 retval = ms_read_status_reg(chip);

1368 if (retval != STATUS_SUCCESS)

1369 TRACE_RET(chip, retval);

1370 retval =

1371 ms_set_rw_reg_addr(chip, OverwriteFlag,

1372 MS_EXTRA_SIZE, SystemParm, 6);

1373 if (retval != STATUS_SUCCESS)

1374 TRACE_RET(chip, retval);

1375 }

1376 }

1377

1378 retval =

1379 ms_read_bytes(chip, READ_REG, MS_EXTRA_SIZE, NO_WAIT_INT, data,

1380 MS_EXTRA_SIZE);

1381 if (retval != STATUS_SUCCESS)

1382 TRACE_RET(chip, retval);

1383

1384 if (buf && buf_len) {

1385 if (buf_len > MS_EXTRA_SIZE)

1386 buf_len = MS_EXTRA_SIZE;

1387 memcpy(buf, data, buf_len);

1388 }

1389

1390 return STATUS_SUCCESS;

1391 }

1392

1393 static int ms_write_extra_data(struct rts51x_chip *chip,

1394 u16 block_addr, u8 page_num, u8 *buf,

1395 int buf_len)

1396 {

1397 struct ms_info *ms_card = &(chip->ms_card);

1398 int retval, i;

1399 u8 val = 0, data[16];

1400

1401 if (!buf || (buf_len < MS_EXTRA_SIZE))

1402 TRACE_RET(chip, STATUS_FAIL);

1403 /* Write REG */

1404 if (CHK_MS4BIT(ms_card)) {

1405 /* Parallel interface */

1406 data[0] = 0x88;

1407 } else {

1408 /* Serial interface */

1409 data[0] = 0x80;

1410 }

1411 /* Block Address */

1412 data[1] = 0;

1413 data[2] = (u8) (block_addr >> 8);

1414 data[3] = (u8) block_addr;

1415 /* Page Number

1416 * Extra data access mode */

1417 data[4] = 0x40;

1418 data[5] = page_num;

1419

1420 for (i = 6; i < MS_EXTRA_SIZE + 6; i++)

1421 data[i] = buf[i - 6];

1422

1423 #ifdef MS_SPEEDUP

1424 retval =

1425 ms_auto_set_cmd(chip, OverwriteFlag, MS_EXTRA_SIZE, SystemParm,

1426 6 + MS_EXTRA_SIZE, BLOCK_WRITE, WAIT_INT, data, 16,

1427 &val);

1428 #else

1429 retval =

1430 ms_set_cmd(chip, OverwriteFlag, MS_EXTRA_SIZE, SystemParm,

1431 6 + MS_EXTRA_SIZE, BLOCK_WRITE, WAIT_INT, data, 16,

1432 &val);

1433 #endif

1434 if (retval != STATUS_SUCCESS)

1435 TRACE_RET(chip, retval);

1436

1437 if (val & INT_REG_CMDNK) {

1438 ms_set_err_code(chip, MS_CMD_NK);

1439 TRACE_RET(chip, STATUS_FAIL);

1440 }

1441 if (val & INT_REG_CED) {

1442 if (val & INT_REG_ERR) {

1443 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR);

1444 TRACE_RET(chip, STATUS_FAIL);

1445 }

1446 }

1447

1448 return STATUS_SUCCESS;

1449 }

1450

1451 static int ms_read_page(struct rts51x_chip *chip, u16 block_addr, u8 page_num)

1452 {

1453 struct ms_info *ms_card = &(chip->ms_card);

1454 int retval;

1455 u8 val = 0, data[6];

1456

1457 if (CHK_MS4BIT(ms_card)) {

1458 /* Parallel interface */

1459 data[0] = 0x88;

1460 } else {

1461 /* Serial interface */

1462 data[0] = 0x80;

1463 }

1464 /* Block Address */

1465 data[1] = 0;

1466 data[2] = (u8) (block_addr >> 8);

1467 data[3] = (u8) block_addr;

1468 /* Page Number

1469 * Single page access mode */

1470 data[4] = 0x20;

1471 data[5] = page_num;

1472

1473 retval = ms_set_cmd(chip, OverwriteFlag, MS_EXTRA_SIZE, SystemParm, 6,

1474 BLOCK_READ, WAIT_INT, data, 6, &val);

1475 if (retval != STATUS_SUCCESS)

1476 TRACE_RET(chip, retval);

1477

1478 if (val & INT_REG_CMDNK) {

1479 ms_set_err_code(chip, MS_CMD_NK);

1480 TRACE_RET(chip, STATUS_FAIL);

1481 }

1482

1483 if (val & INT_REG_CED) {

1484 if (val & INT_REG_ERR) {

1485 if (!(val & INT_REG_BREQ)) {

1486 ms_set_err_code(chip, MS_FLASH_READ_ERROR);

1487 TRACE_RET(chip, STATUS_FAIL);

1488 }

1489 retval = ms_read_status_reg(chip);

1490 if (retval != STATUS_SUCCESS)

1491 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR);

1492 } else {

1493 if (!(val & INT_REG_BREQ)) {

1494 ms_set_err_code(chip, MS_BREQ_ERROR);

1495 TRACE_RET(chip, STATUS_FAIL);

1496 }

1497 }

1498 }

1499

1500 retval =

1501 ms_transfer_tpc(chip, MS_TM_NORMAL_READ, READ_PAGE_DATA, 0,

1502 NO_WAIT_INT);

1503 if (retval != STATUS_SUCCESS)

1504 TRACE_RET(chip, retval);

1505 if (ms_check_err_code(chip, MS_FLASH_WRITE_ERROR))

1506 TRACE_RET(chip, STATUS_FAIL);

1507

1508 return STATUS_SUCCESS;

1509 }

1510

1511 static int ms_set_bad_block(struct rts51x_chip *chip, u16 phy_blk)

1512 {

1513 struct ms_info *ms_card = &(chip->ms_card);

1514 int retval;

1515 u8 val = 0, data[8], extra[MS_EXTRA_SIZE];

1516

1517 retval = ms_read_extra_data(chip, phy_blk, 0, extra, MS_EXTRA_SIZE);

1518 if (retval != STATUS_SUCCESS)

1519 TRACE_RET(chip, retval);

1520

1521 ms_set_err_code(chip, MS_NO_ERROR);

1522

1523 if (CHK_MS4BIT(ms_card)) {

1524 /* Parallel interface */

1525 data[0] = 0x88;

1526 } else {

1527 /* Serial interface */

1528 data[0] = 0x80;

1529 }

1530 /* Block Address */

1531 data[1] = 0;

1532 data[2] = (u8) (phy_blk >> 8);

1533 data[3] = (u8) phy_blk;

1534 data[4] = 0x80;

1535 data[5] = 0;

1536 data[6] = extra[0] & 0x7F;

1537 data[7] = 0xFF;

1538

1539 #ifdef MS_SPEEDUP

1540 retval = ms_set_cmd(chip, OverwriteFlag, MS_EXTRA_SIZE, SystemParm, 7,

1541 BLOCK_WRITE, WAIT_INT, data, 7, &val);

1542 #else

1543 retval = ms_set_cmd(chip, OverwriteFlag, MS_EXTRA_SIZE, SystemParm, 7,

1544 BLOCK_WRITE, WAIT_INT, data, 7, &val);

1545 #endif

1546 if (retval != STATUS_SUCCESS)

1547 TRACE_RET(chip, retval);

1548

1549 if (val & INT_REG_CMDNK) {

1550 ms_set_err_code(chip, MS_CMD_NK);

1551 TRACE_RET(chip, STATUS_FAIL);

1552 }

1553

1554 if (val & INT_REG_CED) {

1555 if (val & INT_REG_ERR) {

1556 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR);

1557 TRACE_RET(chip, STATUS_FAIL);

1558 }

1559 }

1560

1561 return STATUS_SUCCESS;

1562 }

1563

1564 static int ms_erase_block(struct rts51x_chip *chip, u16 phy_blk)

1565 {

1566 struct ms_info *ms_card = &(chip->ms_card);

1567 int retval, i = 0;

1568 u8 val = 0, data[6];

1569

1570 retval =

1571 ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE, SystemParm,

1572 6);

1573 if (retval != STATUS_SUCCESS)

1574 TRACE_RET(chip, retval);

1575

1576 ms_set_err_code(chip, MS_NO_ERROR);

1577

1578 if (CHK_MS4BIT(ms_card)) {

1579 /* Parallel interface */

1580 data[0] = 0x88;

1581 } else {

1582 /* Serial interface */

1583 data[0] = 0x80;

1584 }

1585 /* Block Address */

1586 data[1] = 0;

1587 data[2] = (u8) (phy_blk >> 8);

1588 data[3] = (u8) phy_blk;

1589 data[4] = 0;

1590 data[5] = 0;

1591

1592 ERASE_RTY:

1593 #ifdef MS_SPEEDUP

1594 retval =

1595 ms_auto_set_cmd(chip, OverwriteFlag, MS_EXTRA_SIZE, SystemParm, 6,

1596 BLOCK_ERASE, WAIT_INT, data, 6, &val);

1597 #else

1598 retval = ms_set_cmd(chip, OverwriteFlag, MS_EXTRA_SIZE, SystemParm, 6,

1599 BLOCK_ERASE, WAIT_INT, data, 6, &val);

1600 #endif

1601

1602 if (val & INT_REG_CMDNK) {

1603 if (i < 3) {

1604 i++;

1605 goto ERASE_RTY;

1606 }

1607 ms_set_err_code(chip, MS_CMD_NK);

1608 ms_set_bad_block(chip, phy_blk);

1609 TRACE_RET(chip, STATUS_FAIL);

1610 }

1611

1612 if (val & INT_REG_CED) {

1613 if (val & INT_REG_ERR) {

1614 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR);

1615 TRACE_RET(chip, STATUS_FAIL);

1616 }

1617 }

1618

1619 return STATUS_SUCCESS;

1620 }

1621

1622 static void ms_set_page_status(u16 log_blk, u8 type, u8 *extra, int extra_len)

1623 {

1624 if (!extra || (extra_len < MS_EXTRA_SIZE))

1625 return;

1626

1627 memset(extra, 0xFF, MS_EXTRA_SIZE);

1628

1629 if (type == setPS_NG)

1630 extra[0] = 0xB8;

1631 else

1632 extra[0] = 0x98;

1633

1634 extra[2] = (u8) (log_blk >> 8);

1635 extra[3] = (u8) log_blk;

1636 }

1637

1638 static int ms_init_page(struct rts51x_chip *chip, u16 phy_blk, u16 log_blk,

1639 u8 start_page, u8 end_page)

1640 {

1641 int retval;

1642 u8 extra[MS_EXTRA_SIZE], i;

1643

1644 memset(extra, 0xff, MS_EXTRA_SIZE);

1645

1646 extra[0] = 0xf8; /* Block, page OK, data erased */

1647 extra[1] = 0xff;

1648 extra[2] = (u8) (log_blk >> 8);

1649 extra[3] = (u8) log_blk;

1650

1651 for (i = start_page; i < end_page; i++) {

1652 if (monitor_card_cd(chip, MS_CARD) == CD_NOT_EXIST)

1653 TRACE_RET(chip, STATUS_FAIL);

1654

1655 retval =

1656 ms_write_extra_data(chip, phy_blk, i, extra, MS_EXTRA_SIZE);

1657 if (retval != STATUS_SUCCESS)

1658 TRACE_RET(chip, retval);

1659 }

1660

1661 return STATUS_SUCCESS;

1662 }

1663

1664 static int ms_copy_page(struct rts51x_chip *chip, u16 old_blk, u16 new_blk,

1665 u16 log_blk, u8 start_page, u8 end_page)

1666 {

1667 struct ms_info *ms_card = &(chip->ms_card);

1668 int retval, rty_cnt, uncorrect_flag = 0;

1669 u8 extra[MS_EXTRA_SIZE], val, i, j, data[16];

1670

1671 RTS51X_DEBUGP("Copy page from 0x%x to 0x%x, logical block is 0x%x\n",

1672 old_blk, new_blk, log_blk);

1673 RTS51X_DEBUGP("start_page = %d, end_page = %d\n", start_page,

1674 end_page);

1675

1676 retval = ms_read_extra_data(chip, new_blk, 0, extra, MS_EXTRA_SIZE);

1677 if (retval != STATUS_SUCCESS)

1678 TRACE_RET(chip, retval);

1679

1680 retval = ms_read_status_reg(chip);

1681 if (retval != STATUS_SUCCESS)

1682 TRACE_RET(chip, retval);

1683

1684 RTS51X_READ_REG(chip, PPBUF_BASE2, &val);

1685

1686 if (val & BUF_FULL) {

1687 /* Clear Buffer */

1688 retval = ms_send_cmd(chip, CLEAR_BUF, WAIT_INT);

1689 if (retval != STATUS_SUCCESS)

1690 TRACE_RET(chip, retval);

1691 /* GET_INT Register */

1692 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);

1693 if (retval != STATUS_SUCCESS)

1694 TRACE_RET(chip, retval);

1695

1696 if (!(val & INT_REG_CED)) {

1697 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR);

1698 TRACE_RET(chip, STATUS_FAIL);

1699 }

1700 }

1701

1702 for (i = start_page; i < end_page; i++) {

1703 if (monitor_card_cd(chip, MS_CARD) == CD_NOT_EXIST)

1704 TRACE_RET(chip, STATUS_FAIL);

1705

1706 ms_read_extra_data(chip, old_blk, i, extra, MS_EXTRA_SIZE);

1707

1708 retval =

1709 ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE,

1710 SystemParm, 6);

1711 if (retval != STATUS_SUCCESS)

1712 TRACE_RET(chip, retval);

1713 /* Write REG */

1714 ms_set_err_code(chip, MS_NO_ERROR);

1715

1716 if (CHK_MS4BIT(ms_card)) {

1717 /* Parallel interface */

1718 data[0] = 0x88;

1719 } else {

1720 /* Serial interface */

1721 data[0] = 0x80;

1722 }

1723 /* Block Address */

1724 data[1] = 0;

1725 data[2] = (u8) (old_blk >> 8);

1726 data[3] = (u8) old_blk;

1727 data[4] = 0x20;

1728 data[5] = i;

1729

1730 retval =

1731 ms_write_bytes(chip, WRITE_REG, 6, NO_WAIT_INT, data, 6);

1732 if (retval != STATUS_SUCCESS)

1733 TRACE_RET(chip, retval);

1734

1735 retval = ms_send_cmd(chip, BLOCK_READ, WAIT_INT);

1736 if (retval != STATUS_SUCCESS)

1737 TRACE_RET(chip, retval);

1738

1739 ms_set_err_code(chip, MS_NO_ERROR);

1740 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);

1741 if (retval != STATUS_SUCCESS)

1742 TRACE_RET(chip, retval);

1743

1744 if (val & INT_REG_CMDNK) {

1745 ms_set_err_code(chip, MS_CMD_NK);

1746 TRACE_RET(chip, STATUS_FAIL);

1747 }

1748

1749 if (val & INT_REG_CED) {

1750 if (val & INT_REG_ERR) {

1751 retval = ms_read_status_reg(chip);

1752 if (retval != STATUS_SUCCESS) {

1753 uncorrect_flag = 1;

1754 RTS51X_DEBUGP("Uncorrectable"

1755 "error\n");

1756 } else {

1757 uncorrect_flag = 0;

1758 }

1759

1760 retval =

1761 ms_transfer_tpc(chip, MS_TM_NORMAL_READ,

1762 READ_PAGE_DATA, 0, NO_WAIT_INT);

1763 if (retval != STATUS_SUCCESS)

1764 TRACE_RET(chip, retval);

1765 if (uncorrect_flag) {

1766 ms_set_page_status(log_blk, setPS_NG,

1767 extra, MS_EXTRA_SIZE);

1768 if (i == 0)

1769 extra[0] &= 0xEF;

1770 ms_write_extra_data(chip, old_blk, i,

1771 extra,

1772 MS_EXTRA_SIZE);

1773 RTS51X_DEBUGP("page %d :"

1774 "extra[0] = 0x%x\n",

1775 i, extra[0]);

1776 MS_SET_BAD_BLOCK_FLG(ms_card);

1777

1778 ms_set_page_status(log_blk, setPS_Error,

1779 extra, MS_EXTRA_SIZE);

1780 ms_write_extra_data(chip, new_blk, i,

1781 extra, MS_EXTRA_SIZE);

1782 continue;

1783 }

1784

1785 for (rty_cnt = 0; rty_cnt < MS_MAX_RETRY_COUNT;

1786 rty_cnt++) {

1787 retval =

1788 ms_transfer_tpc(chip,

1789 MS_TM_NORMAL_WRITE,

1790 WRITE_PAGE_DATA, 0,

1791 NO_WAIT_INT);

1792 if (retval == STATUS_SUCCESS)

1793 break;

1794 }

1795 if (rty_cnt == MS_MAX_RETRY_COUNT)

1796 TRACE_RET(chip, STATUS_FAIL);

1797 }

1798

1799 if (!(val & INT_REG_BREQ)) {

1800 ms_set_err_code(chip, MS_BREQ_ERROR);

1801 TRACE_RET(chip, STATUS_FAIL);

1802 }

1803 }

1804

1805 retval = ms_set_rw_reg_addr(chip, OverwriteFlag,

1806 MS_EXTRA_SIZE, SystemParm,

1807 (6 + MS_EXTRA_SIZE));

1808

1809 /* Write REG */

1810 ms_set_err_code(chip, MS_NO_ERROR);

1811

1812 if (CHK_MS4BIT(ms_card)) {

1813 /* Parallel interface */

1814 data[0] = 0x88;

1815 } else {

1816 /* Serial interface */

1817 data[0] = 0x80;

1818 }

1819 /* Block Address */

1820 data[1] = 0;

1821 data[2] = (u8) (new_blk >> 8);

1822 data[3] = (u8) new_blk;

1823 data[4] = 0x20;

1824 data[5] = i;

1825

1826 /* for MS check procedure */

1827 if ((extra[0] & 0x60) != 0x60)

1828 data[6] = extra[0];

1829 else

1830 data[6] = 0xF8;

1831

1832 data[6 + 1] = 0xFF;

1833 data[6 + 2] = (u8) (log_blk >> 8);

1834 data[6 + 3] = (u8) log_blk;

1835

1836 for (j = 4; j <= MS_EXTRA_SIZE; j++)

1837 data[6 + j] = 0xFF;

1838

1839 retval =

1840 ms_write_bytes(chip, WRITE_REG, (6 + MS_EXTRA_SIZE),

1841 NO_WAIT_INT, data, 16);

1842 if (retval != STATUS_SUCCESS)

1843 TRACE_RET(chip, retval);

1844

1845 retval = ms_send_cmd(chip, BLOCK_WRITE, WAIT_INT);

1846 if (retval != STATUS_SUCCESS)

1847 TRACE_RET(chip, retval);

1848 /* GET_INT Register */

1849 ms_set_err_code(chip, MS_NO_ERROR);

1850 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);

1851 if (retval != STATUS_SUCCESS)

1852 TRACE_RET(chip, retval);

1853

1854 if (val & INT_REG_CMDNK) {

1855 ms_set_err_code(chip, MS_CMD_NK);

1856 TRACE_RET(chip, STATUS_FAIL);

1857 }

1858

1859 if (val & INT_REG_CED) {

1860 if (val & INT_REG_ERR) {

1861 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR);

1862 TRACE_RET(chip, STATUS_FAIL);

1863 }

1864 }

1865

1866 if (i == 0) {

1867 retval =

1868 ms_set_rw_reg_addr(chip, OverwriteFlag,

1869 MS_EXTRA_SIZE, SystemParm, 7);

1870 if (retval != STATUS_SUCCESS)

1871 TRACE_RET(chip, retval);

1872

1873 ms_set_err_code(chip, MS_NO_ERROR);

1874

1875 if (CHK_MS4BIT(ms_card)) {

1876 /* Parallel interface */

1877 data[0] = 0x88;

1878 } else {

1879 /* Serial interface */

1880 data[0] = 0x80;

1881 }

1882 /* Block Address */

1883 data[1] = 0;

1884 data[2] = (u8) (old_blk >> 8);

1885 data[3] = (u8) old_blk;

1886 data[4] = 0x80;

1887 data[5] = 0;

1888 data[6] = 0xEF;

1889 data[7] = 0xFF;

1890

1891 retval =

1892 ms_write_bytes(chip, WRITE_REG, 7, NO_WAIT_INT,

1893 data, 8);

1894 if (retval != STATUS_SUCCESS)

1895 TRACE_RET(chip, retval);

1896

1897 retval = ms_send_cmd(chip, BLOCK_WRITE, WAIT_INT);

1898 if (retval != STATUS_SUCCESS)

1899 TRACE_RET(chip, retval);

1900

1901 ms_set_err_code(chip, MS_NO_ERROR);

1902 retval =

1903 ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val,

1904 1);

1905 if (retval != STATUS_SUCCESS)

1906 TRACE_RET(chip, retval);

1907

1908 if (val & INT_REG_CMDNK) {

1909 ms_set_err_code(chip, MS_CMD_NK);

1910 TRACE_RET(chip, STATUS_FAIL);

1911 }

1912

1913 if (val & INT_REG_CED) {

1914 if (val & INT_REG_ERR) {

1915 ms_set_err_code(chip,

1916 MS_FLASH_WRITE_ERROR);

1917 TRACE_RET(chip, STATUS_FAIL);

1918 }

1919 }

1920 }

1921 }

1922

1923 return STATUS_SUCCESS;

1924 }

1925

1926 #ifdef MS_SPEEDUP

1927 static int ms_auto_copy_page(struct rts51x_chip *chip, u16 old_blk, u16 new_blk,

1928 u16 log_blk, u8 start_page, u8 end_page)

1929 {

1930 struct ms_info *ms_card = &(chip->ms_card);

1931 int retval;

1932 u8 page_len, bus_width, val = 0;

1933 u8 extra[MS_EXTRA_SIZE];

1934

1935 RTS51X_DEBUGP("Auto copy page from 0x%x to 0x%x,"

1936 "logical block is 0x%x\n",

1937 old_blk, new_blk, log_blk);

1938 RTS51X_DEBUGP("start_page = %d, end_page = %d\n", start_page,

1939 end_page);

1940

1941 page_len = end_page - start_page;

1942

1943 retval = ms_read_extra_data(chip, new_blk, 0, extra, MS_EXTRA_SIZE);

1944 if (retval != STATUS_SUCCESS)

1945 TRACE_RET(chip, retval);

1946

1947 retval = ms_read_status_reg(chip);

1948 if (retval != STATUS_SUCCESS)

1949 TRACE_RET(chip, retval);

1950

1951 RTS51X_READ_REG(chip, PPBUF_BASE2, &val);

1952

1953 if (val & BUF_FULL) {

1954 retval = ms_send_cmd(chip, CLEAR_BUF, WAIT_INT);

1955 if (retval != STATUS_SUCCESS)

1956 TRACE_RET(chip, retval);

1957

1958 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);

1959 if (retval != STATUS_SUCCESS)

1960 TRACE_RET(chip, retval);

1961

1962 if (!(val & INT_REG_CED)) {

1963 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR);

1964 TRACE_RET(chip, STATUS_FAIL);

1965 }

1966 }

1967

1968 if (CHK_MS4BIT(ms_card)) {

1969 /* Parallel interface */

1970 bus_width = 0x88;

1971 } else {

1972 /* Serial interface */

1973 bus_width = 0x80;

1974 }

1975

1976 rts51x_init_cmd(chip);

1977

1978 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_OLD_BLOCK_0, 0xFF, (u8) old_blk);

1979 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_OLD_BLOCK_1, 0xFF,

1980 (u8) (old_blk >> 8));

1981 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_NEW_BLOCK_0, 0xFF, (u8) new_blk);

1982 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_NEW_BLOCK_1, 0xFF,

1983 (u8) (new_blk >> 8));

1984 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_LOG_BLOCK_0, 0xFF, (u8) log_blk);

1985 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_LOG_BLOCK_1, 0xFF,

1986 (u8) (log_blk >> 8));

1987 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_PAGE_START, 0xFF, start_page);

1988 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_PAGE_LENGTH, 0xFF, page_len);

1989 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_BUS_WIDTH, 0xFF, bus_width);

1990

1991 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 0xFF,

1992 MS_TRANSFER_START | MS_TM_COPY_PAGE);

1993 rts51x_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER, MS_TRANSFER_END,

1994 MS_TRANSFER_END);

1995

1996 retval = rts51x_send_cmd(chip, MODE_CR, 100);

1997 if (retval != STATUS_SUCCESS) {

1998 rts51x_clear_ms_error(chip);

1999 TRACE_RET(chip, retval);

2000 }

2001

2002 retval = rts51x_get_rsp(chip, 1, 5000);

2003

2004 if (CHECK_MS_TRANS_FAIL(chip, retval)) {

2005 rts51x_clear_ms_error(chip);

2006 if (retval == STATUS_TIMEDOUT)

2007 TRACE_RET(chip, retval);

2008 TRACE_GOTO(chip, Fail);

2009 }

2010

2011 return STATUS_SUCCESS;

2012

2013 Fail:

2014 retval = ms_erase_block(chip, new_blk);

2015 if (retval != STATUS_SUCCESS)

2016 TRACE_RET(chip, retval);

2017

2018 retval =

2019 ms_copy_page(chip, old_blk, new_blk, log_blk, start_page, end_page);

2020 if (retval != STATUS_SUCCESS)

2021 TRACE_RET(chip, retval);

2022

2023 return STATUS_SUCCESS;

2024 }

2025 #endif

2026

2027 static int reset_ms(struct rts51x_chip *chip)

2028 {

2029 struct ms_info *ms_card = &(chip->ms_card);

2030 int retval;

2031 u16 i, reg_addr, block_size;

2032 u8 val, j, *ptr;

2033 #ifndef SUPPORT_MAGIC_GATE

2034 u16 eblock_cnt;

2035 #endif

2036

2037 retval = ms_prepare_reset(chip);

2038 if (retval != STATUS_SUCCESS)

2039 TRACE_RET(chip, retval);

2040

2041 ms_card->ms_type |= TYPE_MS;

2042

2043 retval = ms_send_cmd(chip, MS_RESET, NO_WAIT_INT);

2044 if (retval != STATUS_SUCCESS)

2045 TRACE_RET(chip, retval);

2046

2047 retval = ms_read_status_reg(chip);

2048 if (retval != STATUS_SUCCESS)

2049 TRACE_RET(chip, retval);

2050

2051 RTS51X_READ_REG(chip, PPBUF_BASE2, &val);

2052 if (val & WRT_PRTCT)

2053 chip->card_wp |= MS_CARD;

2054 else

2055 chip->card_wp &= ~MS_CARD;

2056

2057 i = 0;

2058

2059 RE_SEARCH:

2060 /* Search For Boot Block */

2061 while (i < (MAX_DEFECTIVE_BLOCK + 2)) {

2062 if (monitor_card_cd(chip, MS_CARD) == CD_NOT_EXIST)

2063 TRACE_RET(chip, STATUS_FAIL);

2064

2065 retval = ms_check_boot_block(chip, i);

2066 if (retval != STATUS_SUCCESS) {

2067 i++;

2068 continue;

2069 }

2070

2071 ms_card->boot_block = i;

2072 break;

2073 }

2074

2075 if (i == (MAX_DEFECTIVE_BLOCK + 2)) {

2076 RTS51X_DEBUGP("No boot block found!");

2077 TRACE_RET(chip, STATUS_FAIL);

2078 }

2079 for (j = 0; j < 3; j++) {

2080 retval = ms_read_page(chip, ms_card->boot_block, j);

2081 if (retval != STATUS_SUCCESS) {

2082 if (ms_check_err_code(chip, MS_FLASH_WRITE_ERROR)) {

2083 i = ms_card->boot_block + 1;

2084 ms_set_err_code(chip, MS_NO_ERROR);

2085 goto RE_SEARCH;

2086 }

2087 }

2088 }

2089

2090 /* Read boot block contents */

2091 retval = ms_read_page(chip, ms_card->boot_block, 0);

2092 if (retval != STATUS_SUCCESS)

2093 TRACE_RET(chip, retval);

2094 /* Read MS system information as sys_info */

2095 retval =

2096 rts51x_seq_read_register(chip, PPBUF_BASE2 + 0x1A0, 96,

2097 ms_card->raw_sys_info);

2098 if (retval != STATUS_SUCCESS)

2099 TRACE_RET(chip, retval);

2100 /* Read useful block contents */

2101 rts51x_init_cmd(chip);

2102

2103 rts51x_add_cmd(chip, READ_REG_CMD, HEADER_ID0, 0, 0);

2104 rts51x_add_cmd(chip, READ_REG_CMD, HEADER_ID1, 0, 0);

2105

2106 for (reg_addr = DISABLED_BLOCK0; reg_addr <= DISABLED_BLOCK3;

2107 reg_addr++) {

2108 rts51x_add_cmd(chip, READ_REG_CMD, reg_addr, 0, 0);

2109 }

2110

2111 for (reg_addr = BLOCK_SIZE_0; reg_addr <= PAGE_SIZE_1; reg_addr++)

2112 rts51x_add_cmd(chip, READ_REG_CMD, reg_addr, 0, 0);

2113

2114 rts51x_add_cmd(chip, READ_REG_CMD, MS_Device_Type, 0, 0);

2115 rts51x_add_cmd(chip, READ_REG_CMD, MS_4bit_Support, 0, 0);

2116

2117 retval = rts51x_send_cmd(chip, MODE_CR, 100);

2118 if (retval != STATUS_SUCCESS)

2119 TRACE_RET(chip, retval);

2120

2121 retval = rts51x_get_rsp(chip, 16, 100);

2122

2123 if (retval != STATUS_SUCCESS)

2124 TRACE_RET(chip, retval);

2125

2126 ptr = rts51x_get_rsp_data(chip);

2127

2128 RTS51X_DEBUGP("Boot block data:\n");

2129 RTS51X_DUMP(ptr, 16);

2130

2131 if (ptr[0] != 0x00 || ptr[1] != 0x01) {

2132 i = ms_card->boot_block + 1;

2133 goto RE_SEARCH;

2134 }

2135 if (ptr[12] != 0x02 || ptr[13] != 0x00) {

2136 i = ms_card->boot_block + 1;

2137 goto RE_SEARCH;

2138 }

2139 if ((ptr[14] == 1) || (ptr[14] == 3))

2140 chip->card_wp |= MS_CARD;

2141 block_size = ((u16) ptr[6] << 8) | ptr[7];

2142 if (block_size == 0x0010) {

2143 ms_card->block_shift = 5;

2144 ms_card->page_off = 0x1F;

2145 } else if (block_size == 0x0008) {

2146 ms_card->block_shift = 4;

2147 ms_card->page_off = 0x0F;

2148 }

2149 ms_card->total_block = ((u16) ptr[8] << 8) | ptr[9];

2150

2151 #ifdef SUPPORT_MAGIC_GATE

2152 j = ptr[10];

2153

2154 if (ms_card->block_shift == 4) {

2155 if (j < 2)

2156 ms_card->capacity = 0x1EE0;

2157 else

2158 ms_card->capacity = 0x3DE0;

2159 } else {

2160 if (j < 5)

2161 ms_card->capacity = 0x7BC0;

2162 else if (j < 0xA)

2163 ms_card->capacity = 0xF7C0;

2164 else if (j < 0x11)

2165 ms_card->capacity = 0x1EF80;

2166 else

2167 ms_card->capacity = 0x3DF00;

2168 }

2169 #else

2170 eblock_cnt = ((u16) ptr[10] << 8) | ptr[11];

2171

2172 ms_card->capacity = ((u32) eblock_cnt - 2) << ms_card->block_shift;

2173 #endif

2174

2175 chip->capacity[chip->card2lun[MS_CARD]] = ms_card->capacity;

2176

2177 if (ptr[15]) {

2178 retval = ms_set_rw_reg_addr(chip, 0, 0, SystemParm, 1);

2179 if (retval != STATUS_SUCCESS)

2180 TRACE_RET(chip, STATUS_FAIL);

2181 RTS51X_WRITE_REG(chip, PPBUF_BASE2, 0xFF, 0x88);

2182 RTS51X_WRITE_REG(chip, PPBUF_BASE2 + 1, 0xFF, 0);

2183

2184 retval =

2185 ms_transfer_tpc(chip, MS_TM_WRITE_BYTES, WRITE_REG, 1,

2186 NO_WAIT_INT);

2187 if (retval != STATUS_SUCCESS)

2188 TRACE_RET(chip, STATUS_FAIL);

2189 RTS51X_WRITE_REG(chip, MS_CFG, 0x58 | MS_NO_CHECK_INT,

2190 MS_BUS_WIDTH_4 | PUSH_TIME_ODD |

2191 MS_NO_CHECK_INT);

2192

2193 ms_card->ms_type |= MS_4BIT;

2194 }

2195

2196 if (CHK_MS4BIT(ms_card))

2197 chip->card_bus_width[chip->card2lun[MS_CARD]] = 4;

2198 else

2199 chip->card_bus_width[chip->card2lun[MS_CARD]] = 1;

2200

2201 return STATUS_SUCCESS;

2202 }

2203

2204 static int ms_init_l2p_tbl(struct rts51x_chip *chip)

2205 {

2206 struct ms_info *ms_card = &(chip->ms_card);

2207 int size, i, seg_no, retval;

2208 u16 defect_block, reg_addr;

2209 u8 val1, val2;

2210

2211 ms_card->segment_cnt = ms_card->total_block >> 9;

2212 RTS51X_DEBUGP("ms_card->segment_cnt = %d\n", ms_card->segment_cnt);

2213

2214 size = ms_card->segment_cnt * sizeof(struct zone_entry);

2215 ms_card->segment = vmalloc(size);

2216 if (ms_card->segment == NULL)

2217 TRACE_RET(chip, STATUS_FAIL);

2218 memset(ms_card->segment, 0, size);

2219

2220 retval = ms_read_page(chip, ms_card->boot_block, 1);

2221 if (retval != STATUS_SUCCESS)

2222 TRACE_GOTO(chip, INIT_FAIL);

2223

2224 reg_addr = PPBUF_BASE2;

2225 for (i = 0; i < (((ms_card->total_block >> 9) * 10) + 1); i++) {

2226 retval = rts51x_read_register(chip, reg_addr++, &val1);

2227 if (retval != STATUS_SUCCESS)

2228 TRACE_GOTO(chip, INIT_FAIL);

2229 retval = rts51x_read_register(chip, reg_addr++, &val2);

2230 if (retval != STATUS_SUCCESS)

2231 TRACE_GOTO(chip, INIT_FAIL);

2232

2233 defect_block = ((u16) val1 << 8) | val2;

2234 if (defect_block == 0xFFFF)

2235 break;

2236 seg_no = defect_block / 512;

2237 ms_card->segment[seg_no].defect_list[ms_card->segment[seg_no].

2238 disable_count++] =

2239 defect_block;

2240 }

2241

2242 for (i = 0; i < ms_card->segment_cnt; i++) {

2243 ms_card->segment[i].build_flag = 0;

2244 ms_card->segment[i].l2p_table = NULL;

2245 ms_card->segment[i].free_table = NULL;

2246 ms_card->segment[i].get_index = 0;

2247 ms_card->segment[i].set_index = 0;

2248 ms_card->segment[i].unused_blk_cnt = 0;

2249

2250 RTS51X_DEBUGP("defective block count of segment %d is %d\n",

2251 i, ms_card->segment[i].disable_count);

2252 }

2253

2254 return STATUS_SUCCESS;

2255

2256 INIT_FAIL:

2257 if (ms_card->segment) {

2258 vfree(ms_card->segment);

2259 ms_card->segment = NULL;

2260 }

2261

2262 return STATUS_FAIL;

2263 }

2264

2265 static u16 ms_get_l2p_tbl(struct rts51x_chip *chip, int seg_no, u16 log_off)

2266 {

2267 struct ms_info *ms_card = &(chip->ms_card);

2268 struct zone_entry *segment;

2269

2270 if (ms_card->segment == NULL)

2271 return 0xFFFF;

2272

2273 segment = &(ms_card->segment[seg_no]);

2274

2275 if (segment->l2p_table)

2276 return segment->l2p_table[log_off];

2277

2278 return 0xFFFF;

2279 }

2280

2281 static void ms_set_l2p_tbl(struct rts51x_chip *chip, int seg_no, u16 log_off,

2282 u16 phy_blk)

2283 {

2284 struct ms_info *ms_card = &(chip->ms_card);

2285 struct zone_entry *segment;

2286

2287 if (ms_card->segment == NULL)

2288 return;

2289

2290 segment = &(ms_card->segment[seg_no]);

2291 if (segment->l2p_table)

2292 segment->l2p_table[log_off] = phy_blk;

2293 }

2294

2295 static void ms_set_unused_block(struct rts51x_chip *chip, u16 phy_blk)

2296 {

2297 struct ms_info *ms_card = &(chip->ms_card);

2298 struct zone_entry *segment;

2299 int seg_no;

2300

2301 seg_no = (int)phy_blk >> 9;

2302 segment = &(ms_card->segment[seg_no]);

2303

2304 segment->free_table[segment->set_index++] = phy_blk;

2305 if (segment->set_index >= MS_FREE_TABLE_CNT)

2306 segment->set_index = 0;

2307 segment->unused_blk_cnt++;

2308 }

2309

2310 static u16 ms_get_unused_block(struct rts51x_chip *chip, int seg_no)

2311 {

2312 struct ms_info *ms_card = &(chip->ms_card);

2313 struct zone_entry *segment;

2314 u16 phy_blk;

2315

2316 segment = &(ms_card->segment[seg_no]);

2317

2318 if (segment->unused_blk_cnt <= 0)

2319 return 0xFFFF;

2320

2321 phy_blk = segment->free_table[segment->get_index];

2322 segment->free_table[segment->get_index++] = 0xFFFF;

2323 if (segment->get_index >= MS_FREE_TABLE_CNT)

2324 segment->get_index = 0;

2325 segment->unused_blk_cnt--;

2326

2327 return phy_blk;

2328 }

2329

2330 static const unsigned short ms_start_idx[] = {

2331 0, 494, 990, 1486, 1982, 2478, 2974, 3470,

2332 3966, 4462, 4958, 5454, 5950, 6446, 6942, 7438, 7934

2333 };

2334

2335 static int ms_arbitrate_l2p(struct rts51x_chip *chip, u16 phy_blk, u16 log_off,

2336 u8 us1, u8 us2)

2337 {

2338 struct ms_info *ms_card = &(chip->ms_card);

2339 struct zone_entry *segment;

2340 int seg_no;

2341 u16 tmp_blk;

2342

2343 seg_no = (int)phy_blk >> 9;

2344 segment = &(ms_card->segment[seg_no]);

2345 tmp_blk = segment->l2p_table[log_off];

2346

2347 if (us1 != us2) {

2348 if (us1 == 0) {

2349 if (!(chip->card_wp & MS_CARD))

2350 ms_erase_block(chip, tmp_blk);

2351 ms_set_unused_block(chip, tmp_blk);

2352 segment->l2p_table[log_off] = phy_blk;

2353 } else {

2354 if (!(chip->card_wp & MS_CARD))

2355 ms_erase_block(chip, phy_blk);

2356 ms_set_unused_block(chip, phy_blk);

2357 }

2358 } else {

2359 if (phy_blk < tmp_blk) {

2360 if (!(chip->card_wp & MS_CARD))

2361 ms_erase_block(chip, phy_blk);

2362 ms_set_unused_block(chip, phy_blk);

2363 } else {

2364 if (!(chip->card_wp & MS_CARD))

2365 ms_erase_block(chip, tmp_blk);

2366 ms_set_unused_block(chip, tmp_blk);

2367 segment->l2p_table[log_off] = phy_blk;

2368 }

2369 }

2370

2371 return STATUS_SUCCESS;

2372 }

2373

2374 static int ms_build_l2p_tbl(struct rts51x_chip *chip, int seg_no)

2375 {

2376 struct ms_info *ms_card = &(chip->ms_card);

2377 struct zone_entry *segment;

2378 int retval, table_size, disable_cnt, defect_flag, i;

2379 u16 start, end, phy_blk, log_blk, tmp_blk;

2380 u8 extra[MS_EXTRA_SIZE], us1, us2;

2381

2382 RTS51X_DEBUGP("ms_build_l2p_tbl: %d\n", seg_no);

2383

2384 if (ms_card->segment == NULL) {

2385 retval = ms_init_l2p_tbl(chip);

2386 if (retval != STATUS_SUCCESS)

2387 TRACE_RET(chip, retval);

2388 }

2389

2390 if (ms_card->segment[seg_no].build_flag) {

2391 RTS51X_DEBUGP("l2p table of segment %d has been built\n",

2392 seg_no);

2393 return STATUS_SUCCESS;

2394 }

2395

2396 if (seg_no == 0)

2397 table_size = 494;

2398 else

2399 table_size = 496;

2400

2401 segment = &(ms_card->segment[seg_no]);

2402

2403 if (segment->l2p_table == NULL) {

2404 segment->l2p_table = vmalloc(table_size * 2);

2405 if (segment->l2p_table == NULL)

2406 TRACE_GOTO(chip, BUILD_FAIL);

2407 }

2408 memset((u8 *) (segment->l2p_table), 0xff, table_size * 2);

2409

2410 if (segment->free_table == NULL) {

2411 segment->free_table = vmalloc(MS_FREE_TABLE_CNT * 2);

2412 if (segment->free_table == NULL)

2413 TRACE_GOTO(chip, BUILD_FAIL);

2414 }

2415 memset((u8 *) (segment->free_table), 0xff, MS_FREE_TABLE_CNT * 2);

2416

2417 start = (u16) seg_no << 9;

2418 end = (u16) (seg_no + 1) << 9;

2419

2420 disable_cnt = segment->disable_count;

2421

2422 segment->get_index = segment->set_index = 0;

2423 segment->unused_blk_cnt = 0;

2424

2425 for (phy_blk = start; phy_blk < end; phy_blk++) {

2426 if (disable_cnt) {

2427 defect_flag = 0;

2428 for (i = 0; i < segment->disable_count; i++) {

2429 if (phy_blk == segment->defect_list[i]) {

2430 defect_flag = 1;

2431 break;

2432 }

2433 }

2434 if (defect_flag) {

2435 disable_cnt--;

2436 continue;

2437 }

2438 }

2439

2440 retval =

2441 ms_read_extra_data(chip, phy_blk, 0, extra, MS_EXTRA_SIZE);

2442 if (retval != STATUS_SUCCESS) {

2443 RTS51X_DEBUGP("read extra data fail\n");

2444 ms_set_bad_block(chip, phy_blk);

2445 continue;

2446 }

2447

2448 if (seg_no == ms_card->segment_cnt - 1) {

2449 if (!(extra[1] & NOT_TRANSLATION_TABLE)) {

2450 if (!(chip->card_wp & MS_CARD)) {

2451 retval = ms_erase_block(chip, phy_blk);

2452 if (retval != STATUS_SUCCESS)

2453 continue;

2454 extra[2] = 0xff;

2455 extra[3] = 0xff;

2456 }

2457 }

2458 }

2459

2460 if (!(extra[0] & BLOCK_OK))

2461 continue;

2462 if (!(extra[1] & NOT_BOOT_BLOCK))

2463 continue;

2464 if ((extra[0] & PAGE_OK) != PAGE_OK)

2465 continue;

2466

2467 log_blk = ((u16) extra[2] << 8) | extra[3];

2468

2469 if (log_blk == 0xFFFF) {

2470 if (!(chip->card_wp & MS_CARD)) {

2471 retval = ms_erase_block(chip, phy_blk);

2472 if (retval != STATUS_SUCCESS)

2473 continue;

2474 }

2475 ms_set_unused_block(chip, phy_blk);

2476 continue;

2477 }

2478

2479 if ((log_blk < ms_start_idx[seg_no]) ||

2480 (log_blk >= ms_start_idx[seg_no + 1])) {

2481 if (!(chip->card_wp & MS_CARD)) {

2482 retval = ms_erase_block(chip, phy_blk);

2483 if (retval != STATUS_SUCCESS)

2484 continue;

2485 }

2486 ms_set_unused_block(chip, phy_blk);

2487 continue;

2488 }

2489

2490 if (segment->l2p_table[log_blk - ms_start_idx[seg_no]] ==

2491 0xFFFF) {

2492 segment->l2p_table[log_blk - ms_start_idx[seg_no]] =

2493 phy_blk;

2494 continue;

2495 }

2496

2497 us1 = extra[0] & 0x10;

2498 tmp_blk = segment->l2p_table[log_blk - ms_start_idx[seg_no]];

2499 retval =

2500 ms_read_extra_data(chip, tmp_blk, 0, extra, MS_EXTRA_SIZE);

2501 if (retval != STATUS_SUCCESS)

2502 continue;

2503 us2 = extra[0] & 0x10;

2504

2505 (void)ms_arbitrate_l2p(chip, phy_blk,

2506 log_blk - ms_start_idx[seg_no], us1,

2507 us2);

2508 continue;

2509 }

2510

2511 segment->build_flag = 1;

2512

2513 RTS51X_DEBUGP("unused block count: %d\n", segment->unused_blk_cnt);

2514

2515 if (seg_no == ms_card->segment_cnt - 1) {

2516 if (segment->unused_blk_cnt < 2)

2517 chip->card_wp |= MS_CARD;

2518 } else {

2519 if (segment->unused_blk_cnt < 1)

2520 chip->card_wp |= MS_CARD;

2521 }

2522

2523 if (chip->card_wp & MS_CARD)

2524 return STATUS_SUCCESS;

2525

2526 for (log_blk = ms_start_idx[seg_no]; log_blk < ms_start_idx[seg_no + 1];

2527 log_blk++) {

2528 if (segment->l2p_table[log_blk - ms_start_idx[seg_no]] ==

2529 0xFFFF) {

2530 phy_blk = ms_get_unused_block(chip, seg_no);

2531 if (phy_blk == 0xFFFF) {

2532 chip->card_wp |= MS_CARD;

2533 return STATUS_SUCCESS;

2534 }

2535 retval = ms_init_page(chip, phy_blk, log_blk, 0, 1);

2536 if (retval != STATUS_SUCCESS)

2537 TRACE_GOTO(chip, BUILD_FAIL);

2538 segment->l2p_table[log_blk - ms_start_idx[seg_no]] =

2539 phy_blk;

2540 if (seg_no == ms_card->segment_cnt - 1) {

2541 if (segment->unused_blk_cnt < 2) {

2542 chip->card_wp |= MS_CARD;

2543 return STATUS_SUCCESS;

2544 }

2545 } else {

2546 if (segment->unused_blk_cnt < 1) {

2547 chip->card_wp |= MS_CARD;

2548 return STATUS_SUCCESS;

2549 }

2550 }

2551 }

2552 }

2553

2554 if (seg_no == 0) {

2555 for (log_blk = 0; log_blk < 494; log_blk++) {

2556 tmp_blk = segment->l2p_table[log_blk];

2557 if (tmp_blk < ms_card->boot_block) {

2558 RTS51X_DEBUGP("Boot block is not the first"

2559 "normal block.\n");

2560

2561 if (chip->card_wp & MS_CARD)

2562 break;

2563

2564 phy_blk = ms_get_unused_block(chip, 0);

2565 #ifdef MS_SPEEDUP

2566 retval =

2567 ms_auto_copy_page(chip, tmp_blk, phy_blk,

2568 log_blk, 0,

2569 ms_card->page_off + 1);

2570 #else

2571 retval = ms_copy_page(chip, tmp_blk, phy_blk,

2572 log_blk, 0,

2573 ms_card->page_off + 1);

2574 #endif

2575 if (retval != STATUS_SUCCESS)

2576 TRACE_RET(chip, retval);

2577

2578 segment->l2p_table[log_blk] = phy_blk;

2579

2580 retval = ms_set_bad_block(chip, tmp_blk);

2581 if (retval != STATUS_SUCCESS)

2582 TRACE_RET(chip, retval);

2583 }

2584 }

2585 }

2586

2587 return STATUS_SUCCESS;

2588

2589 BUILD_FAIL:

2590 segment->build_flag = 0;

2591 if (segment->l2p_table) {

2592 vfree(segment->l2p_table);

2593 segment->l2p_table = NULL;

2594 }

2595 if (segment->free_table) {

2596 vfree(segment->free_table);

2597 segment->free_table = NULL;

2598 }

2599

2600 return STATUS_FAIL;

2601 }

2602

2603 int reset_ms_card(struct rts51x_chip *chip)

2604 {

2605 struct ms_info *ms_card = &(chip->ms_card);

2606 int retval;

2607

2608 memset(ms_card, 0, sizeof(struct ms_info));

2609

2610 enable_card_clock(chip, MS_CARD);

2611

2612 retval = rts51x_select_card(chip, MS_CARD);

2613 if (retval != STATUS_SUCCESS)

2614 TRACE_RET(chip, retval);

2615

2616 ms_card->ms_type = 0;

2617 ms_card->last_rw_int = 0;

2618

2619 retval = reset_ms_pro(chip);

2620 if (retval != STATUS_SUCCESS) {

2621 if (ms_card->check_ms_flow) {

2622 retval = reset_ms(chip);

2623 if (retval != STATUS_SUCCESS) {

2624 if (chip->option.reset_or_rw_fail_set_pad_drive) {

2625 rts51x_write_register(chip,

2626 CARD_DRIVE_SEL, SD20_DRIVE_MASK,

2627 DRIVE_8mA);

2628 }

2629 TRACE_RET(chip, retval);

2630 }

2631 } else {

2632 if (chip->option.reset_or_rw_fail_set_pad_drive) {

2633 rts51x_write_register(chip, CARD_DRIVE_SEL,

2634 SD20_DRIVE_MASK,

2635 DRIVE_8mA);

2636 }

2637 TRACE_RET(chip, retval);

2638 }

2639 }

2640

2641 retval = ms_set_init_para(chip);

2642 if (retval != STATUS_SUCCESS)

2643 TRACE_RET(chip, retval);

2644

2645 if (!CHK_MSPRO(ms_card)) {

2646 retval = ms_build_l2p_tbl(chip, ms_card->total_block / 512 - 1);

2647 if (retval != STATUS_SUCCESS)

2648 TRACE_RET(chip, retval);

2649 }

2650

2651 RTS51X_DEBUGP("ms_card->ms_type = 0x%x\n", ms_card->ms_type);

2652

2653 return STATUS_SUCCESS;

2654 }

2655

2656 static int mspro_set_rw_cmd(struct rts51x_chip *chip, u32 start_sec,

2657 u16 sec_cnt, u8 cmd)

2658 {

2659 int retval, i;

2660 u8 data[8];

2661

2662 data[0] = cmd;

2663 data[1] = (u8) (sec_cnt >> 8);

2664 data[2] = (u8) sec_cnt;

2665 data[3] = (u8) (start_sec >> 24);

2666 data[4] = (u8) (start_sec >> 16);

2667 data[5] = (u8) (start_sec >> 8);

2668 data[6] = (u8) start_sec;

2669 data[7] = 0;

2670

2671 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {

2672 retval =

2673 ms_write_bytes(chip, PRO_EX_SET_CMD, 7, WAIT_INT, data, 8);

2674 if (retval == STATUS_SUCCESS)

2675 break;

2676 }

2677 if (i == MS_MAX_RETRY_COUNT)

2678 TRACE_RET(chip, STATUS_FAIL);

2679

2680 return STATUS_SUCCESS;

2681 }

2682

2683 static void mspro_stop_seq_mode(struct rts51x_chip *chip)

2684 {

2685 struct ms_info *ms_card = &(chip->ms_card);

2686 int retval;

2687

2688 if (ms_card->seq_mode) {

2689 retval = ms_switch_clock(chip);

2690 if (retval != STATUS_SUCCESS)

2691 return;

2692

2693 ms_card->seq_mode = 0;

2694 ms_card->total_sec_cnt = 0;

2695 ms_card->last_rw_int = 0;

2696 ms_send_cmd(chip, PRO_STOP, WAIT_INT);

2697

2698 rts51x_ep0_write_register(chip, MC_FIFO_CTL, FIFO_FLUSH,

2699 FIFO_FLUSH);

2700 }

2701 }

2702

2703 static inline int ms_auto_tune_clock(struct rts51x_chip *chip)

2704 {

2705 struct ms_info *ms_card = &(chip->ms_card);

2706 int retval;

2707

2708 if (chip->asic_code) {

2709 if (ms_card->ms_clock > 30)

2710 ms_card->ms_clock -= 20;

2711 } else {

2712 if (ms_card->ms_clock == CLK_80)

2713 ms_card->ms_clock = CLK_60;

2714 else if (ms_card->ms_clock == CLK_60)

2715 ms_card->ms_clock = CLK_40;

2716 }

2717

2718 retval = ms_switch_clock(chip);

2719 if (retval != STATUS_SUCCESS)

2720 TRACE_RET(chip, retval);

2721

2722 return STATUS_SUCCESS;

2723 }

2724

2725 static int mspro_rw_multi_sector(struct scsi_cmnd *srb,

2726 struct rts51x_chip *chip, u32 start_sector,

2727 u16 sector_cnt)

2728 {

2729 struct ms_info *ms_card = &(chip->ms_card);

2730 int retval, mode_2k = 0;

2731 u16 count;

2732 u8 val, trans_mode, rw_tpc, rw_cmd;

2733

2734 ms_set_err_code(chip, MS_NO_ERROR);

2735

2736 ms_card->counter = 0;

2737

2738 if (CHK_MSHG(ms_card)) {

2739 if ((start_sector % 4) || (sector_cnt % 4)) {

2740 if (srb->sc_data_direction == DMA_FROM_DEVICE) {

2741 rw_tpc = PRO_READ_LONG_DATA;

2742 rw_cmd = PRO_READ_DATA;

2743 } else {

2744 rw_tpc = PRO_WRITE_LONG_DATA;

2745 rw_cmd = PRO_WRITE_DATA;

2746 }

2747 } else {

2748 if (srb->sc_data_direction == DMA_FROM_DEVICE) {

2749 rw_tpc = PRO_READ_QUAD_DATA;

2750 rw_cmd = PRO_READ_2K_DATA;

2751 } else {

2752 rw_tpc = PRO_WRITE_QUAD_DATA;

2753 rw_cmd = PRO_WRITE_2K_DATA;

2754 }

2755 mode_2k = 1;

2756 }

2757 } else {

2758 if (srb->sc_data_direction == DMA_FROM_DEVICE) {

2759 rw_tpc = PRO_READ_LONG_DATA;

2760 rw_cmd = PRO_READ_DATA;

2761 } else {

2762 rw_tpc = PRO_WRITE_LONG_DATA;

2763 rw_cmd = PRO_WRITE_DATA;

2764 }

2765 }

2766

2767 retval = ms_switch_clock(chip);

2768 if (retval != STATUS_SUCCESS)

2769 TRACE_RET(chip, retval);

2770

2771 if (srb->sc_data_direction == DMA_FROM_DEVICE)

2772 trans_mode = MS_TM_AUTO_READ;

2773 else

2774 trans_mode = MS_TM_AUTO_WRITE;

2775

2776 val = ms_card->last_rw_int;

2777

2778 if (ms_card->seq_mode) {

2779 if ((ms_card->pre_dir != srb->sc_data_direction)

2780 || ((ms_card->pre_sec_addr + ms_card->pre_sec_cnt) !=

2781 start_sector)

2782 || (mode_2k && (ms_card->seq_mode & MODE_512_SEQ))

2783 || (!mode_2k && (ms_card->seq_mode & MODE_2K_SEQ))

2784 || !(val & MS_INT_BREQ)

2785 || ((ms_card->total_sec_cnt + sector_cnt) > 0xFE00)) {

2786 ms_card->seq_mode = 0;

2787 ms_card->total_sec_cnt = 0;

2788 ms_card->last_rw_int = 0;

2789 if (val & MS_INT_BREQ) {

2790 retval = ms_send_cmd(chip, PRO_STOP, WAIT_INT);

2791 if (retval != STATUS_SUCCESS)

2792 TRACE_RET(chip, retval);

2793

2794 rts51x_ep0_write_register(chip, MC_FIFO_CTL,

2795 FIFO_FLUSH, FIFO_FLUSH);

2796 }

2797 }

2798 }

2799

2800 if (!ms_card->seq_mode) {

2801 ms_card->total_sec_cnt = 0;

2802 if (sector_cnt >= 0x80) {

2803 if ((ms_card->capacity - start_sector) > 0xFE00)

2804 count = 0xFE00;

2805 else

2806 count =

2807 (u16) (ms_card->capacity - start_sector);

2808 if (count > sector_cnt) {

2809 if (mode_2k)

2810 ms_card->seq_mode |= MODE_2K_SEQ;

2811 else

2812 ms_card->seq_mode |= MODE_512_SEQ;

2813 }

2814 } else {

2815 count = sector_cnt;

2816 }

2817 retval = mspro_set_rw_cmd(chip, start_sector, count, rw_cmd);

2818 if (retval != STATUS_SUCCESS) {

2819 ms_card->seq_mode = 0;

2820 TRACE_RET(chip, retval);

2821 }

2822 }

2823

2824 retval =

2825 ms_transfer_data(chip, trans_mode, rw_tpc, sector_cnt, WAIT_INT,

2826 mode_2k, scsi_sg_count(srb), scsi_sglist(srb),

2827 scsi_bufflen(srb));

2828 if (retval != STATUS_SUCCESS) {

2829 ms_card->seq_mode = 0;

2830 rts51x_ep0_read_register(chip, MS_TRANS_CFG, &val);

2831 rts51x_clear_ms_error(chip);

2832 if (val & MS_INT_BREQ)

2833 ms_send_cmd(chip, PRO_STOP, WAIT_INT);

2834 if (val & (MS_CRC16_ERR | MS_RDY_TIMEOUT)) {

2835 RTS51X_DEBUGP("MSPro CRC error, tune clock!\n");

2836 ms_auto_tune_clock(chip);

2837 }

2838

2839 TRACE_RET(chip, retval);

2840 }

2841

2842 ms_card->pre_sec_addr = start_sector;

2843 ms_card->pre_sec_cnt = sector_cnt;

2844 ms_card->pre_dir = srb->sc_data_direction;

2845 ms_card->total_sec_cnt += sector_cnt;

2846

2847 return STATUS_SUCCESS;

2848 }

2849

2850 static int mspro_read_format_progress(struct rts51x_chip *chip,

2851 const int short_data_len)

2852 {

2853 struct ms_info *ms_card = &(chip->ms_card);

2854 int retval, i;

2855 u32 total_progress, cur_progress;

2856 u8 cnt, tmp;

2857 u8 data[8];

2858

2859 ms_card->format_status = FORMAT_FAIL;

2860

2861 retval = ms_switch_clock(chip);

2862 if (retval != STATUS_SUCCESS)

2863 TRACE_RET(chip, retval);

2864

2865 RTS51X_READ_REG(chip, MS_TRANS_CFG, &tmp);

2866

2867 if ((tmp & (MS_INT_CED | MS_INT_CMDNK | MS_INT_ERR)) == MS_INT_CED) {

2868 ms_card->format_status = FORMAT_SUCCESS;

2869 ms_card->pro_under_formatting = 0;

2870 return STATUS_SUCCESS;

2871 }

2872 if (!

2873 ((tmp & (MS_INT_BREQ | MS_INT_CED | MS_INT_CMDNK | MS_INT_ERR)) ==

2874 MS_INT_BREQ)) {

2875 ms_card->pro_under_formatting = 0;

2876 TRACE_RET(chip, STATUS_FAIL);

2877 }

2878

2879 if (short_data_len >= 256)

2880 cnt = 0;

2881 else

2882 cnt = (u8) short_data_len;

2883

2884 retval =

2885 ms_read_bytes(chip, PRO_READ_SHORT_DATA, cnt, WAIT_INT, data, 8);

2886 if (retval != STATUS_SUCCESS)

2887 TRACE_RET(chip, retval);

2888

2889 total_progress =

2890 (data[0] << 24) | (data[1] << 16) | (data[2] << 8) | data[3];

2891 cur_progress =

2892 (data[4] << 24) | (data[5] << 16) | (data[6] << 8) | data[7];

2893

2894 RTS51X_DEBUGP("total_progress = %d, cur_progress = %d\n",

2895 total_progress, cur_progress);

2896

2897 if (total_progress == 0) {

2898 ms_card->progress = 0;

2899 } else {

2900 u64 ulltmp = (u64) cur_progress * (u64) 65535;

2901 do_div(ulltmp, total_progress);

2902 ms_card->progress = (u16) ulltmp;

2903 }

2904 RTS51X_DEBUGP("progress = %d\n", ms_card->progress);

2905

2906 for (i = 0; i < 2500; i++) {

2907 RTS51X_READ_REG(chip, MS_TRANS_CFG, &tmp);

2908 if (tmp &

2909 (MS_INT_CED | MS_INT_CMDNK | MS_INT_BREQ | MS_INT_ERR))

2910 break;

2911

2912 wait_timeout(1);

2913 }

2914

2915 if (i == 2500)

2916 TRACE_RET(chip, STATUS_FAIL);

2917

2918 RTS51X_DEBUGP("MSPro format tmp:%d\n", tmp);

2919

2920 if (tmp & (MS_INT_CMDNK | MS_INT_ERR))

2921 TRACE_RET(chip, STATUS_FAIL);

2922 if (tmp & MS_INT_CED) {

2923 ms_card->format_status = FORMAT_SUCCESS;

2924 ms_card->pro_under_formatting = 0;

2925 } else if (tmp & MS_INT_BREQ) {

2926 ms_card->format_status = FORMAT_IN_PROGRESS;

2927 } else {

2928 ms_card->format_status = FORMAT_FAIL;

2929 ms_card->pro_under_formatting = 0;

2930 TRACE_RET(chip, STATUS_FAIL);

2931 }

2932

2933 RTS51X_DEBUGP("MSPro format format_status:%d\n",

2934 ms_card->format_status);

2935

2936 return STATUS_SUCCESS;

2937 }

2938

2939 void mspro_polling_format_status(struct rts51x_chip *chip)

2940 {

2941 struct ms_info *ms_card = &(chip->ms_card);

2942 int i;

2943

2944 if (ms_card->pro_under_formatting) {

2945 for (i = 0; i < 65535; i++) {

2946 mspro_read_format_progress(chip, MS_SHORT_DATA_LEN);

2947 if (ms_card->format_status != FORMAT_IN_PROGRESS)

2948 break;

2949 }

2950 }

2951

2952 return;

2953 }

2954

2955 void mspro_format_sense(struct rts51x_chip *chip, unsigned int lun)

2956 {

2957 struct ms_info *ms_card = &(chip->ms_card);

2958

2959 if (CHK_FORMAT_STATUS(ms_card, FORMAT_SUCCESS)) {

2960 set_sense_type(chip, lun, SENSE_TYPE_NO_SENSE);

2961 ms_card->pro_under_formatting = 0;

2962 ms_card->progress = 0;

2963 } else if (CHK_FORMAT_STATUS(ms_card, FORMAT_IN_PROGRESS)) {

2964 set_sense_data(chip, lun, CUR_ERR, 0x02, 0, 0x04, 0x04,

2965 0, (u16) (ms_card->progress));

2966 } else {

2967 set_sense_type(chip, lun, SENSE_TYPE_FORMAT_CMD_FAILED);

2968 ms_card->pro_under_formatting = 0;

2969 ms_card->progress = 0;

2970 }

2971 }

2972

2973 int mspro_format(struct scsi_cmnd *srb, struct rts51x_chip *chip,

2974 int short_data_len, int quick_format)

2975 {

2976 struct ms_info *ms_card = &(chip->ms_card);

2977 int retval, i;

2978 u8 buf[8], tmp;

2979 u16 para;

2980

2981 retval = ms_switch_clock(chip);

2982 if (retval != STATUS_SUCCESS)

2983 TRACE_RET(chip, retval);

2984

2985 retval = ms_set_rw_reg_addr(chip, 0x00, 0x00, Pro_TPCParm, 0x01);

2986 if (retval != STATUS_SUCCESS)

2987 TRACE_RET(chip, retval);

2988

2989 memset(buf, 0, 2);

2990 switch (short_data_len) {

2991 case 32:

2992 buf[0] = 0;

2993 break;

2994 case 64:

2995 buf[0] = 1;

2996 break;

2997 case 128:

2998 buf[0] = 2;

2999 break;

3000 case 256:

3001 default:

3002 buf[0] = 3;

3003 break;

3004 }

3005

3006 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {

3007 retval =

3008 ms_write_bytes(chip, PRO_WRITE_REG, 1, NO_WAIT_INT, buf, 2);

3009 if (retval == STATUS_SUCCESS)

3010 break;

3011 }

3012 if (i == MS_MAX_RETRY_COUNT)

3013 TRACE_RET(chip, STATUS_FAIL);

3014 /* Format command */

3015 if (quick_format)

3016 para = 0x0000;

3017 else

3018 para = 0x0001;

3019 retval = mspro_set_rw_cmd(chip, 0, para, PRO_FORMAT);

3020 if (retval != STATUS_SUCCESS)

3021 TRACE_RET(chip, retval);

3022 /* Check INT */

3023 RTS51X_READ_REG(chip, MS_TRANS_CFG, &tmp);

3024 if (tmp & (MS_INT_CMDNK | MS_INT_ERR))

3025 TRACE_RET(chip, STATUS_FAIL);

3026

3027 if ((tmp & (MS_INT_BREQ | MS_INT_CED)) == MS_INT_BREQ) {

3028 ms_card->pro_under_formatting = 1;

3029 ms_card->progress = 0;

3030 ms_card->format_status = FORMAT_IN_PROGRESS;

3031 return STATUS_SUCCESS;

3032 }

3033

3034 if (tmp & MS_INT_CED) {

3035 ms_card->pro_under_formatting = 0;

3036 ms_card->progress = 0;

3037 ms_card->format_status = FORMAT_SUCCESS;

3038 set_sense_type(chip, SCSI_LUN(srb), SENSE_TYPE_NO_SENSE);

3039 return STATUS_SUCCESS;

3040 }

3041

3042 TRACE_RET(chip, STATUS_FAIL);

3043 }

3044

3045 #ifdef MS_SPEEDUP

3046 static int ms_read_multiple_pages(struct rts51x_chip *chip, u16 phy_blk,

3047 u16 log_blk, u8 start_page, u8 end_page,

3048 u8 *buf, void **ptr, unsigned int *offset)

3049 {

3050 struct ms_info *ms_card = &(chip->ms_card);

3051 int retval;

3052 int send_blkend;

3053 u8 extra[MS_EXTRA_SIZE], val1, val2, data[6];

3054 u8 page_cnt = end_page - start_page, page_addr, sec_cnt;

3055

3056 if (end_page != (ms_card->page_off + 1))

3057 send_blkend = 1;

3058 else

3059 send_blkend = 0;

3060

3061 retval =

3062 ms_read_extra_data(chip, phy_blk, start_page, extra, MS_EXTRA_SIZE);

3063 if (retval == STATUS_SUCCESS) {

3064 if ((extra[1] & 0x30) != 0x30) {

3065 ms_set_err_code(chip, MS_FLASH_READ_ERROR);

3066 TRACE_RET(chip, STATUS_FAIL);

3067 }

3068 }

3069

3070 if (CHK_MS4BIT(ms_card)) {

3071 /* Parallel interface */

3072 data[0] = 0x88;

3073 } else {

3074 /* Serial interface */

3075 data[0] = 0x80;

3076 }

3077 /* Block Address */

3078 data[1] = 0;

3079 data[2] = (u8) (phy_blk >> 8);

3080 data[3] = (u8) phy_blk;

3081 /* Page Number

3082 * Extra data access mode */

3083 data[4] = 0;

3084 data[5] = start_page;

3085

3086 retval =

3087 ms_auto_set_cmd(chip, OverwriteFlag, MS_EXTRA_SIZE, SystemParm, 6,

3088 BLOCK_READ, WAIT_INT, data, 6, &val1);

3089 if (retval != STATUS_SUCCESS)

3090 TRACE_RET(chip, retval);

3091

3092 rts51x_init_cmd(chip);

3093

3094 if (send_blkend)

3095 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_BLKEND, SET_BLKEND,

3096 SET_BLKEND);

3097 else

3098 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_BLKEND, SET_BLKEND, 0);

3099 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, WAIT_INT,

3100 NO_WAIT_INT);

3101 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_SECTOR_CNT_L, 0xFF,

3102 (u8) page_cnt);

3103 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_SECTOR_CNT_H, 0xFF, 0);

3104 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, READ_PAGE_DATA);

3105

3106 trans_dma_enable(DMA_FROM_DEVICE, chip, 512 * page_cnt, DMA_512);

3107

3108 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 0xFF,

3109 MS_TRANSFER_START | MS_TM_MULTI_READ);

3110 rts51x_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER, MS_TRANSFER_END,

3111 MS_TRANSFER_END);

3112

3113 retval = rts51x_send_cmd(chip, MODE_CDIR | STAGE_MS_STATUS, 100);

3114 if (retval != STATUS_SUCCESS)

3115 TRACE_RET(chip, retval);

3116

3117 retval =

3118 rts51x_transfer_data_partial(chip, RCV_BULK_PIPE(chip), (void *)buf,

3119 ptr, offset, 512 * page_cnt,

3120 scsi_sg_count(chip->srb), NULL, 2000);

3121 if (retval != STATUS_SUCCESS) {

3122 rts51x_clear_ms_error(chip);

3123 if (retval == STATUS_TIMEDOUT)

3124 TRACE_RET(chip, retval);

3125 TRACE_GOTO(chip, Fail);

3126 }

3127 retval = rts51x_get_rsp(chip, 3, 200);

3128 if (CHECK_MS_TRANS_FAIL(chip, retval)) {

3129 rts51x_clear_ms_error(chip);

3130 if (retval == STATUS_TIMEDOUT)

3131 TRACE_RET(chip, retval);

3132 TRACE_GOTO(chip, Fail);

3133 }

3134

3135 return STATUS_SUCCESS;

3136

3137 Fail:

3138 rts51x_init_cmd(chip);

3139

3140 rts51x_add_cmd(chip, READ_REG_CMD, MS_SECTOR_CNT_L, 0, 0);

3141

3142 retval = rts51x_send_cmd(chip, MODE_CR | STAGE_MS_STATUS, 100);

3143 if (retval != STATUS_SUCCESS)

3144 TRACE_RET(chip, retval);

3145

3146 retval = rts51x_get_rsp(chip, 3, 200);

3147

3148 if (CHECK_MS_TRANS_FAIL(chip, retval))

3149 TRACE_RET(chip, STATUS_FAIL);

3150

3151 sec_cnt = chip->rsp_buf[0];

3152 RTS51X_DEBUGP("%d pages need be transferred, %d pages remained\n",

3153 (int)page_cnt, (int)sec_cnt);

3154 page_addr = start_page + (page_cnt - sec_cnt);

3155

3156 if (CHK_MS4BIT(ms_card)) {

3157 val1 = chip->rsp_buf[1];

3158 RTS51X_DEBUGP("MS_TRANS_CFG: 0x%x\n", val1);

3159 } else {

3160 val1 = 0;

3161 }

3162

3163 val2 = chip->rsp_buf[2];

3164 RTS51X_DEBUGP("GET_INT: 0x%x\n", val2);

3165

3166 if ((val1 & INT_CMDNK) || (val2 & INT_REG_CMDNK)) {

3167 ms_set_err_code(chip, MS_CMD_NK);

3168 TRACE_RET(chip, STATUS_FAIL);

3169 }

3170

3171 if ((val1 & INT_ERR) || (val2 & INT_REG_ERR)) {

3172 if ((val1 & INT_BREQ) || (val2 & INT_REG_BREQ)) {

3173 retval = ms_read_status_reg(chip);

3174 if (retval != STATUS_SUCCESS) {

3175 if (!(chip->card_wp & MS_CARD)) {

3176 reset_ms(chip);

3177 ms_set_page_status(log_blk, setPS_NG,

3178 extra, MS_EXTRA_SIZE);

3179 ms_write_extra_data(chip, phy_blk,

3180 page_addr, extra,

3181 MS_EXTRA_SIZE);

3182 }

3183 ms_set_err_code(chip, MS_FLASH_READ_ERROR);

3184 TRACE_RET(chip, STATUS_FAIL);

3185 }

3186 } else {

3187 ms_set_err_code(chip, MS_FLASH_READ_ERROR);

3188 TRACE_RET(chip, STATUS_FAIL);

3189 }

3190 } else {

3191 if (CHK_MS4BIT(ms_card)) {

3192 if (!(val1 & INT_BREQ) && !(val2 & INT_REG_BREQ)) {

3193 ms_set_err_code(chip, MS_BREQ_ERROR);

3194 TRACE_RET(chip, STATUS_FAIL);

3195 }

3196 } else {

3197 if (!(val2 & INT_REG_BREQ)) {

3198 ms_set_err_code(chip, MS_BREQ_ERROR);

3199 TRACE_RET(chip, STATUS_FAIL);

3200 }

3201 }

3202 }

3203

3204 TRACE_RET(chip, STATUS_FAIL);

3205 }

3206

3207 static int ms_write_multiple_pages(struct rts51x_chip *chip, u16 old_blk,

3208 u16 new_blk, u16 log_blk, u8 start_page,

3209 u8 end_page, u8 *buf, void **ptr,

3210 unsigned int *offset)

3211 {

3212 struct ms_info *ms_card = &(chip->ms_card);

3213 int retval, i;

3214 int send_blkend;

3215 u8 val, data[16];

3216 u8 page_cnt = end_page - start_page;

3217

3218 if ((end_page == (ms_card->page_off + 1)) || (page_cnt == 1))

3219 send_blkend = 0;

3220 else

3221 send_blkend = 1;

3222

3223 if (!start_page) {

3224 if (CHK_MS4BIT(ms_card)) {

3225 /* Parallel interface */

3226 data[0] = 0x88;

3227 } else {

3228 /* Serial interface */

3229 data[0] = 0x80;

3230 }

3231 /* Block Address */

3232 data[1] = 0;

3233 data[2] = (u8) (old_blk >> 8);

3234 data[3] = (u8) old_blk;

3235 data[4] = 0x80;

3236 data[5] = 0;

3237 data[6] = 0xEF;

3238 data[7] = 0xFF;

3239

3240 retval =

3241 ms_auto_set_cmd(chip, OverwriteFlag, MS_EXTRA_SIZE,

3242 SystemParm, 7, BLOCK_WRITE, WAIT_INT, data,

3243 7, &val);

3244 if (retval != STATUS_SUCCESS)

3245 TRACE_RET(chip, retval);

3246 }

3247

3248 retval =

3249 ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE, SystemParm,

3250 (6 + MS_EXTRA_SIZE));

3251 if (retval != STATUS_SUCCESS)

3252 TRACE_RET(chip, retval);

3253

3254 ms_set_err_code(chip, MS_NO_ERROR);

3255

3256 if (CHK_MS4BIT(ms_card)) {

3257 /* Parallel interface */

3258 data[0] = 0x88;

3259 } else {

3260 /* Serial interface */

3261 data[0] = 0x80;

3262 }

3263 /* Block Address */

3264 data[1] = 0;

3265 data[2] = (u8) (new_blk >> 8);

3266 data[3] = (u8) new_blk;

3267 /* Page Number

3268 * Extra data access mode */

3269 if (page_cnt == 1) {

3270 /* Single page access mode */

3271 data[4] = 0x20;

3272 } else {

3273 /* Block access mode */

3274 data[4] = 0;

3275 }

3276 data[5] = start_page;

3277 data[6] = 0xF8;

3278 data[7] = 0xFF;

3279 data[8] = (u8) (log_blk >> 8);

3280 data[9] = (u8) log_blk;

3281

3282 for (i = 0x0A; i < 0x10; i++) {

3283 /* ECC */

3284 data[i] = 0xFF;

3285 }

3286

3287 retval =

3288 ms_auto_set_cmd(chip, OverwriteFlag, MS_EXTRA_SIZE, SystemParm,

3289 (6 + MS_EXTRA_SIZE), BLOCK_WRITE, WAIT_INT, data,

3290 16, &val);

3291 if (retval != STATUS_SUCCESS)

3292 TRACE_RET(chip, retval);

3293

3294 rts51x_init_cmd(chip);

3295

3296 if (send_blkend)

3297 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_BLKEND, SET_BLKEND,

3298 SET_BLKEND);

3299 else

3300 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_BLKEND, SET_BLKEND, 0);

3301 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, WAIT_INT,

3302 NO_WAIT_INT);

3303 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_SECTOR_CNT_L, 0xFF,

3304 (u8) page_cnt);

3305 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_SECTOR_CNT_H, 0xFF, 0);

3306 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, WRITE_PAGE_DATA);

3307 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01,

3308 RING_BUFFER);

3309

3310 trans_dma_enable(DMA_TO_DEVICE, chip, 512 * page_cnt, DMA_512);

3311

3312 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 0xFF,

3313 MS_TRANSFER_START | MS_TM_MULTI_WRITE);

3314 rts51x_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER, MS_TRANSFER_END,

3315 MS_TRANSFER_END);

3316

3317 retval = rts51x_send_cmd(chip, MODE_CDOR | STAGE_MS_STATUS, 100);

3318 if (retval != STATUS_SUCCESS)

3319 TRACE_RET(chip, retval);

3320

3321 retval =

3322 rts51x_transfer_data_partial(chip, SND_BULK_PIPE(chip), (void *)buf,

3323 ptr, offset, 512 * page_cnt,

3324 scsi_sg_count(chip->srb), NULL, 2000);

3325 if (retval != STATUS_SUCCESS) {

3326 rts51x_clear_ms_error(chip);

3327 TRACE_RET(chip, retval);

3328 }

3329

3330 retval = rts51x_get_rsp(chip, 3, 2000);

3331

3332

3333 if (CHECK_MS_TRANS_FAIL(chip, retval)) {

3334 rts51x_clear_ms_error(chip);

3335 TRACE_RET(chip, STATUS_FAIL);

3336 }

3337

3338 return STATUS_SUCCESS;

3339 }

3340

3341 #else

3342

3343 static int ms_read_multiple_pages(struct rts51x_chip *chip, u16 phy_blk,

3344 u16 log_blk, u8 start_page, u8 end_page,

3345 u8 *buf, void **ptr, unsigned int *offset)

3346 {

3347 struct ms_info *ms_card = &(chip->ms_card);

3348 int retval, i;

3349 u8 extra[MS_EXTRA_SIZE], page_addr, val, trans_cfg, data[6];

3350

3351 retval =

3352 ms_read_extra_data(chip, phy_blk, start_page, extra, MS_EXTRA_SIZE);

3353 if (retval == STATUS_SUCCESS) {

3354 if ((extra[1] & 0x30) != 0x30) {

3355 ms_set_err_code(chip, MS_FLASH_READ_ERROR);

3356 TRACE_RET(chip, STATUS_FAIL);

3357 }

3358 }

3359

3360 retval =

3361 ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE, SystemParm,

3362 6);

3363 if (retval != STATUS_SUCCESS)

3364 TRACE_RET(chip, retval);

3365 /* Write REG */

3366 if (CHK_MS4BIT(ms_card)) {

3367 /* Parallel interface */

3368 data[0] = 0x88;

3369 } else {

3370 /* Serial interface */

3371 data[0] = 0x80;

3372 }

3373 /* Block Address */

3374 data[1] = 0;

3375 data[2] = (u8) (phy_blk >> 8);

3376 data[3] = (u8) phy_blk;

3377 /* Page Number

3378 * Extra data access mode */

3379 data[4] = 0;

3380 data[5] = start_page;

3381

3382 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {

3383 retval =

3384 ms_write_bytes(chip, WRITE_REG, 6, NO_WAIT_INT, data, 6);

3385 if (retval == STATUS_SUCCESS)

3386 break;

3387 }

3388 if (i == MS_MAX_RETRY_COUNT)

3389 TRACE_RET(chip, STATUS_FAIL);

3390

3391 ms_set_err_code(chip, MS_NO_ERROR);

3392

3393 retval = ms_send_cmd(chip, BLOCK_READ, WAIT_INT);

3394 if (retval != STATUS_SUCCESS)

3395 TRACE_RET(chip, retval);

3396

3397 for (page_addr = start_page; page_addr < end_page; page_addr++) {

3398 ms_set_err_code(chip, MS_NO_ERROR);

3399

3400 if (monitor_card_cd(chip, MS_CARD) == CD_NOT_EXIST) {

3401 ms_set_err_code(chip, MS_NO_CARD);

3402 chip->card_exist &= ~MS_CARD;

3403 chip->card_ready &= ~MS_CARD;

3404 TRACE_RET(chip, STATUS_FAIL);

3405 }

3406 /* GET_INT Register */

3407 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);

3408 if (retval != STATUS_SUCCESS)

3409 TRACE_RET(chip, retval);

3410 if (val & INT_REG_CMDNK) {

3411 ms_set_err_code(chip, MS_CMD_NK);

3412 TRACE_RET(chip, STATUS_FAIL);

3413 }

3414 if (val & INT_REG_ERR) {

3415 if (val & INT_REG_BREQ) {

3416 retval = ms_read_status_reg(chip);

3417 if (retval != STATUS_SUCCESS) {

3418 if (!(chip->card_wp & MS_CARD)) {

3419 reset_ms(chip);

3420 ms_set_page_status(log_blk,

3421 setPS_NG, extra,

3422 MS_EXTRA_SIZE);

3423 ms_write_extra_data(chip,

3424 phy_blk, page_addr,

3425 extra, MS_EXTRA_SIZE);

3426 }

3427 ms_set_err_code(chip,

3428 MS_FLASH_READ_ERROR);

3429 TRACE_RET(chip, STATUS_FAIL);

3430 }

3431 } else {

3432 ms_set_err_code(chip, MS_FLASH_READ_ERROR);

3433 TRACE_RET(chip, STATUS_FAIL);

3434 }

3435 } else {

3436 if (!(val & INT_REG_BREQ)) {

3437 ms_set_err_code(chip, MS_BREQ_ERROR);

3438 TRACE_RET(chip, STATUS_FAIL);

3439 }

3440 }

3441

3442 if (page_addr == (end_page - 1)) {

3443 if (!(val & INT_REG_CED)) {

3444 retval = ms_send_cmd(chip, BLOCK_END, WAIT_INT);

3445 if (retval != STATUS_SUCCESS)

3446 TRACE_RET(chip, retval);

3447 }

3448 retval =

3449 ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val,

3450 1);

3451 if (retval != STATUS_SUCCESS)

3452 TRACE_RET(chip, retval);

3453 if (!(val & INT_REG_CED)) {

3454 ms_set_err_code(chip, MS_FLASH_READ_ERROR);

3455 TRACE_RET(chip, STATUS_FAIL);

3456 }

3457

3458 trans_cfg = NO_WAIT_INT;

3459 } else {

3460 trans_cfg = WAIT_INT;

3461 }

3462

3463 rts51x_init_cmd(chip);

3464

3465 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF,

3466 READ_PAGE_DATA);

3467 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF,

3468 trans_cfg);

3469

3470 trans_dma_enable(DMA_FROM_DEVICE, chip, 512, DMA_512);

3471

3472 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 0xFF,

3473 MS_TRANSFER_START | MS_TM_NORMAL_READ);

3474 rts51x_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER,

3475 MS_TRANSFER_END, MS_TRANSFER_END);

3476

3477 retval = rts51x_send_cmd(chip, MODE_CDIR, 100);

3478 if (retval != STATUS_SUCCESS)

3479 TRACE_RET(chip, retval);

3480

3481 retval =

3482 rts51x_transfer_data_partial(chip, RCV_BULK_PIPE(chip),

3483 (void *)buf, ptr, offset, 512,

3484 scsi_sg_count(chip->srb), NULL,

3485 2000);

3486 if (retval != STATUS_SUCCESS) {

3487 if (retval == STATUS_TIMEDOUT) {

3488 ms_set_err_code(chip, MS_TO_ERROR);

3489 rts51x_clear_ms_error(chip);

3490 TRACE_RET(chip, retval);

3491 }

3492

3493 retval =

3494 rts51x_ep0_read_register(chip, MS_TRANS_CFG, &val);

3495 if (retval != STATUS_SUCCESS) {

3496 ms_set_err_code(chip, MS_TO_ERROR);

3497 rts51x_clear_ms_error(chip);

3498 TRACE_RET(chip, STATUS_FAIL);

3499 }

3500 if (val & (MS_CRC16_ERR | MS_RDY_TIMEOUT)) {

3501 ms_set_err_code(chip, MS_CRC16_ERROR);

3502 rts51x_clear_ms_error(chip);

3503 TRACE_RET(chip, STATUS_FAIL);

3504 }

3505 }

3506

3507 retval = rts51x_get_rsp(chip, 1, 2000);

3508 if (CHECK_MS_TRANS_FAIL(chip, retval)) {

3509 if (retval == STATUS_TIMEDOUT) {

3510 ms_set_err_code(chip, MS_TO_ERROR);

3511 rts51x_clear_ms_error(chip);

3512 TRACE_RET(chip, retval);

3513 }

3514

3515 retval =

3516 rts51x_ep0_read_register(chip, MS_TRANS_CFG, &val);

3517 if (retval != STATUS_SUCCESS) {

3518 ms_set_err_code(chip, MS_TO_ERROR);

3519 rts51x_clear_ms_error(chip);

3520 TRACE_RET(chip, retval);

3521 }

3522 if (val & (MS_CRC16_ERR | MS_RDY_TIMEOUT)) {

3523 ms_set_err_code(chip, MS_CRC16_ERROR);

3524 rts51x_clear_ms_error(chip);

3525 TRACE_RET(chip, STATUS_FAIL);

3526 }

3527 }

3528 }

3529

3530 return STATUS_SUCCESS;

3531 }

3532

3533 static int ms_write_multiple_pages(struct rts51x_chip *chip, u16 old_blk,

3534 u16 new_blk, u16 log_blk, u8 start_page,

3535 u8 end_page, u8 *buf, void **ptr,

3536 unsigned int *offset)

3537 {

3538 struct ms_info *ms_card = &(chip->ms_card);

3539 int retval, i;

3540 u8 page_addr, val, data[16];

3541

3542 if (!start_page) {

3543 retval =

3544 ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE,

3545 SystemParm, 7);

3546 if (retval != STATUS_SUCCESS)

3547 TRACE_RET(chip, retval);

3548

3549 if (CHK_MS4BIT(ms_card)) {

3550 /* Parallel interface */

3551 data[0] = 0x88;

3552 } else {

3553 /* Serial interface */

3554 data[0] = 0x80;

3555 }

3556 /* Block Address */

3557 data[1] = 0;

3558 data[2] = (u8) (old_blk >> 8);

3559 data[3] = (u8) old_blk;

3560 data[4] = 0x80;

3561 data[5] = 0;

3562 data[6] = 0xEF;

3563 data[7] = 0xFF;

3564

3565 retval =

3566 ms_write_bytes(chip, WRITE_REG, 7, NO_WAIT_INT, data, 8);

3567 if (retval != STATUS_SUCCESS)

3568 TRACE_RET(chip, retval);

3569

3570 retval = ms_send_cmd(chip, BLOCK_WRITE, WAIT_INT);

3571 if (retval != STATUS_SUCCESS)

3572 TRACE_RET(chip, retval);

3573 /* GET_INT Register */

3574 ms_set_err_code(chip, MS_NO_ERROR);

3575 retval =

3576 ms_transfer_tpc(chip, MS_TM_READ_BYTES, GET_INT, 1,

3577 NO_WAIT_INT);

3578 if (retval != STATUS_SUCCESS)

3579 TRACE_RET(chip, retval);

3580 }

3581

3582 retval =

3583 ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE, SystemParm,

3584 (6 + MS_EXTRA_SIZE));

3585 if (retval != STATUS_SUCCESS)

3586 TRACE_RET(chip, retval);

3587

3588 ms_set_err_code(chip, MS_NO_ERROR);

3589

3590 if (CHK_MS4BIT(ms_card)) {

3591 /* Parallel interface */

3592 data[0] = 0x88;

3593 } else {

3594 /* Serial interface */

3595 data[0] = 0x80;

3596 }

3597 /* Block Address */

3598 data[1] = 0;

3599 data[2] = (u8) (new_blk >> 8);

3600 data[3] = (u8) new_blk;

3601 /* Page Number

3602 * Extra data access mode */

3603 if ((end_page - start_page) == 1) {

3604 /* Single page access mode */

3605 data[4] = 0x20;

3606 } else {

3607 /* Block access mode */

3608 data[4] = 0;

3609 }

3610 data[5] = start_page;

3611 data[6] = 0xF8;

3612 data[7] = 0xFF;

3613 data[8] = (u8) (log_blk >> 8);

3614 data[9] = (u8) log_blk;

3615

3616 for (i = 0x0A; i < 0x10; i++) {

3617 /* ECC */

3618 data[i] = 0xFF;

3619 }

3620

3621 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {

3622 retval =

3623 ms_write_bytes(chip, WRITE_REG, 6 + MS_EXTRA_SIZE,

3624 NO_WAIT_INT, data, 16);

3625 if (retval == STATUS_SUCCESS)

3626 break;

3627 }

3628 if (i == MS_MAX_RETRY_COUNT)

3629 TRACE_RET(chip, STATUS_FAIL);

3630

3631 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {

3632 retval = ms_send_cmd(chip, BLOCK_WRITE, WAIT_INT);

3633 if (retval == STATUS_SUCCESS)

3634 break;

3635 }

3636 if (i == MS_MAX_RETRY_COUNT)

3637 TRACE_RET(chip, STATUS_FAIL);

3638 /* GET_INT Register */

3639 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);

3640 if (retval != STATUS_SUCCESS)

3641 TRACE_RET(chip, retval);

3642

3643 for (page_addr = start_page; page_addr < end_page; page_addr++) {

3644 ms_set_err_code(chip, MS_NO_ERROR);

3645

3646 if (monitor_card_cd(chip, MS_CARD) == CD_NOT_EXIST) {

3647 ms_set_err_code(chip, MS_NO_CARD);

3648 TRACE_RET(chip, STATUS_FAIL);

3649 }

3650

3651 if (val & INT_REG_CMDNK) {

3652 ms_set_err_code(chip, MS_CMD_NK);

3653 TRACE_RET(chip, STATUS_FAIL);

3654 }

3655 if (val & INT_REG_ERR) {

3656 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR);

3657 TRACE_RET(chip, STATUS_FAIL);

3658 }

3659 if (!(val & INT_REG_BREQ)) {

3660 ms_set_err_code(chip, MS_BREQ_ERROR);

3661 TRACE_RET(chip, STATUS_FAIL);

3662 }

3663

3664 udelay(30);

3665

3666 rts51x_init_cmd(chip);

3667

3668 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF,

3669 WRITE_PAGE_DATA);

3670 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF,

3671 WAIT_INT);

3672

3673 trans_dma_enable(DMA_TO_DEVICE, chip, 512, DMA_512);

3674

3675 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 0xFF,

3676 MS_TRANSFER_START | MS_TM_NORMAL_WRITE);

3677 rts51x_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER,

3678 MS_TRANSFER_END, MS_TRANSFER_END);

3679

3680 retval = rts51x_send_cmd(chip, MODE_CDOR, 100);

3681 if (retval != STATUS_SUCCESS)

3682 TRACE_RET(chip, retval);

3683

3684 retval =

3685 rts51x_transfer_data_partial(chip, SND_BULK_PIPE(chip),

3686 (void *)buf, ptr, offset, 512,

3687 scsi_sg_count(chip->srb), NULL,

3688 2000);

3689 if (retval != STATUS_SUCCESS) {

3690 ms_set_err_code(chip, MS_TO_ERROR);

3691 rts51x_clear_ms_error(chip);

3692

3693 if (retval == STATUS_TIMEDOUT)

3694 TRACE_RET(chip, STATUS_TIMEDOUT);

3695 else

3696 TRACE_RET(chip, STATUS_FAIL);

3697 }

3698

3699 retval = rts51x_get_rsp(chip, 1, 2000);

3700 if (CHECK_MS_TRANS_FAIL(chip, retval)) {

3701 ms_set_err_code(chip, MS_TO_ERROR);

3702 rts51x_clear_ms_error(chip);

3703

3704 if (retval == STATUS_TIMEDOUT)

3705 TRACE_RET(chip, STATUS_TIMEDOUT);

3706 else

3707 TRACE_RET(chip, STATUS_FAIL);

3708 }

3709 /* GET_INT Register */

3710 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);

3711 if (retval != STATUS_SUCCESS)

3712 TRACE_RET(chip, retval);

3713

3714 if ((end_page - start_page) == 1) {

3715 if (!(val & INT_REG_CED)) {

3716 /* Command can not be executed */

3717 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR);

3718 TRACE_RET(chip, STATUS_FAIL);

3719 }

3720 } else {

3721 if (page_addr == (end_page - 1)) {

3722 if (!(val & INT_REG_CED)) {

3723 retval =

3724 ms_send_cmd(chip, BLOCK_END,

3725 WAIT_INT);

3726 if (retval != STATUS_SUCCESS)

3727 TRACE_RET(chip, retval);

3728 }

3729 /* GET_INT Register */

3730 retval =

3731 ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT,

3732 &val, 1);

3733 if (retval != STATUS_SUCCESS)

3734 TRACE_RET(chip, retval);

3735 }

3736

3737 if ((page_addr == (end_page - 1))

3738 || (page_addr == ms_card->page_off)) {

3739 if (!(val & INT_REG_CED)) {

3740 ms_set_err_code(chip,

3741 MS_FLASH_WRITE_ERROR);

3742 TRACE_RET(chip, STATUS_FAIL);

3743 }

3744 }

3745 }

3746 }

3747

3748 return STATUS_SUCCESS;

3749 }

3750 #endif

3751

3752 static int ms_finish_write(struct rts51x_chip *chip, u16 old_blk, u16 new_blk,

3753 u16 log_blk, u8 page_off)

3754 {

3755 struct ms_info *ms_card = &(chip->ms_card);

3756 int retval, seg_no;

3757

3758 #ifdef MS_SPEEDUP

3759 retval = ms_auto_copy_page(chip, old_blk, new_blk, log_blk,

3760 page_off, ms_card->page_off + 1);

3761 #else

3762 retval = ms_copy_page(chip, old_blk, new_blk, log_blk,

3763 page_off, ms_card->page_off + 1);

3764 #endif

3765 if (retval != STATUS_SUCCESS)

3766 TRACE_RET(chip, retval);

3767

3768 seg_no = old_blk >> 9;

3769

3770 if (MS_TST_BAD_BLOCK_FLG(ms_card)) {

3771 MS_CLR_BAD_BLOCK_FLG(ms_card);

3772 ms_set_bad_block(chip, old_blk);

3773 } else {

3774 retval = ms_erase_block(chip, old_blk);

3775 if (retval == STATUS_SUCCESS)

3776 ms_set_unused_block(chip, old_blk);

3777 }

3778

3779 ms_set_l2p_tbl(chip, seg_no, log_blk - ms_start_idx[seg_no], new_blk);

3780

3781 return STATUS_SUCCESS;

3782 }

3783

3784 static int ms_prepare_write(struct rts51x_chip *chip, u16 old_blk, u16 new_blk,

3785 u16 log_blk, u8 start_page)

3786 {

3787 int retval;

3788

3789 if (start_page) {

3790 #ifdef MS_SPEEDUP

3791 retval =

3792 ms_auto_copy_page(chip, old_blk, new_blk, log_blk, 0,

3793 start_page);

3794 #else

3795 retval =

3796 ms_copy_page(chip, old_blk, new_blk, log_blk, 0,

3797 start_page);

3798 #endif

3799 if (retval != STATUS_SUCCESS)

3800 TRACE_RET(chip, retval);

3801 }

3802

3803 return STATUS_SUCCESS;

3804 }

3805

3806 int ms_delay_write(struct rts51x_chip *chip)

3807 {

3808 struct ms_info *ms_card = &(chip->ms_card);

3809 struct ms_delay_write_tag *delay_write = &(ms_card->delay_write);

3810 int retval;

3811

3812 if (delay_write->delay_write_flag) {

3813 retval = ms_set_init_para(chip);

3814 if (retval != STATUS_SUCCESS)

3815 TRACE_RET(chip, retval);

3816

3817 delay_write->delay_write_flag = 0;

3818 retval = ms_finish_write(chip,

3819 delay_write->old_phyblock,

3820 delay_write->new_phyblock,

3821 delay_write->logblock,

3822 delay_write->pageoff);

3823 if (retval != STATUS_SUCCESS)

3824 TRACE_RET(chip, retval);

3825 }

3826

3827 return STATUS_SUCCESS;

3828 }

3829

3830 static inline void ms_rw_fail(struct scsi_cmnd *srb, struct rts51x_chip *chip)

3831 {

3832 if (srb->sc_data_direction == DMA_FROM_DEVICE)

3833 set_sense_type(chip, SCSI_LUN(srb),

3834 SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);

3835 else

3836 set_sense_type(chip, SCSI_LUN(srb), SENSE_TYPE_MEDIA_WRITE_ERR);

3837 }

3838

3839 static int ms_rw_multi_sector(struct scsi_cmnd *srb, struct rts51x_chip *chip,

3840 u32 start_sector, u16 sector_cnt)

3841 {

3842 struct ms_info *ms_card = &(chip->ms_card);

3843 unsigned int lun = SCSI_LUN(srb);

3844 int retval, seg_no;

3845 unsigned int offset = 0;

3846 u16 old_blk = 0, new_blk = 0, log_blk, total_sec_cnt = sector_cnt;

3847 u8 start_page, end_page = 0, page_cnt;

3848 u8 *buf;

3849 void *ptr = NULL;

3850 struct ms_delay_write_tag *delay_write = &(ms_card->delay_write);

3851

3852 ms_set_err_code(chip, MS_NO_ERROR);

3853

3854 ms_card->counter = 0;

3855

3856 buf = (u8 *) scsi_sglist(srb);

3857

3858 retval = ms_switch_clock(chip);

3859 if (retval != STATUS_SUCCESS) {

3860 ms_rw_fail(srb, chip);

3861 TRACE_RET(chip, retval);

3862 }

3863

3864 log_blk = (u16) (start_sector >> ms_card->block_shift);

3865 start_page = (u8) (start_sector & ms_card->page_off);

3866

3867 for (seg_no = 0; seg_no < ARRAY_SIZE(ms_start_idx) - 1; seg_no++) {

3868 if (log_blk < ms_start_idx[seg_no + 1])

3869 break;

3870 }

3871

3872 if (ms_card->segment[seg_no].build_flag == 0) {

3873 retval = ms_build_l2p_tbl(chip, seg_no);

3874 if (retval != STATUS_SUCCESS) {

3875 chip->card_fail |= MS_CARD;

3876 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);

3877 TRACE_RET(chip, retval);

3878 }

3879 }

3880

3881 if (srb->sc_data_direction == DMA_TO_DEVICE) {

3882 if (delay_write->delay_write_flag &&

3883 (delay_write->logblock == log_blk) &&

3884 (start_page > delay_write->pageoff)) {

3885 delay_write->delay_write_flag = 0;

3886 #ifdef MS_SPEEDUP

3887 retval = ms_auto_copy_page(chip,

3888 delay_write->old_phyblock,

3889 delay_write->new_phyblock,

3890 log_blk,

3891 delay_write->pageoff,

3892 start_page);

3893 #else

3894 retval = ms_copy_page(chip,

3895 delay_write->old_phyblock,

3896 delay_write->new_phyblock,

3897 log_blk, delay_write->pageoff,

3898 start_page);

3899 #endif

3900 if (retval != STATUS_SUCCESS) {

3901 set_sense_type(chip, lun,

3902 SENSE_TYPE_MEDIA_WRITE_ERR);

3903 TRACE_RET(chip, retval);

3904 }

3905 old_blk = delay_write->old_phyblock;

3906 new_blk = delay_write->new_phyblock;

3907 } else if (delay_write->delay_write_flag &&

3908 (delay_write->logblock == log_blk) &&

3909 (start_page == delay_write->pageoff)) {

3910 delay_write->delay_write_flag = 0;

3911 old_blk = delay_write->old_phyblock;

3912 new_blk = delay_write->new_phyblock;

3913 } else {

3914 retval = ms_delay_write(chip);

3915 if (retval != STATUS_SUCCESS) {

3916 set_sense_type(chip, lun,

3917 SENSE_TYPE_MEDIA_WRITE_ERR);

3918 TRACE_RET(chip, retval);

3919 }

3920 old_blk =

3921 ms_get_l2p_tbl(chip, seg_no,

3922 log_blk - ms_start_idx[seg_no]);

3923 new_blk = ms_get_unused_block(chip, seg_no);

3924 if ((old_blk == 0xFFFF) || (new_blk == 0xFFFF)) {

3925 set_sense_type(chip, lun,

3926 SENSE_TYPE_MEDIA_WRITE_ERR);

3927 TRACE_RET(chip, STATUS_FAIL);

3928 }

3929

3930 retval =

3931 ms_prepare_write(chip, old_blk, new_blk, log_blk,

3932 start_page);

3933 if (retval != STATUS_SUCCESS) {

3934 if (monitor_card_cd(chip, MS_CARD) ==

3935 CD_NOT_EXIST) {

3936 set_sense_type(chip, lun,

3937 SENSE_TYPE_MEDIA_NOT_PRESENT);

3938 TRACE_RET(chip, STATUS_FAIL);

3939 }

3940

3941 set_sense_type(chip, lun,

3942 SENSE_TYPE_MEDIA_WRITE_ERR);

3943 TRACE_RET(chip, retval);

3944 }

3945 }

3946 } else {

3947 retval = ms_delay_write(chip);

3948 if (retval != STATUS_SUCCESS) {

3949 if (monitor_card_cd(chip, MS_CARD) == CD_NOT_EXIST) {

3950 set_sense_type(chip, lun,

3951 SENSE_TYPE_MEDIA_NOT_PRESENT);

3952 TRACE_RET(chip, STATUS_FAIL);

3953 }

3954

3955 set_sense_type(chip, lun,

3956 SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);

3957 TRACE_RET(chip, retval);

3958 }

3959 old_blk =

3960 ms_get_l2p_tbl(chip, seg_no,

3961 log_blk - ms_start_idx[seg_no]);

3962 if (old_blk == 0xFFFF) {

3963 set_sense_type(chip, lun,

3964 SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);

3965 TRACE_RET(chip, STATUS_FAIL);

3966 }

3967 }

3968

3969 RTS51X_DEBUGP("seg_no = %d, old_blk = 0x%x, new_blk = 0x%x\n", seg_no,

3970 old_blk, new_blk);

3971

3972 while (total_sec_cnt) {

3973 if ((start_page + total_sec_cnt) > (ms_card->page_off + 1))

3974 end_page = ms_card->page_off + 1;

3975 else

3976 end_page = start_page + (u8) total_sec_cnt;

3977 page_cnt = end_page - start_page;

3978

3979 RTS51X_DEBUGP("start_page = %d, end_page = %d,"

3980 "page_cnt = %d\n",

3981 start_page, end_page, page_cnt);

3982

3983 if (srb->sc_data_direction == DMA_FROM_DEVICE)

3984 retval = ms_read_multiple_pages(chip,

3985 old_blk, log_blk,

3986 start_page, end_page,

3987 buf, &ptr, &offset);

3988 else

3989 retval = ms_write_multiple_pages(chip, old_blk,

3990 new_blk, log_blk,

3991 start_page, end_page,

3992 buf, &ptr, &offset);

3993

3994 if (retval != STATUS_SUCCESS) {

3995 if (monitor_card_cd(chip, MS_CARD) == CD_NOT_EXIST) {

3996 set_sense_type(chip, lun,

3997 SENSE_TYPE_MEDIA_NOT_PRESENT);

3998 TRACE_RET(chip, STATUS_FAIL);

3999 }

4000

4001 ms_rw_fail(srb, chip);

4002 TRACE_RET(chip, retval);

4003 }

4004 /* Update L2P table if need */

4005 if (srb->sc_data_direction == DMA_TO_DEVICE) {

4006 if (end_page == (ms_card->page_off + 1)) {

4007 retval = ms_erase_block(chip, old_blk);

4008 if (retval == STATUS_SUCCESS)

4009 ms_set_unused_block(chip, old_blk);

4010 ms_set_l2p_tbl(chip, seg_no,

4011 log_blk - ms_start_idx[seg_no],

4012 new_blk);

4013 }

4014 }

4015

4016 total_sec_cnt -= page_cnt;

4017

4018 if (total_sec_cnt == 0)

4019 break;

4020

4021 log_blk++;

4022

4023 for (seg_no = 0; seg_no < ARRAY_SIZE(ms_start_idx) - 1;

4024 seg_no++) {

4025 if (log_blk < ms_start_idx[seg_no + 1])

4026 break;

4027 }

4028

4029 if (ms_card->segment[seg_no].build_flag == 0) {

4030 retval = ms_build_l2p_tbl(chip, seg_no);

4031 if (retval != STATUS_SUCCESS) {

4032 chip->card_fail |= MS_CARD;

4033 set_sense_type(chip, lun,

4034 SENSE_TYPE_MEDIA_NOT_PRESENT);

4035 TRACE_RET(chip, retval);

4036 }

4037 }

4038

4039 old_blk =

4040 ms_get_l2p_tbl(chip, seg_no,

4041 log_blk - ms_start_idx[seg_no]);

4042 if (old_blk == 0xFFFF) {

4043 ms_rw_fail(srb, chip);

4044 TRACE_RET(chip, STATUS_FAIL);

4045 }

4046

4047 if (srb->sc_data_direction == DMA_TO_DEVICE) {

4048 new_blk = ms_get_unused_block(chip, seg_no);

4049 if (new_blk == 0xFFFF) {

4050 ms_rw_fail(srb, chip);

4051 TRACE_RET(chip, STATUS_FAIL);

4052 }

4053 }

4054

4055 RTS51X_DEBUGP("seg_no = %d, old_blk = 0x%x, new_blk = 0x%x\n",

4056 seg_no, old_blk, new_blk);

4057

4058 start_page = 0;

4059 }

4060

4061 if (srb->sc_data_direction == DMA_TO_DEVICE) {

4062 if (end_page < (ms_card->page_off + 1)) {

4063 delay_write->delay_write_flag = 1;

4064 delay_write->old_phyblock = old_blk;

4065 delay_write->new_phyblock = new_blk;

4066 delay_write->logblock = log_blk;

4067 delay_write->pageoff = end_page;

4068 }

4069 }

4070

4071 scsi_set_resid(srb, 0);

4072

4073 return STATUS_SUCCESS;

4074 }

4075

4076 int ms_rw(struct scsi_cmnd *srb, struct rts51x_chip *chip, u32 start_sector,

4077 u16 sector_cnt)

4078 {

4079 struct ms_info *ms_card = &(chip->ms_card);

4080 int retval;

4081

4082 if (CHK_MSPRO(ms_card))

4083 retval =

4084 mspro_rw_multi_sector(srb, chip, start_sector, sector_cnt);

4085 else

4086 retval =

4087 ms_rw_multi_sector(srb, chip, start_sector, sector_cnt);

4088

4089 return retval;

4090 }

4091

4092 void ms_free_l2p_tbl(struct rts51x_chip *chip)

4093 {

4094 struct ms_info *ms_card = &(chip->ms_card);

4095 int i = 0;

4096

4097 if (ms_card->segment != NULL) {

4098 for (i = 0; i < ms_card->segment_cnt; i++) {

4099 if (ms_card->segment[i].l2p_table != NULL) {

4100 vfree(ms_card->segment[i].l2p_table);

4101 ms_card->segment[i].l2p_table = NULL;

4102 }

4103 if (ms_card->segment[i].free_table != NULL) {

4104 vfree(ms_card->segment[i].free_table);

4105 ms_card->segment[i].free_table = NULL;

4106 }

4107 }

4108 vfree(ms_card->segment);

4109 ms_card->segment = NULL;

4110 }

4111 }

4112

4113 void ms_cleanup_work(struct rts51x_chip *chip)

4114 {

4115 struct ms_info *ms_card = &(chip->ms_card);

4116

4117 if (CHK_MSPRO(ms_card)) {

4118 if (ms_card->seq_mode) {

4119 RTS51X_DEBUGP("MS Pro: stop transmission\n");

4120 mspro_stop_seq_mode(chip);

4121 ms_card->counter = 0;

4122 }

4123 if (CHK_MSHG(ms_card)) {

4124 u8 value;

4125 rts51x_read_register(chip, MS_CFG, &value);

4126 if (value & MS_2K_SECTOR_MODE)

4127 rts51x_write_register(chip, MS_CFG,

4128 MS_2K_SECTOR_MODE, 0x00);

4129 }

4130 } else if ((!CHK_MSPRO(ms_card))

4131 && ms_card->delay_write.delay_write_flag) {

4132 RTS51X_DEBUGP("MS: delay write\n");

4133 ms_delay_write(chip);

4134 ms_card->counter = 0;

4135 }

4136 }

4137

4138 static int ms_power_off_card3v3(struct rts51x_chip *chip)

4139 {

4140 int retval;

4141

4142 rts51x_init_cmd(chip);

4143

4144 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_CLK_EN, MS_CLK_EN, 0);

4145 if (chip->asic_code)

4146 ms_pull_ctl_disable(chip);

4147 else

4148 rts51x_add_cmd(chip, WRITE_REG_CMD, FPGA_PULL_CTL,

4149 FPGA_MS_PULL_CTL_BIT | 0x20,

4150 FPGA_MS_PULL_CTL_BIT);

4151 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_OE, MS_OUTPUT_EN, 0);

4152 if (!chip->option.FT2_fast_mode) {

4153 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PWR_CTL, POWER_MASK,

4154 POWER_OFF);

4155 }

4156

4157 retval = rts51x_send_cmd(chip, MODE_C, 100);

4158 if (retval != STATUS_SUCCESS)

4159 TRACE_RET(chip, retval);

4160

4161 return STATUS_SUCCESS;

4162 }

4163

4164 int release_ms_card(struct rts51x_chip *chip)

4165 {

4166 struct ms_info *ms_card = &(chip->ms_card);

4167 int retval;

4168

4169 RTS51X_DEBUGP("release_ms_card\n");

4170

4171 ms_card->delay_write.delay_write_flag = 0;

4172 ms_card->pro_under_formatting = 0;

4173

4174 chip->card_ready &= ~MS_CARD;

4175 chip->card_fail &= ~MS_CARD;

4176 chip->card_wp &= ~MS_CARD;

4177

4178 ms_free_l2p_tbl(chip);

4179

4180 rts51x_write_register(chip, SFSM_ED, HW_CMD_STOP, HW_CMD_STOP);

4181

4182 memset(ms_card->raw_sys_info, 0, 96);

4183 #ifdef SUPPORT_PCGL_1P18

4184 memset(ms_card->raw_model_name, 0, 48);

4185 #endif

4186

4187 retval = ms_power_off_card3v3(chip);

4188 if (retval != STATUS_SUCCESS)

4189 TRACE_RET(chip, retval);

4190

4191 return STATUS_SUCCESS;

4192 }