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1 /*

3 *

4 * Permission is hereby granted, free of charge, to any person obtaining a

5 * copy of this software and associated documentation files (the "Software"),

6 * to deal in the Software without restriction, including without limitation

7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

8 * and/or sell copies of the Software, and to permit persons to whom the

9 * Software is furnished to do so, subject to the following conditions:

10 *

11 * The above copyright notice and this permission notice (including the next

12 * paragraph) shall be included in all copies or substantial portions of the

13 * Software.

14 *

15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL

18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING

20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS

21 * IN THE SOFTWARE.

22 *

23 * Authors:

24 * Eugeni Dodonov <eugeni.dodonov@intel.com>

25 * Daniel Vetter <daniel.vetter@ffwll.ch>

26 *

27 */

29 #include <linux/pm_runtime.h>

30 #include <linux/vgaarb.h>

32 #include "i915_drv.h"

33 #include "intel_drv.h"

35 /**

36 * DOC: runtime pm

37 *

38 * The i915 driver supports dynamic enabling and disabling of entire hardware

39 * blocks at runtime. This is especially important on the display side where

40 * software is supposed to control many power gates manually on recent hardware,

41 * since on the GT side a lot of the power management is done by the hardware.

42 * But even there some manual control at the device level is required.

43 *

44 * Since i915 supports a diverse set of platforms with a unified codebase and

45 * hardware engineers just love to shuffle functionality around between power

46 * domains there's a sizeable amount of indirection required. This file provides

47 * generic functions to the driver for grabbing and releasing references for

48 * abstract power domains. It then maps those to the actual power wells

49 * present for a given platform.

50 */

52 #define GEN9_ENABLE_DC5(dev) 0

53 #define SKL_ENABLE_DC6(dev) IS_SKYLAKE(dev)

55 #define for_each_power_well(i, power_well, domain_mask, power_domains) \

56 for (i = 0; \

57 i < (power_domains)->power_well_count && \

58 ((power_well) = &(power_domains)->power_wells[i]); \

59 i++) \

60 if ((power_well)->domains & (domain_mask))

62 #define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \

63 for (i = (power_domains)->power_well_count - 1; \

64 i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\

65 i--) \

66 if ((power_well)->domains & (domain_mask))

68 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,

69 int power_well_id);

71 static void intel_power_well_enable(struct drm_i915_private *dev_priv,

72 struct i915_power_well *power_well)

73 {

74 DRM_DEBUG_KMS("enabling %s\n", power_well->name);

75 power_well->ops->enable(dev_priv, power_well);

76 power_well->hw_enabled = true;

77 }

79 static void intel_power_well_disable(struct drm_i915_private *dev_priv,

80 struct i915_power_well *power_well)

81 {

82 DRM_DEBUG_KMS("disabling %s\n", power_well->name);

83 power_well->hw_enabled = false;

84 power_well->ops->disable(dev_priv, power_well);

85 }

87 /*

88 * We should only use the power well if we explicitly asked the hardware to

89 * enable it, so check if it's enabled and also check if we've requested it to

90 * be enabled.

91 */

92 static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,

93 struct i915_power_well *power_well)

94 {

95 return I915_READ(HSW_PWR_WELL_DRIVER) ==

96 (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);

97 }

99 /**

100 * __intel_display_power_is_enabled - unlocked check for a power domain

101 * @dev_priv: i915 device instance

102 * @domain: power domain to check

103 *

104 * This is the unlocked version of intel_display_power_is_enabled() and should

105 * only be used from error capture and recovery code where deadlocks are

106 * possible.

107 *

108 * Returns:

109 * True when the power domain is enabled, false otherwise.

110 */

111 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,

112 enum intel_display_power_domain domain)

113 {

114 struct i915_power_domains *power_domains;

115 struct i915_power_well *power_well;

116 bool is_enabled;

117 int i;

118

119 if (dev_priv->pm.suspended)

120 return false;

121

122 power_domains = &dev_priv->power_domains;

123

124 is_enabled = true;

125

126 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {

127 if (power_well->always_on)

128 continue;

129

130 if (!power_well->hw_enabled) {

131 is_enabled = false;

132 break;

133 }

134 }

135

136 return is_enabled;

137 }

138

139 /**

140 * intel_display_power_is_enabled - check for a power domain

141 * @dev_priv: i915 device instance

142 * @domain: power domain to check

143 *

144 * This function can be used to check the hw power domain state. It is mostly

145 * used in hardware state readout functions. Everywhere else code should rely

146 * upon explicit power domain reference counting to ensure that the hardware

147 * block is powered up before accessing it.

148 *

149 * Callers must hold the relevant modesetting locks to ensure that concurrent

150 * threads can't disable the power well while the caller tries to read a few

151 * registers.

152 *

153 * Returns:

154 * True when the power domain is enabled, false otherwise.

155 */

156 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,

157 enum intel_display_power_domain domain)

158 {

159 struct i915_power_domains *power_domains;

160 bool ret;

161

162 power_domains = &dev_priv->power_domains;

163

164 mutex_lock(&power_domains->lock);

165 ret = __intel_display_power_is_enabled(dev_priv, domain);

166 mutex_unlock(&power_domains->lock);

167

168 return ret;

169 }

170

171 /**

172 * intel_display_set_init_power - set the initial power domain state

173 * @dev_priv: i915 device instance

174 * @enable: whether to enable or disable the initial power domain state

175 *

176 * For simplicity our driver load/unload and system suspend/resume code assumes

177 * that all power domains are always enabled. This functions controls the state

178 * of this little hack. While the initial power domain state is enabled runtime

179 * pm is effectively disabled.

180 */

181 void intel_display_set_init_power(struct drm_i915_private *dev_priv,

182 bool enable)

183 {

184 if (dev_priv->power_domains.init_power_on == enable)

185 return;

186

187 if (enable)

188 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);

189 else

190 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);

191

192 dev_priv->power_domains.init_power_on = enable;

193 }

194

195 /*

196 * Starting with Haswell, we have a "Power Down Well" that can be turned off

197 * when not needed anymore. We have 4 registers that can request the power well

198 * to be enabled, and it will only be disabled if none of the registers is

199 * requesting it to be enabled.

200 */

201 static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)

202 {

203 struct drm_device *dev = dev_priv->dev;

204

205 /*

206 * After we re-enable the power well, if we touch VGA register 0x3d5

207 * we'll get unclaimed register interrupts. This stops after we write

208 * anything to the VGA MSR register. The vgacon module uses this

209 * register all the time, so if we unbind our driver and, as a

210 * consequence, bind vgacon, we'll get stuck in an infinite loop at

211 * console_unlock(). So make here we touch the VGA MSR register, making

212 * sure vgacon can keep working normally without triggering interrupts

213 * and error messages.

214 */

215 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);

216 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);

217 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);

218

219 if (IS_BROADWELL(dev))

220 gen8_irq_power_well_post_enable(dev_priv,

221 1 << PIPE_C | 1 << PIPE_B);

222 }

223

224 static void skl_power_well_post_enable(struct drm_i915_private *dev_priv,

225 struct i915_power_well *power_well)

226 {

227 struct drm_device *dev = dev_priv->dev;

228

229 /*

230 * After we re-enable the power well, if we touch VGA register 0x3d5

231 * we'll get unclaimed register interrupts. This stops after we write

232 * anything to the VGA MSR register. The vgacon module uses this

233 * register all the time, so if we unbind our driver and, as a

234 * consequence, bind vgacon, we'll get stuck in an infinite loop at

235 * console_unlock(). So make here we touch the VGA MSR register, making

236 * sure vgacon can keep working normally without triggering interrupts

237 * and error messages.

238 */

239 if (power_well->data == SKL_DISP_PW_2) {

240 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);

241 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);

242 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);

243

244 gen8_irq_power_well_post_enable(dev_priv,

245 1 << PIPE_C | 1 << PIPE_B);

246 }

247

248 if (power_well->data == SKL_DISP_PW_1) {

249 intel_prepare_ddi(dev);

250 gen8_irq_power_well_post_enable(dev_priv, 1 << PIPE_A);

251 }

252 }

253

254 static void hsw_set_power_well(struct drm_i915_private *dev_priv,

255 struct i915_power_well *power_well, bool enable)

256 {

257 bool is_enabled, enable_requested;

258 uint32_t tmp;

259

260 tmp = I915_READ(HSW_PWR_WELL_DRIVER);

261 is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;

262 enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;

263

264 if (enable) {

265 if (!enable_requested)

266 I915_WRITE(HSW_PWR_WELL_DRIVER,

267 HSW_PWR_WELL_ENABLE_REQUEST);

268

269 if (!is_enabled) {

270 DRM_DEBUG_KMS("Enabling power well\n");

271 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &

272 HSW_PWR_WELL_STATE_ENABLED), 20))

273 DRM_ERROR("Timeout enabling power well\n");

274 hsw_power_well_post_enable(dev_priv);

275 }

276

277 } else {

278 if (enable_requested) {

279 I915_WRITE(HSW_PWR_WELL_DRIVER, 0);

280 POSTING_READ(HSW_PWR_WELL_DRIVER);

281 DRM_DEBUG_KMS("Requesting to disable the power well\n");

282 }

283 }

284 }

285

286 #define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \

287 BIT(POWER_DOMAIN_TRANSCODER_A) | \

288 BIT(POWER_DOMAIN_PIPE_B) | \

289 BIT(POWER_DOMAIN_TRANSCODER_B) | \

290 BIT(POWER_DOMAIN_PIPE_C) | \

291 BIT(POWER_DOMAIN_TRANSCODER_C) | \

292 BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \

293 BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \

294 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \

295 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \

296 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \

297 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \

298 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \

299 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \

300 BIT(POWER_DOMAIN_PORT_DDI_E_2_LANES) | \

301 BIT(POWER_DOMAIN_AUX_B) | \

302 BIT(POWER_DOMAIN_AUX_C) | \

303 BIT(POWER_DOMAIN_AUX_D) | \

304 BIT(POWER_DOMAIN_AUDIO) | \

305 BIT(POWER_DOMAIN_VGA) | \

306 BIT(POWER_DOMAIN_INIT))

307 #define SKL_DISPLAY_DDI_A_E_POWER_DOMAINS ( \

308 BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \

309 BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \

310 BIT(POWER_DOMAIN_PORT_DDI_E_2_LANES) | \

311 BIT(POWER_DOMAIN_INIT))

312 #define SKL_DISPLAY_DDI_B_POWER_DOMAINS ( \

313 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \

314 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \

315 BIT(POWER_DOMAIN_INIT))

316 #define SKL_DISPLAY_DDI_C_POWER_DOMAINS ( \

317 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \

318 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \

319 BIT(POWER_DOMAIN_INIT))

320 #define SKL_DISPLAY_DDI_D_POWER_DOMAINS ( \

321 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \

322 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \

323 BIT(POWER_DOMAIN_INIT))

324 #define SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS ( \

325 (POWER_DOMAIN_MASK & ~( \

326 SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \

327 SKL_DISPLAY_DDI_A_E_POWER_DOMAINS | \

328 SKL_DISPLAY_DDI_B_POWER_DOMAINS | \

329 SKL_DISPLAY_DDI_C_POWER_DOMAINS | \

330 SKL_DISPLAY_DDI_D_POWER_DOMAINS)) | \

331 BIT(POWER_DOMAIN_INIT))

332

333 #define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \

334 BIT(POWER_DOMAIN_TRANSCODER_A) | \

335 BIT(POWER_DOMAIN_PIPE_B) | \

336 BIT(POWER_DOMAIN_TRANSCODER_B) | \

337 BIT(POWER_DOMAIN_PIPE_C) | \

338 BIT(POWER_DOMAIN_TRANSCODER_C) | \

339 BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \

340 BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \

341 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \

342 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \

343 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \

344 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \

345 BIT(POWER_DOMAIN_AUX_B) | \

346 BIT(POWER_DOMAIN_AUX_C) | \

347 BIT(POWER_DOMAIN_AUDIO) | \

348 BIT(POWER_DOMAIN_VGA) | \

349 BIT(POWER_DOMAIN_INIT))

350 #define BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS ( \

351 BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS | \

352 BIT(POWER_DOMAIN_PIPE_A) | \

353 BIT(POWER_DOMAIN_TRANSCODER_EDP) | \

354 BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \

355 BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \

356 BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \

357 BIT(POWER_DOMAIN_AUX_A) | \

358 BIT(POWER_DOMAIN_PLLS) | \

359 BIT(POWER_DOMAIN_INIT))

360 #define BXT_DISPLAY_ALWAYS_ON_POWER_DOMAINS ( \

361 (POWER_DOMAIN_MASK & ~(BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS | \

362 BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS)) | \

363 BIT(POWER_DOMAIN_INIT))

364

365 static void assert_can_enable_dc9(struct drm_i915_private *dev_priv)

366 {

367 struct drm_device *dev = dev_priv->dev;

368

369 WARN(!IS_BROXTON(dev), "Platform doesn't support DC9.\n");

370 WARN((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9),

371 "DC9 already programmed to be enabled.\n");

372 WARN(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,

373 "DC5 still not disabled to enable DC9.\n");

374 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on.\n");

375 WARN(intel_irqs_enabled(dev_priv), "Interrupts not disabled yet.\n");

376

377 /*

378 * TODO: check for the following to verify the conditions to enter DC9

379 * state are satisfied:

380 * 1] Check relevant display engine registers to verify if mode set

381 * disable sequence was followed.

382 * 2] Check if display uninitialize sequence is initialized.

383 */

384 }

385

386 static void assert_can_disable_dc9(struct drm_i915_private *dev_priv)

387 {

388 WARN(intel_irqs_enabled(dev_priv), "Interrupts not disabled yet.\n");

389 WARN(!(I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9),

390 "DC9 already programmed to be disabled.\n");

391 WARN(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,

392 "DC5 still not disabled.\n");

393

394 /*

395 * TODO: check for the following to verify DC9 state was indeed

396 * entered before programming to disable it:

397 * 1] Check relevant display engine registers to verify if mode

398 * set disable sequence was followed.

399 * 2] Check if display uninitialize sequence is initialized.

400 */

401 }

402

403 static void gen9_set_dc_state(struct drm_i915_private *dev_priv, uint32_t state)

404 {

405 uint32_t val;

406 uint32_t mask;

407

408 mask = DC_STATE_EN_UPTO_DC5;

409 if (IS_BROXTON(dev_priv))

410 mask |= DC_STATE_EN_DC9;

411 else

412 mask |= DC_STATE_EN_UPTO_DC6;

413

414 WARN_ON_ONCE(state & ~mask);

415

416 val = I915_READ(DC_STATE_EN);

417 DRM_DEBUG_KMS("Setting DC state from %02x to %02x\n",

418 val & mask, state);

419 val &= ~mask;

420 val |= state;

421 I915_WRITE(DC_STATE_EN, val);

422 POSTING_READ(DC_STATE_EN);

423 }

424

425 void bxt_enable_dc9(struct drm_i915_private *dev_priv)

426 {

427 assert_can_enable_dc9(dev_priv);

428

429 DRM_DEBUG_KMS("Enabling DC9\n");

430

431 gen9_set_dc_state(dev_priv, DC_STATE_EN_DC9);

432 }

433

434 void bxt_disable_dc9(struct drm_i915_private *dev_priv)

435 {

436 assert_can_disable_dc9(dev_priv);

437

438 DRM_DEBUG_KMS("Disabling DC9\n");

439

440 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);

441 }

442

443 static void gen9_set_dc_state_debugmask_memory_up(

444 struct drm_i915_private *dev_priv)

445 {

446 uint32_t val;

447

448 /* The below bit doesn't need to be cleared ever afterwards */

449 val = I915_READ(DC_STATE_DEBUG);

450 if (!(val & DC_STATE_DEBUG_MASK_MEMORY_UP)) {

451 val |= DC_STATE_DEBUG_MASK_MEMORY_UP;

452 I915_WRITE(DC_STATE_DEBUG, val);

453 POSTING_READ(DC_STATE_DEBUG);

454 }

455 }

456

457 static void assert_csr_loaded(struct drm_i915_private *dev_priv)

458 {

459 WARN_ONCE(!I915_READ(CSR_PROGRAM(0)),

460 "CSR program storage start is NULL\n");

461 WARN_ONCE(!I915_READ(CSR_SSP_BASE), "CSR SSP Base Not fine\n");

462 WARN_ONCE(!I915_READ(CSR_HTP_SKL), "CSR HTP Not fine\n");

463 }

464

465 static void assert_can_enable_dc5(struct drm_i915_private *dev_priv)

466 {

467 struct drm_device *dev = dev_priv->dev;

468 bool pg2_enabled = intel_display_power_well_is_enabled(dev_priv,

469 SKL_DISP_PW_2);

470

471 WARN_ONCE(!IS_SKYLAKE(dev), "Platform doesn't support DC5.\n");

472 WARN_ONCE(!HAS_RUNTIME_PM(dev), "Runtime PM not enabled.\n");

473 WARN_ONCE(pg2_enabled, "PG2 not disabled to enable DC5.\n");

474

475 WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5),

476 "DC5 already programmed to be enabled.\n");

477 WARN_ONCE(dev_priv->pm.suspended,

478 "DC5 cannot be enabled, if platform is runtime-suspended.\n");

479

480 assert_csr_loaded(dev_priv);

481 }

482

483 static void assert_can_disable_dc5(struct drm_i915_private *dev_priv)

484 {

485 bool pg2_enabled = intel_display_power_well_is_enabled(dev_priv,

486 SKL_DISP_PW_2);

487 /*

488 * During initialization, the firmware may not be loaded yet.

489 * We still want to make sure that the DC enabling flag is cleared.

490 */

491 if (dev_priv->power_domains.initializing)

492 return;

493

494 WARN_ONCE(!pg2_enabled, "PG2 not enabled to disable DC5.\n");

495 WARN_ONCE(dev_priv->pm.suspended,

496 "Disabling of DC5 while platform is runtime-suspended should never happen.\n");

497 }

498

499 static void gen9_enable_dc5(struct drm_i915_private *dev_priv)

500 {

501 assert_can_enable_dc5(dev_priv);

502

503 DRM_DEBUG_KMS("Enabling DC5\n");

504

505 gen9_set_dc_state_debugmask_memory_up(dev_priv);

506

507 gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5);

508 }

509

510 static void gen9_disable_dc5(struct drm_i915_private *dev_priv)

511 {

512 assert_can_disable_dc5(dev_priv);

513

514 DRM_DEBUG_KMS("Disabling DC5\n");

515

516 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);

517 }

518

519 static void assert_can_enable_dc6(struct drm_i915_private *dev_priv)

520 {

521 struct drm_device *dev = dev_priv->dev;

522

523 WARN_ONCE(!IS_SKYLAKE(dev), "Platform doesn't support DC6.\n");

524 WARN_ONCE(!HAS_RUNTIME_PM(dev), "Runtime PM not enabled.\n");

525 WARN_ONCE(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,

526 "Backlight is not disabled.\n");

527 WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC6),

528 "DC6 already programmed to be enabled.\n");

529

530 assert_csr_loaded(dev_priv);

531 }

532

533 static void assert_can_disable_dc6(struct drm_i915_private *dev_priv)

534 {

535 /*

536 * During initialization, the firmware may not be loaded yet.

537 * We still want to make sure that the DC enabling flag is cleared.

538 */

539 if (dev_priv->power_domains.initializing)

540 return;

541

542 WARN_ONCE(!(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC6),

543 "DC6 already programmed to be disabled.\n");

544 }

545

546 void skl_enable_dc6(struct drm_i915_private *dev_priv)

547 {

548 assert_can_enable_dc6(dev_priv);

549

550 DRM_DEBUG_KMS("Enabling DC6\n");

551

552 gen9_set_dc_state_debugmask_memory_up(dev_priv);

553

554 gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6);

555

556 }

557

558 void skl_disable_dc6(struct drm_i915_private *dev_priv)

559 {

560 assert_can_disable_dc6(dev_priv);

561

562 DRM_DEBUG_KMS("Disabling DC6\n");

563

564 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);

565 }

566

567 static void skl_set_power_well(struct drm_i915_private *dev_priv,

568 struct i915_power_well *power_well, bool enable)

569 {

570 struct drm_device *dev = dev_priv->dev;

571 uint32_t tmp, fuse_status;

572 uint32_t req_mask, state_mask;

573 bool is_enabled, enable_requested, check_fuse_status = false;

574

575 tmp = I915_READ(HSW_PWR_WELL_DRIVER);

576 fuse_status = I915_READ(SKL_FUSE_STATUS);

577

578 switch (power_well->data) {

579 case SKL_DISP_PW_1:

580 if (wait_for((I915_READ(SKL_FUSE_STATUS) &

581 SKL_FUSE_PG0_DIST_STATUS), 1)) {

582 DRM_ERROR("PG0 not enabled\n");

583 return;

584 }

585 break;

586 case SKL_DISP_PW_2:

587 if (!(fuse_status & SKL_FUSE_PG1_DIST_STATUS)) {

588 DRM_ERROR("PG1 in disabled state\n");

589 return;

590 }

591 break;

592 case SKL_DISP_PW_DDI_A_E:

593 case SKL_DISP_PW_DDI_B:

594 case SKL_DISP_PW_DDI_C:

595 case SKL_DISP_PW_DDI_D:

596 case SKL_DISP_PW_MISC_IO:

597 break;

598 default:

599 WARN(1, "Unknown power well %lu\n", power_well->data);

600 return;

601 }

602

603 req_mask = SKL_POWER_WELL_REQ(power_well->data);

604 enable_requested = tmp & req_mask;

605 state_mask = SKL_POWER_WELL_STATE(power_well->data);

606 is_enabled = tmp & state_mask;

607

608 if (enable) {

609 if (!enable_requested) {

610 WARN((tmp & state_mask) &&

611 !I915_READ(HSW_PWR_WELL_BIOS),

612 "Invalid for power well status to be enabled, unless done by the BIOS, \

613 when request is to disable!\n");

614 if (power_well->data == SKL_DISP_PW_2) {

615 if (GEN9_ENABLE_DC5(dev))

616 gen9_disable_dc5(dev_priv);

617 if (SKL_ENABLE_DC6(dev)) {

618 /*

619 * DDI buffer programming unnecessary during driver-load/resume

620 * as it's already done during modeset initialization then.

621 * It's also invalid here as encoder list is still uninitialized.

622 */

623 if (!dev_priv->power_domains.initializing)

624 intel_prepare_ddi(dev);

625 }

626 }

627 I915_WRITE(HSW_PWR_WELL_DRIVER, tmp | req_mask);

628 }

629

630 if (!is_enabled) {

631 DRM_DEBUG_KMS("Enabling %s\n", power_well->name);

632 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &

633 state_mask), 1))

634 DRM_ERROR("%s enable timeout\n",

635 power_well->name);

636 check_fuse_status = true;

637 }

638 } else {

639 if (enable_requested) {

640 I915_WRITE(HSW_PWR_WELL_DRIVER, tmp & ~req_mask);

641 POSTING_READ(HSW_PWR_WELL_DRIVER);

642 DRM_DEBUG_KMS("Disabling %s\n", power_well->name);

643

644 if (GEN9_ENABLE_DC5(dev) &&

645 power_well->data == SKL_DISP_PW_2)

646 gen9_enable_dc5(dev_priv);

647 }

648 }

649

650 if (check_fuse_status) {

651 if (power_well->data == SKL_DISP_PW_1) {

652 if (wait_for((I915_READ(SKL_FUSE_STATUS) &

653 SKL_FUSE_PG1_DIST_STATUS), 1))

654 DRM_ERROR("PG1 distributing status timeout\n");

655 } else if (power_well->data == SKL_DISP_PW_2) {

656 if (wait_for((I915_READ(SKL_FUSE_STATUS) &

657 SKL_FUSE_PG2_DIST_STATUS), 1))

658 DRM_ERROR("PG2 distributing status timeout\n");

659 }

660 }

661

662 if (enable && !is_enabled)

663 skl_power_well_post_enable(dev_priv, power_well);

664 }

665

666 static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,

667 struct i915_power_well *power_well)

668 {

669 hsw_set_power_well(dev_priv, power_well, power_well->count > 0);

670

671 /*

672 * We're taking over the BIOS, so clear any requests made by it since

673 * the driver is in charge now.

674 */

675 if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)

676 I915_WRITE(HSW_PWR_WELL_BIOS, 0);

677 }

678

679 static void hsw_power_well_enable(struct drm_i915_private *dev_priv,

680 struct i915_power_well *power_well)

681 {

682 hsw_set_power_well(dev_priv, power_well, true);

683 }

684

685 static void hsw_power_well_disable(struct drm_i915_private *dev_priv,

686 struct i915_power_well *power_well)

687 {

688 hsw_set_power_well(dev_priv, power_well, false);

689 }

690

691 static bool skl_power_well_enabled(struct drm_i915_private *dev_priv,

692 struct i915_power_well *power_well)

693 {

694 uint32_t mask = SKL_POWER_WELL_REQ(power_well->data) |

695 SKL_POWER_WELL_STATE(power_well->data);

696

697 return (I915_READ(HSW_PWR_WELL_DRIVER) & mask) == mask;

698 }

699

700 static void skl_power_well_sync_hw(struct drm_i915_private *dev_priv,

701 struct i915_power_well *power_well)

702 {

703 skl_set_power_well(dev_priv, power_well, power_well->count > 0);

704

705 /* Clear any request made by BIOS as driver is taking over */

706 I915_WRITE(HSW_PWR_WELL_BIOS, 0);

707 }

708

709 static void skl_power_well_enable(struct drm_i915_private *dev_priv,

710 struct i915_power_well *power_well)

711 {

712 skl_set_power_well(dev_priv, power_well, true);

713 }

714

715 static void skl_power_well_disable(struct drm_i915_private *dev_priv,

716 struct i915_power_well *power_well)

717 {

718 skl_set_power_well(dev_priv, power_well, false);

719 }

720

721 static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv,

722 struct i915_power_well *power_well)

723 {

724 }

725

726 static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv,

727 struct i915_power_well *power_well)

728 {

729 return true;

730 }

731

732 static void vlv_set_power_well(struct drm_i915_private *dev_priv,

733 struct i915_power_well *power_well, bool enable)

734 {

735 enum punit_power_well power_well_id = power_well->data;

736 u32 mask;

737 u32 state;

738 u32 ctrl;

739

740 mask = PUNIT_PWRGT_MASK(power_well_id);

741 state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) :

742 PUNIT_PWRGT_PWR_GATE(power_well_id);

743

744 mutex_lock(&dev_priv->rps.hw_lock);

745

746 #define COND \

747 ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state)

748

749 if (COND)

750 goto out;

751

752 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL);

753 ctrl &= ~mask;

754 ctrl |= state;

755 vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl);

756

757 if (wait_for(COND, 100))

758 DRM_ERROR("timeout setting power well state %08x (%08x)\n",

759 state,

760 vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL));

761

762 #undef COND

763

764 out:

765 mutex_unlock(&dev_priv->rps.hw_lock);

766 }

767

768 static void vlv_power_well_sync_hw(struct drm_i915_private *dev_priv,

769 struct i915_power_well *power_well)

770 {

771 vlv_set_power_well(dev_priv, power_well, power_well->count > 0);

772 }

773

774 static void vlv_power_well_enable(struct drm_i915_private *dev_priv,

775 struct i915_power_well *power_well)

776 {

777 vlv_set_power_well(dev_priv, power_well, true);

778 }

779

780 static void vlv_power_well_disable(struct drm_i915_private *dev_priv,

781 struct i915_power_well *power_well)

782 {

783 vlv_set_power_well(dev_priv, power_well, false);

784 }

785

786 static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,

787 struct i915_power_well *power_well)

788 {

789 int power_well_id = power_well->data;

790 bool enabled = false;

791 u32 mask;

792 u32 state;

793 u32 ctrl;

794

795 mask = PUNIT_PWRGT_MASK(power_well_id);

796 ctrl = PUNIT_PWRGT_PWR_ON(power_well_id);

797

798 mutex_lock(&dev_priv->rps.hw_lock);

799

800 state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask;

801 /*

802 * We only ever set the power-on and power-gate states, anything

803 * else is unexpected.

804 */

805 WARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) &&

806 state != PUNIT_PWRGT_PWR_GATE(power_well_id));

807 if (state == ctrl)

808 enabled = true;

809

810 /*

811 * A transient state at this point would mean some unexpected party

812 * is poking at the power controls too.

813 */

814 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask;

815 WARN_ON(ctrl != state);

816

817 mutex_unlock(&dev_priv->rps.hw_lock);

818

819 return enabled;

820 }

821

822 static void vlv_display_power_well_init(struct drm_i915_private *dev_priv)

823 {

824 enum pipe pipe;

825

826 /*

827 * Enable the CRI clock source so we can get at the

828 * display and the reference clock for VGA

829 * hotplug / manual detection. Supposedly DSI also

830 * needs the ref clock up and running.

831 *

832 * CHV DPLL B/C have some issues if VGA mode is enabled.

833 */

834 for_each_pipe(dev_priv->dev, pipe) {

835 u32 val = I915_READ(DPLL(pipe));

836

837 val |= DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;

838 if (pipe != PIPE_A)

839 val |= DPLL_INTEGRATED_CRI_CLK_VLV;

840

841 I915_WRITE(DPLL(pipe), val);

842 }

843

844 spin_lock_irq(&dev_priv->irq_lock);

845 valleyview_enable_display_irqs(dev_priv);

846 spin_unlock_irq(&dev_priv->irq_lock);

847

848 /*

849 * During driver initialization/resume we can avoid restoring the

850 * part of the HW/SW state that will be inited anyway explicitly.

851 */

852 if (dev_priv->power_domains.initializing)

853 return;

854

855 intel_hpd_init(dev_priv);

856

857 i915_redisable_vga_power_on(dev_priv->dev);

858 }

859

860 static void vlv_display_power_well_deinit(struct drm_i915_private *dev_priv)

861 {

862 spin_lock_irq(&dev_priv->irq_lock);

863 valleyview_disable_display_irqs(dev_priv);

864 spin_unlock_irq(&dev_priv->irq_lock);

865

866 vlv_power_sequencer_reset(dev_priv);

867 }

868

869 static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv,

870 struct i915_power_well *power_well)

871 {

872 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);

873

874 vlv_set_power_well(dev_priv, power_well, true);

875

876 vlv_display_power_well_init(dev_priv);

877 }

878

879 static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv,

880 struct i915_power_well *power_well)

881 {

882 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);

883

884 vlv_display_power_well_deinit(dev_priv);

885

886 vlv_set_power_well(dev_priv, power_well, false);

887 }

888

889 static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,

890 struct i915_power_well *power_well)

891 {

892 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);

893

894 /* since ref/cri clock was enabled */

895 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */

896

897 vlv_set_power_well(dev_priv, power_well, true);

898

899 /*

900 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -

901 * 6. De-assert cmn_reset/side_reset. Same as VLV X0.

902 * a. GUnit 0x2110 bit[0] set to 1 (def 0)

903 * b. The other bits such as sfr settings / modesel may all

904 * be set to 0.

905 *

906 * This should only be done on init and resume from S3 with

907 * both PLLs disabled, or we risk losing DPIO and PLL

908 * synchronization.

909 */

910 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);

911 }

912

913 static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,

914 struct i915_power_well *power_well)

915 {

916 enum pipe pipe;

917

918 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);

919

920 for_each_pipe(dev_priv, pipe)

921 assert_pll_disabled(dev_priv, pipe);

922

923 /* Assert common reset */

924 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) & ~DPIO_CMNRST);

925

926 vlv_set_power_well(dev_priv, power_well, false);

927 }

928

929 #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)

930

931 static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_priv,

932 int power_well_id)

933 {

934 struct i915_power_domains *power_domains = &dev_priv->power_domains;

935 int i;

936

937 for (i = 0; i < power_domains->power_well_count; i++) {

938 struct i915_power_well *power_well;

939

940 power_well = &power_domains->power_wells[i];

941 if (power_well->data == power_well_id)

942 return power_well;

943 }

944

945 return NULL;

946 }

947

948 #define BITS_SET(val, bits) (((val) & (bits)) == (bits))

949

950 static void assert_chv_phy_status(struct drm_i915_private *dev_priv)

951 {

952 struct i915_power_well *cmn_bc =

953 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);

954 struct i915_power_well *cmn_d =

955 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D);

956 u32 phy_control = dev_priv->chv_phy_control;

957 u32 phy_status = 0;

958 u32 phy_status_mask = 0xffffffff;

959 u32 tmp;

960

961 /*

962 * The BIOS can leave the PHY is some weird state

963 * where it doesn't fully power down some parts.

964 * Disable the asserts until the PHY has been fully

965 * reset (ie. the power well has been disabled at

966 * least once).

967 */

968 if (!dev_priv->chv_phy_assert[DPIO_PHY0])

969 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0) |

970 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0) |

971 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1) |

972 PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1) |

973 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0) |

974 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1));

975

976 if (!dev_priv->chv_phy_assert[DPIO_PHY1])

977 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0) |

978 PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0) |

979 PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1));

980

981 if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) {

982 phy_status |= PHY_POWERGOOD(DPIO_PHY0);

983

984 /* this assumes override is only used to enable lanes */

985 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0)) == 0)

986 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0);

987

988 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1)) == 0)

989 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1);

990

991 /* CL1 is on whenever anything is on in either channel */

992 if (BITS_SET(phy_control,

993 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0) |

994 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)))

995 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0);

996

997 /*

998 * The DPLLB check accounts for the pipe B + port A usage

999 * with CL2 powered up but all the lanes in the second channel

1000 * powered down.

1001 */

1002 if (BITS_SET(phy_control,

1003 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)) &&

1004 (I915_READ(DPLL(PIPE_B)) & DPLL_VCO_ENABLE) == 0)

1005 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1);

1006

1007 if (BITS_SET(phy_control,

1008 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH0)))

1009 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0);

1010 if (BITS_SET(phy_control,

1011 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH0)))

1012 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1);

1013

1014 if (BITS_SET(phy_control,

1015 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH1)))

1016 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0);

1017 if (BITS_SET(phy_control,

1018 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH1)))

1019 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1);

1020 }

1021

1022 if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) {

1023 phy_status |= PHY_POWERGOOD(DPIO_PHY1);

1024

1025 /* this assumes override is only used to enable lanes */

1026 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0)) == 0)

1027 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0);

1028

1029 if (BITS_SET(phy_control,

1030 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0)))

1031 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0);

1032

1033 if (BITS_SET(phy_control,

1034 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY1, DPIO_CH0)))

1035 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0);

1036 if (BITS_SET(phy_control,

1037 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY1, DPIO_CH0)))

1038 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1);

1039 }

1040

1041 phy_status &= phy_status_mask;

1042

1043 /*

1044 * The PHY may be busy with some initial calibration and whatnot,

1045 * so the power state can take a while to actually change.

1046 */

1047 if (wait_for((tmp = I915_READ(DISPLAY_PHY_STATUS) & phy_status_mask) == phy_status, 10))

1048 WARN(phy_status != tmp,

1049 "Unexpected PHY_STATUS 0x%08x, expected 0x%08x (PHY_CONTROL=0x%08x)\n",

1050 tmp, phy_status, dev_priv->chv_phy_control);

1051 }

1052

1053 #undef BITS_SET

1054

1055 static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,

1056 struct i915_power_well *power_well)

1057 {

1058 enum dpio_phy phy;

1059 enum pipe pipe;

1060 uint32_t tmp;

1061

1062 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&

1063 power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);

1064

1065 if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {

1066 pipe = PIPE_A;

1067 phy = DPIO_PHY0;

1068 } else {

1069 pipe = PIPE_C;

1070 phy = DPIO_PHY1;

1071 }

1072

1073 /* since ref/cri clock was enabled */

1074 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */

1075 vlv_set_power_well(dev_priv, power_well, true);

1076

1077 /* Poll for phypwrgood signal */

1078 if (wait_for(I915_READ(DISPLAY_PHY_STATUS) & PHY_POWERGOOD(phy), 1))

1079 DRM_ERROR("Display PHY %d is not power up\n", phy);

1080

1081 mutex_lock(&dev_priv->sb_lock);

1082

1083 /* Enable dynamic power down */

1084 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW28);

1085 tmp |= DPIO_DYNPWRDOWNEN_CH0 | DPIO_CL1POWERDOWNEN |

1086 DPIO_SUS_CLK_CONFIG_GATE_CLKREQ;

1087 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW28, tmp);

1088

1089 if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {

1090 tmp = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW6_CH1);

1091 tmp |= DPIO_DYNPWRDOWNEN_CH1;

1092 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW6_CH1, tmp);

1093 } else {

1094 /*

1095 * Force the non-existing CL2 off. BXT does this

1096 * too, so maybe it saves some power even though

1097 * CL2 doesn't exist?

1098 */

1099 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);

1100 tmp |= DPIO_CL2_LDOFUSE_PWRENB;

1101 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, tmp);

1102 }

1103

1104 mutex_unlock(&dev_priv->sb_lock);

1105

1106 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy);

1107 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);

1108

1109 DRM_DEBUG_KMS("Enabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",

1110 phy, dev_priv->chv_phy_control);

1111

1112 assert_chv_phy_status(dev_priv);

1113 }

1114

1115 static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,

1116 struct i915_power_well *power_well)

1117 {

1118 enum dpio_phy phy;

1119

1120 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&

1121 power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);

1122

1123 if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {

1124 phy = DPIO_PHY0;

1125 assert_pll_disabled(dev_priv, PIPE_A);

1126 assert_pll_disabled(dev_priv, PIPE_B);

1127 } else {

1128 phy = DPIO_PHY1;

1129 assert_pll_disabled(dev_priv, PIPE_C);

1130 }

1131

1132 dev_priv->chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy);

1133 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);

1134

1135 vlv_set_power_well(dev_priv, power_well, false);

1136

1137 DRM_DEBUG_KMS("Disabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",

1138 phy, dev_priv->chv_phy_control);

1139

1140 /* PHY is fully reset now, so we can enable the PHY state asserts */

1141 dev_priv->chv_phy_assert[phy] = true;

1142

1143 assert_chv_phy_status(dev_priv);

1144 }

1145

1146 static void assert_chv_phy_powergate(struct drm_i915_private *dev_priv, enum dpio_phy phy,

1147 enum dpio_channel ch, bool override, unsigned int mask)

1148 {

1149 enum pipe pipe = phy == DPIO_PHY0 ? PIPE_A : PIPE_C;

1150 u32 reg, val, expected, actual;

1151

1152 /*

1153 * The BIOS can leave the PHY is some weird state

1154 * where it doesn't fully power down some parts.

1155 * Disable the asserts until the PHY has been fully

1156 * reset (ie. the power well has been disabled at

1157 * least once).

1158 */

1159 if (!dev_priv->chv_phy_assert[phy])

1160 return;

1161

1162 if (ch == DPIO_CH0)

1163 reg = _CHV_CMN_DW0_CH0;

1164 else

1165 reg = _CHV_CMN_DW6_CH1;

1166

1167 mutex_lock(&dev_priv->sb_lock);

1168 val = vlv_dpio_read(dev_priv, pipe, reg);

1169 mutex_unlock(&dev_priv->sb_lock);

1170

1171 /*

1172 * This assumes !override is only used when the port is disabled.

1173 * All lanes should power down even without the override when

1174 * the port is disabled.

1175 */

1176 if (!override || mask == 0xf) {

1177 expected = DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN;

1178 /*

1179 * If CH1 common lane is not active anymore

1180 * (eg. for pipe B DPLL) the entire channel will

1181 * shut down, which causes the common lane registers

1182 * to read as 0. That means we can't actually check

1183 * the lane power down status bits, but as the entire

1184 * register reads as 0 it's a good indication that the

1185 * channel is indeed entirely powered down.

1186 */

1187 if (ch == DPIO_CH1 && val == 0)

1188 expected = 0;

1189 } else if (mask != 0x0) {

1190 expected = DPIO_ANYDL_POWERDOWN;

1191 } else {

1192 expected = 0;

1193 }

1194

1195 if (ch == DPIO_CH0)

1196 actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH0;

1197 else

1198 actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH1;

1199 actual &= DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN;

1200

1201 WARN(actual != expected,

1202 "Unexpected DPIO lane power down: all %d, any %d. Expected: all %d, any %d. (0x%x = 0x%08x)\n",

1203 !!(actual & DPIO_ALLDL_POWERDOWN), !!(actual & DPIO_ANYDL_POWERDOWN),

1204 !!(expected & DPIO_ALLDL_POWERDOWN), !!(expected & DPIO_ANYDL_POWERDOWN),

1205 reg, val);

1206 }

1207

1208 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,

1209 enum dpio_channel ch, bool override)

1210 {

1211 struct i915_power_domains *power_domains = &dev_priv->power_domains;

1212 bool was_override;

1213

1214 mutex_lock(&power_domains->lock);

1215

1216 was_override = dev_priv->chv_phy_control & PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);

1217

1218 if (override == was_override)

1219 goto out;

1220

1221 if (override)

1222 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);

1223 else

1224 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);

1225

1226 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);

1227

1228 DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d (DPIO_PHY_CONTROL=0x%08x)\n",

1229 phy, ch, dev_priv->chv_phy_control);

1230

1231 assert_chv_phy_status(dev_priv);

1232

1233 out:

1234 mutex_unlock(&power_domains->lock);

1235

1236 return was_override;

1237 }

1238

1239 void chv_phy_powergate_lanes(struct intel_encoder *encoder,

1240 bool override, unsigned int mask)

1241 {

1242 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

1243 struct i915_power_domains *power_domains = &dev_priv->power_domains;

1244 enum dpio_phy phy = vlv_dport_to_phy(enc_to_dig_port(&encoder->base));

1245 enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base));

1246

1247 mutex_lock(&power_domains->lock);

1248

1249 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD(0xf, phy, ch);

1250 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD(mask, phy, ch);

1251

1252 if (override)

1253 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);

1254 else

1255 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);

1256

1257 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);

1258

1259 DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d lanes 0x%x (PHY_CONTROL=0x%08x)\n",

1260 phy, ch, mask, dev_priv->chv_phy_control);

1261

1262 assert_chv_phy_status(dev_priv);

1263

1264 assert_chv_phy_powergate(dev_priv, phy, ch, override, mask);

1265

1266 mutex_unlock(&power_domains->lock);

1267 }

1268

1269 static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv,

1270 struct i915_power_well *power_well)

1271 {

1272 enum pipe pipe = power_well->data;

1273 bool enabled;

1274 u32 state, ctrl;

1275

1276 mutex_lock(&dev_priv->rps.hw_lock);

1277

1278 state = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe);

1279 /*

1280 * We only ever set the power-on and power-gate states, anything

1281 * else is unexpected.

1282 */

1283 WARN_ON(state != DP_SSS_PWR_ON(pipe) && state != DP_SSS_PWR_GATE(pipe));

1284 enabled = state == DP_SSS_PWR_ON(pipe);

1285

1286 /*

1287 * A transient state at this point would mean some unexpected party

1288 * is poking at the power controls too.

1289 */

1290 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSC_MASK(pipe);

1291 WARN_ON(ctrl << 16 != state);

1292

1293 mutex_unlock(&dev_priv->rps.hw_lock);

1294

1295 return enabled;

1296 }

1297

1298 static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv,

1299 struct i915_power_well *power_well,

1300 bool enable)

1301 {

1302 enum pipe pipe = power_well->data;

1303 u32 state;

1304 u32 ctrl;

1305

1306 state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe);

1307

1308 mutex_lock(&dev_priv->rps.hw_lock);

1309

1310 #define COND \

1311 ((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe)) == state)

1312

1313 if (COND)

1314 goto out;

1315

1316 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);

1317 ctrl &= ~DP_SSC_MASK(pipe);

1318 ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe);

1319 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, ctrl);

1320

1321 if (wait_for(COND, 100))

1322 DRM_ERROR("timeout setting power well state %08x (%08x)\n",

1323 state,

1324 vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ));

1325

1326 #undef COND

1327

1328 out:

1329 mutex_unlock(&dev_priv->rps.hw_lock);

1330 }

1331

1332 static void chv_pipe_power_well_sync_hw(struct drm_i915_private *dev_priv,

1333 struct i915_power_well *power_well)

1334 {

1335 WARN_ON_ONCE(power_well->data != PIPE_A);

1336

1337 chv_set_pipe_power_well(dev_priv, power_well, power_well->count > 0);

1338 }

1339

1340 static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv,

1341 struct i915_power_well *power_well)

1342 {

1343 WARN_ON_ONCE(power_well->data != PIPE_A);

1344

1345 chv_set_pipe_power_well(dev_priv, power_well, true);

1346

1347 vlv_display_power_well_init(dev_priv);

1348 }

1349

1350 static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv,

1351 struct i915_power_well *power_well)

1352 {

1353 WARN_ON_ONCE(power_well->data != PIPE_A);

1354

1355 vlv_display_power_well_deinit(dev_priv);

1356

1357 chv_set_pipe_power_well(dev_priv, power_well, false);

1358 }

1359

1360 /**

1361 * intel_display_power_get - grab a power domain reference

1362 * @dev_priv: i915 device instance

1363 * @domain: power domain to reference

1364 *

1365 * This function grabs a power domain reference for @domain and ensures that the

1366 * power domain and all its parents are powered up. Therefore users should only

1367 * grab a reference to the innermost power domain they need.

1368 *

1369 * Any power domain reference obtained by this function must have a symmetric

1370 * call to intel_display_power_put() to release the reference again.

1371 */

1372 void intel_display_power_get(struct drm_i915_private *dev_priv,

1373 enum intel_display_power_domain domain)

1374 {

1375 struct i915_power_domains *power_domains;

1376 struct i915_power_well *power_well;

1377 int i;

1378

1379 intel_runtime_pm_get(dev_priv);

1380

1381 power_domains = &dev_priv->power_domains;

1382

1383 mutex_lock(&power_domains->lock);

1384

1385 for_each_power_well(i, power_well, BIT(domain), power_domains) {

1386 if (!power_well->count++)

1387 intel_power_well_enable(dev_priv, power_well);

1388 }

1389

1390 power_domains->domain_use_count[domain]++;

1391

1392 mutex_unlock(&power_domains->lock);

1393 }

1394

1395 /**

1396 * intel_display_power_put - release a power domain reference

1397 * @dev_priv: i915 device instance

1398 * @domain: power domain to reference

1399 *

1400 * This function drops the power domain reference obtained by

1401 * intel_display_power_get() and might power down the corresponding hardware

1402 * block right away if this is the last reference.

1403 */

1404 void intel_display_power_put(struct drm_i915_private *dev_priv,

1405 enum intel_display_power_domain domain)

1406 {

1407 struct i915_power_domains *power_domains;

1408 struct i915_power_well *power_well;

1409 int i;

1410

1411 power_domains = &dev_priv->power_domains;

1412

1413 mutex_lock(&power_domains->lock);

1414

1415 WARN_ON(!power_domains->domain_use_count[domain]);

1416 power_domains->domain_use_count[domain]--;

1417

1418 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {

1419 WARN_ON(!power_well->count);

1420

1421 if (!--power_well->count && i915.disable_power_well)

1422 intel_power_well_disable(dev_priv, power_well);

1423 }

1424

1425 mutex_unlock(&power_domains->lock);

1426

1427 intel_runtime_pm_put(dev_priv);

1428 }

1429

1430 #define HSW_ALWAYS_ON_POWER_DOMAINS ( \

1431 BIT(POWER_DOMAIN_PIPE_A) | \

1432 BIT(POWER_DOMAIN_TRANSCODER_EDP) | \

1433 BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \

1434 BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \

1435 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \

1436 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \

1437 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \

1438 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \

1439 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \

1440 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \

1441 BIT(POWER_DOMAIN_PORT_CRT) | \

1442 BIT(POWER_DOMAIN_PLLS) | \

1443 BIT(POWER_DOMAIN_AUX_A) | \

1444 BIT(POWER_DOMAIN_AUX_B) | \

1445 BIT(POWER_DOMAIN_AUX_C) | \

1446 BIT(POWER_DOMAIN_AUX_D) | \

1447 BIT(POWER_DOMAIN_INIT))

1448 #define HSW_DISPLAY_POWER_DOMAINS ( \

1449 (POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) | \

1450 BIT(POWER_DOMAIN_INIT))

1451

1452 #define BDW_ALWAYS_ON_POWER_DOMAINS ( \

1453 HSW_ALWAYS_ON_POWER_DOMAINS | \

1454 BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER))

1455 #define BDW_DISPLAY_POWER_DOMAINS ( \

1456 (POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS) | \

1457 BIT(POWER_DOMAIN_INIT))

1458

1459 #define VLV_ALWAYS_ON_POWER_DOMAINS BIT(POWER_DOMAIN_INIT)

1460 #define VLV_DISPLAY_POWER_DOMAINS POWER_DOMAIN_MASK

1461

1462 #define VLV_DPIO_CMN_BC_POWER_DOMAINS ( \

1463 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \

1464 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \

1465 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \

1466 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \

1467 BIT(POWER_DOMAIN_PORT_CRT) | \

1468 BIT(POWER_DOMAIN_AUX_B) | \

1469 BIT(POWER_DOMAIN_AUX_C) | \

1470 BIT(POWER_DOMAIN_INIT))

1471

1472 #define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \

1473 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \

1474 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \

1475 BIT(POWER_DOMAIN_AUX_B) | \

1476 BIT(POWER_DOMAIN_INIT))

1477

1478 #define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \

1479 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \

1480 BIT(POWER_DOMAIN_AUX_B) | \

1481 BIT(POWER_DOMAIN_INIT))

1482

1483 #define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \

1484 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \

1485 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \

1486 BIT(POWER_DOMAIN_AUX_C) | \

1487 BIT(POWER_DOMAIN_INIT))

1488

1489 #define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \

1490 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \

1491 BIT(POWER_DOMAIN_AUX_C) | \

1492 BIT(POWER_DOMAIN_INIT))

1493

1494 #define CHV_DPIO_CMN_BC_POWER_DOMAINS ( \

1495 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \

1496 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \

1497 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \

1498 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \

1499 BIT(POWER_DOMAIN_AUX_B) | \

1500 BIT(POWER_DOMAIN_AUX_C) | \

1501 BIT(POWER_DOMAIN_INIT))

1502

1503 #define CHV_DPIO_CMN_D_POWER_DOMAINS ( \

1504 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \

1505 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \

1506 BIT(POWER_DOMAIN_AUX_D) | \

1507 BIT(POWER_DOMAIN_INIT))

1508

1509 static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {

1510 .sync_hw = i9xx_always_on_power_well_noop,

1511 .enable = i9xx_always_on_power_well_noop,

1512 .disable = i9xx_always_on_power_well_noop,

1513 .is_enabled = i9xx_always_on_power_well_enabled,

1514 };

1515

1516 static const struct i915_power_well_ops chv_pipe_power_well_ops = {

1517 .sync_hw = chv_pipe_power_well_sync_hw,

1518 .enable = chv_pipe_power_well_enable,

1519 .disable = chv_pipe_power_well_disable,

1520 .is_enabled = chv_pipe_power_well_enabled,

1521 };

1522

1523 static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = {

1524 .sync_hw = vlv_power_well_sync_hw,

1525 .enable = chv_dpio_cmn_power_well_enable,

1526 .disable = chv_dpio_cmn_power_well_disable,

1527 .is_enabled = vlv_power_well_enabled,

1528 };

1529

1530 static struct i915_power_well i9xx_always_on_power_well[] = {

1531 {

1532 .name = "always-on",

1533 .always_on = 1,

1534 .domains = POWER_DOMAIN_MASK,

1535 .ops = &i9xx_always_on_power_well_ops,

1536 },

1537 };

1538

1539 static const struct i915_power_well_ops hsw_power_well_ops = {

1540 .sync_hw = hsw_power_well_sync_hw,

1541 .enable = hsw_power_well_enable,

1542 .disable = hsw_power_well_disable,

1543 .is_enabled = hsw_power_well_enabled,

1544 };

1545

1546 static const struct i915_power_well_ops skl_power_well_ops = {

1547 .sync_hw = skl_power_well_sync_hw,

1548 .enable = skl_power_well_enable,

1549 .disable = skl_power_well_disable,

1550 .is_enabled = skl_power_well_enabled,

1551 };

1552

1553 static struct i915_power_well hsw_power_wells[] = {

1554 {

1555 .name = "always-on",

1556 .always_on = 1,

1557 .domains = HSW_ALWAYS_ON_POWER_DOMAINS,

1558 .ops = &i9xx_always_on_power_well_ops,

1559 },

1560 {

1561 .name = "display",

1562 .domains = HSW_DISPLAY_POWER_DOMAINS,

1563 .ops = &hsw_power_well_ops,

1564 },

1565 };

1566

1567 static struct i915_power_well bdw_power_wells[] = {

1568 {

1569 .name = "always-on",

1570 .always_on = 1,

1571 .domains = BDW_ALWAYS_ON_POWER_DOMAINS,

1572 .ops = &i9xx_always_on_power_well_ops,

1573 },

1574 {

1575 .name = "display",

1576 .domains = BDW_DISPLAY_POWER_DOMAINS,

1577 .ops = &hsw_power_well_ops,

1578 },

1579 };

1580

1581 static const struct i915_power_well_ops vlv_display_power_well_ops = {

1582 .sync_hw = vlv_power_well_sync_hw,

1583 .enable = vlv_display_power_well_enable,

1584 .disable = vlv_display_power_well_disable,

1585 .is_enabled = vlv_power_well_enabled,

1586 };

1587

1588 static const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = {

1589 .sync_hw = vlv_power_well_sync_hw,

1590 .enable = vlv_dpio_cmn_power_well_enable,

1591 .disable = vlv_dpio_cmn_power_well_disable,

1592 .is_enabled = vlv_power_well_enabled,

1593 };

1594

1595 static const struct i915_power_well_ops vlv_dpio_power_well_ops = {

1596 .sync_hw = vlv_power_well_sync_hw,

1597 .enable = vlv_power_well_enable,

1598 .disable = vlv_power_well_disable,

1599 .is_enabled = vlv_power_well_enabled,

1600 };

1601

1602 static struct i915_power_well vlv_power_wells[] = {

1603 {

1604 .name = "always-on",

1605 .always_on = 1,

1606 .domains = VLV_ALWAYS_ON_POWER_DOMAINS,

1607 .ops = &i9xx_always_on_power_well_ops,

1608 .data = PUNIT_POWER_WELL_ALWAYS_ON,

1609 },

1610 {

1611 .name = "display",

1612 .domains = VLV_DISPLAY_POWER_DOMAINS,

1613 .data = PUNIT_POWER_WELL_DISP2D,

1614 .ops = &vlv_display_power_well_ops,

1615 },

1616 {

1617 .name = "dpio-tx-b-01",

1618 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |

1619 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |

1620 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |

1621 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,

1622 .ops = &vlv_dpio_power_well_ops,

1623 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01,

1624 },

1625 {

1626 .name = "dpio-tx-b-23",

1627 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |

1628 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |

1629 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |

1630 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,

1631 .ops = &vlv_dpio_power_well_ops,

1632 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23,

1633 },

1634 {

1635 .name = "dpio-tx-c-01",

1636 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |

1637 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |

1638 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |

1639 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,

1640 .ops = &vlv_dpio_power_well_ops,

1641 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01,

1642 },

1643 {

1644 .name = "dpio-tx-c-23",

1645 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |

1646 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |

1647 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |

1648 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,

1649 .ops = &vlv_dpio_power_well_ops,

1650 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,

1651 },

1652 {

1653 .name = "dpio-common",

1654 .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS,

1655 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,

1656 .ops = &vlv_dpio_cmn_power_well_ops,

1657 },

1658 };

1659

1660 static struct i915_power_well chv_power_wells[] = {

1661 {

1662 .name = "always-on",

1663 .always_on = 1,

1664 .domains = VLV_ALWAYS_ON_POWER_DOMAINS,

1665 .ops = &i9xx_always_on_power_well_ops,

1666 },

1667 {

1668 .name = "display",

1669 /*

1670 * Pipe A power well is the new disp2d well. Pipe B and C

1671 * power wells don't actually exist. Pipe A power well is

1672 * required for any pipe to work.

1673 */

1674 .domains = VLV_DISPLAY_POWER_DOMAINS,

1675 .data = PIPE_A,

1676 .ops = &chv_pipe_power_well_ops,

1677 },

1678 {

1679 .name = "dpio-common-bc",

1680 .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS,

1681 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,

1682 .ops = &chv_dpio_cmn_power_well_ops,

1683 },

1684 {

1685 .name = "dpio-common-d",

1686 .domains = CHV_DPIO_CMN_D_POWER_DOMAINS,

1687 .data = PUNIT_POWER_WELL_DPIO_CMN_D,

1688 .ops = &chv_dpio_cmn_power_well_ops,

1689 },

1690 };

1691

1692 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,

1693 int power_well_id)

1694 {

1695 struct i915_power_well *power_well;

1696 bool ret;

1697

1698 power_well = lookup_power_well(dev_priv, power_well_id);

1699 ret = power_well->ops->is_enabled(dev_priv, power_well);

1700

1701 return ret;

1702 }

1703

1704 static struct i915_power_well skl_power_wells[] = {

1705 {

1706 .name = "always-on",

1707 .always_on = 1,

1708 .domains = SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS,

1709 .ops = &i9xx_always_on_power_well_ops,

1710 .data = SKL_DISP_PW_ALWAYS_ON,

1711 },

1712 {

1713 .name = "power well 1",

1714 /* Handled by the DMC firmware */

1715 .domains = 0,

1716 .ops = &skl_power_well_ops,

1717 .data = SKL_DISP_PW_1,

1718 },

1719 {

1720 .name = "MISC IO power well",

1721 /* Handled by the DMC firmware */

1722 .domains = 0,

1723 .ops = &skl_power_well_ops,

1724 .data = SKL_DISP_PW_MISC_IO,

1725 },

1726 {

1727 .name = "power well 2",

1728 .domains = SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS,

1729 .ops = &skl_power_well_ops,

1730 .data = SKL_DISP_PW_2,

1731 },

1732 {

1733 .name = "DDI A/E power well",

1734 .domains = SKL_DISPLAY_DDI_A_E_POWER_DOMAINS,

1735 .ops = &skl_power_well_ops,

1736 .data = SKL_DISP_PW_DDI_A_E,

1737 },

1738 {

1739 .name = "DDI B power well",

1740 .domains = SKL_DISPLAY_DDI_B_POWER_DOMAINS,

1741 .ops = &skl_power_well_ops,

1742 .data = SKL_DISP_PW_DDI_B,

1743 },

1744 {

1745 .name = "DDI C power well",

1746 .domains = SKL_DISPLAY_DDI_C_POWER_DOMAINS,

1747 .ops = &skl_power_well_ops,

1748 .data = SKL_DISP_PW_DDI_C,

1749 },

1750 {

1751 .name = "DDI D power well",

1752 .domains = SKL_DISPLAY_DDI_D_POWER_DOMAINS,

1753 .ops = &skl_power_well_ops,

1754 .data = SKL_DISP_PW_DDI_D,

1755 },

1756 };

1757

1758 void skl_pw1_misc_io_init(struct drm_i915_private *dev_priv)

1759 {

1760 struct i915_power_well *well;

1761

1762 if (!IS_SKYLAKE(dev_priv))

1763 return;

1764

1765 well = lookup_power_well(dev_priv, SKL_DISP_PW_1);

1766 intel_power_well_enable(dev_priv, well);

1767

1768 well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO);

1769 intel_power_well_enable(dev_priv, well);

1770 }

1771

1772 void skl_pw1_misc_io_fini(struct drm_i915_private *dev_priv)

1773 {

1774 struct i915_power_well *well;

1775

1776 if (!IS_SKYLAKE(dev_priv))

1777 return;

1778

1779 well = lookup_power_well(dev_priv, SKL_DISP_PW_1);

1780 intel_power_well_disable(dev_priv, well);

1781

1782 well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO);

1783 intel_power_well_disable(dev_priv, well);

1784 }

1785

1786 static struct i915_power_well bxt_power_wells[] = {

1787 {

1788 .name = "always-on",

1789 .always_on = 1,

1790 .domains = BXT_DISPLAY_ALWAYS_ON_POWER_DOMAINS,

1791 .ops = &i9xx_always_on_power_well_ops,

1792 },

1793 {

1794 .name = "power well 1",

1795 .domains = BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS,

1796 .ops = &skl_power_well_ops,

1797 .data = SKL_DISP_PW_1,

1798 },

1799 {

1800 .name = "power well 2",

1801 .domains = BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS,

1802 .ops = &skl_power_well_ops,

1803 .data = SKL_DISP_PW_2,

1804 }

1805 };

1806

1807 #define set_power_wells(power_domains, __power_wells) ({ \

1808 (power_domains)->power_wells = (__power_wells); \

1809 (power_domains)->power_well_count = ARRAY_SIZE(__power_wells); \

1810 })

1811

1812 /**

1813 * intel_power_domains_init - initializes the power domain structures

1814 * @dev_priv: i915 device instance

1815 *

1816 * Initializes the power domain structures for @dev_priv depending upon the

1817 * supported platform.

1818 */

1819 int intel_power_domains_init(struct drm_i915_private *dev_priv)

1820 {

1821 struct i915_power_domains *power_domains = &dev_priv->power_domains;

1822

1823 mutex_init(&power_domains->lock);

1824

1825 /*

1826 * The enabling order will be from lower to higher indexed wells,

1827 * the disabling order is reversed.

1828 */

1829 if (IS_HASWELL(dev_priv->dev)) {

1830 set_power_wells(power_domains, hsw_power_wells);

1831 } else if (IS_BROADWELL(dev_priv->dev)) {

1832 set_power_wells(power_domains, bdw_power_wells);

1833 } else if (IS_SKYLAKE(dev_priv->dev) || IS_KABYLAKE(dev_priv->dev)) {

1834 set_power_wells(power_domains, skl_power_wells);

1835 } else if (IS_BROXTON(dev_priv->dev)) {

1836 set_power_wells(power_domains, bxt_power_wells);

1837 } else if (IS_CHERRYVIEW(dev_priv->dev)) {

1838 set_power_wells(power_domains, chv_power_wells);

1839 } else if (IS_VALLEYVIEW(dev_priv->dev)) {

1840 set_power_wells(power_domains, vlv_power_wells);

1841 } else {

1842 set_power_wells(power_domains, i9xx_always_on_power_well);

1843 }

1844

1845 return 0;

1846 }

1847

1848 /**

1849 * intel_power_domains_fini - finalizes the power domain structures

1850 * @dev_priv: i915 device instance

1851 *

1852 * Finalizes the power domain structures for @dev_priv depending upon the

1853 * supported platform. This function also disables runtime pm and ensures that

1854 * the device stays powered up so that the driver can be reloaded.

1855 */

1856 void intel_power_domains_fini(struct drm_i915_private *dev_priv)

1857 {

1858 /* The i915.ko module is still not prepared to be loaded when

1859 * the power well is not enabled, so just enable it in case

1860 * we're going to unload/reload. */

1861 intel_display_set_init_power(dev_priv, true);

1862 }

1863

1864 static void intel_power_domains_sync_hw(struct drm_i915_private *dev_priv)

1865 {

1866 struct i915_power_domains *power_domains = &dev_priv->power_domains;

1867 struct i915_power_well *power_well;

1868 int i;

1869

1870 mutex_lock(&power_domains->lock);

1871 for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {

1872 power_well->ops->sync_hw(dev_priv, power_well);

1873 power_well->hw_enabled = power_well->ops->is_enabled(dev_priv,

1874 power_well);

1875 }

1876 mutex_unlock(&power_domains->lock);

1877 }

1878

1879 static void skl_display_core_init(struct drm_i915_private *dev_priv,

1880 bool resume)

1881 {

1882 struct i915_power_domains *power_domains = &dev_priv->power_domains;

1883 uint32_t val;

1884

1885 /* enable PCH reset handshake */

1886 val = I915_READ(HSW_NDE_RSTWRN_OPT);

1887 I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);

1888

1889 /* enable PG1 and Misc I/O */

1890 mutex_lock(&power_domains->lock);

1891 skl_pw1_misc_io_init(dev_priv);

1892 mutex_unlock(&power_domains->lock);

1893

1894 if (!resume)

1895 return;

1896

1897 skl_init_cdclk(dev_priv);

1898

1899 if (dev_priv->csr.dmc_payload)

1900 intel_csr_load_program(dev_priv);

1901 }

1902

1903 static void skl_display_core_uninit(struct drm_i915_private *dev_priv)

1904 {

1905 struct i915_power_domains *power_domains = &dev_priv->power_domains;

1906

1907 skl_uninit_cdclk(dev_priv);

1908

1909 /* The spec doesn't call for removing the reset handshake flag */

1910 /* disable PG1 and Misc I/O */

1911 mutex_lock(&power_domains->lock);

1912 skl_pw1_misc_io_fini(dev_priv);

1913 mutex_unlock(&power_domains->lock);

1914 }

1915

1916 static void chv_phy_control_init(struct drm_i915_private *dev_priv)

1917 {

1918 struct i915_power_well *cmn_bc =

1919 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);

1920 struct i915_power_well *cmn_d =

1921 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D);

1922

1923 /*

1924 * DISPLAY_PHY_CONTROL can get corrupted if read. As a

1925 * workaround never ever read DISPLAY_PHY_CONTROL, and

1926 * instead maintain a shadow copy ourselves. Use the actual

1927 * power well state and lane status to reconstruct the

1928 * expected initial value.

1929 */

1930 dev_priv->chv_phy_control =

1931 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY0) |

1932 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY1) |

1933 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH0) |

1934 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH1) |

1935 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY1, DPIO_CH0);

1936

1937 /*

1938 * If all lanes are disabled we leave the override disabled

1939 * with all power down bits cleared to match the state we

1940 * would use after disabling the port. Otherwise enable the

1941 * override and set the lane powerdown bits accding to the

1942 * current lane status.

1943 */

1944 if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) {

1945 uint32_t status = I915_READ(DPLL(PIPE_A));

1946 unsigned int mask;

1947

1948 mask = status & DPLL_PORTB_READY_MASK;

1949 if (mask == 0xf)

1950 mask = 0x0;

1951 else

1952 dev_priv->chv_phy_control |=

1953 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0);

1954

1955 dev_priv->chv_phy_control |=

1956 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH0);

1957

1958 mask = (status & DPLL_PORTC_READY_MASK) >> 4;

1959 if (mask == 0xf)

1960 mask = 0x0;

1961 else

1962 dev_priv->chv_phy_control |=

1963 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1);

1964

1965 dev_priv->chv_phy_control |=

1966 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH1);

1967

1968 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY0);

1969

1970 dev_priv->chv_phy_assert[DPIO_PHY0] = false;

1971 } else {

1972 dev_priv->chv_phy_assert[DPIO_PHY0] = true;

1973 }

1974

1975 if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) {

1976 uint32_t status = I915_READ(DPIO_PHY_STATUS);

1977 unsigned int mask;

1978

1979 mask = status & DPLL_PORTD_READY_MASK;

1980

1981 if (mask == 0xf)

1982 mask = 0x0;

1983 else

1984 dev_priv->chv_phy_control |=

1985 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0);

1986

1987 dev_priv->chv_phy_control |=

1988 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY1, DPIO_CH0);

1989

1990 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY1);

1991

1992 dev_priv->chv_phy_assert[DPIO_PHY1] = false;

1993 } else {

1994 dev_priv->chv_phy_assert[DPIO_PHY1] = true;

1995 }

1996

1997 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);

1998

1999 DRM_DEBUG_KMS("Initial PHY_CONTROL=0x%08x\n",

2000 dev_priv->chv_phy_control);

2001 }

2002

2003 static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv)

2004 {

2005 struct i915_power_well *cmn =

2006 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);

2007 struct i915_power_well *disp2d =

2008 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DISP2D);

2009

2010 /* If the display might be already active skip this */

2011 if (cmn->ops->is_enabled(dev_priv, cmn) &&

2012 disp2d->ops->is_enabled(dev_priv, disp2d) &&

2013 I915_READ(DPIO_CTL) & DPIO_CMNRST)

2014 return;

2015

2016 DRM_DEBUG_KMS("toggling display PHY side reset\n");

2017

2018 /* cmnlane needs DPLL registers */

2019 disp2d->ops->enable(dev_priv, disp2d);

2020

2021 /*

2022 * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx:

2023 * Need to assert and de-assert PHY SB reset by gating the

2024 * common lane power, then un-gating it.

2025 * Simply ungating isn't enough to reset the PHY enough to get

2026 * ports and lanes running.

2027 */

2028 cmn->ops->disable(dev_priv, cmn);

2029 }

2030

2031 /**

2032 * intel_power_domains_init_hw - initialize hardware power domain state

2033 * @dev_priv: i915 device instance

2034 *

2035 * This function initializes the hardware power domain state and enables all

2036 * power domains using intel_display_set_init_power().

2037 */

2038 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume)

2039 {

2040 struct drm_device *dev = dev_priv->dev;

2041 struct i915_power_domains *power_domains = &dev_priv->power_domains;

2042

2043 power_domains->initializing = true;

2044

2045 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {

2046 skl_display_core_init(dev_priv, resume);

2047 } else if (IS_CHERRYVIEW(dev)) {

2048 mutex_lock(&power_domains->lock);

2049 chv_phy_control_init(dev_priv);

2050 mutex_unlock(&power_domains->lock);

2051 } else if (IS_VALLEYVIEW(dev)) {

2052 mutex_lock(&power_domains->lock);

2053 vlv_cmnlane_wa(dev_priv);

2054 mutex_unlock(&power_domains->lock);

2055 }

2056

2057 /* For now, we need the power well to be always enabled. */

2058 intel_display_set_init_power(dev_priv, true);

2059 intel_power_domains_sync_hw(dev_priv);

2060 power_domains->initializing = false;

2061 }

2062

2063 /**

2064 * intel_power_domains_suspend - suspend power domain state

2065 * @dev_priv: i915 device instance

2066 *

2067 * This function prepares the hardware power domain state before entering

2068 * system suspend. It must be paired with intel_power_domains_init_hw().

2069 */

2070 void intel_power_domains_suspend(struct drm_i915_private *dev_priv)

2071 {

2072 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))

2073 skl_display_core_uninit(dev_priv);

2074 }

2075

2076 /**

2077 * intel_aux_display_runtime_get - grab an auxiliary power domain reference

2078 * @dev_priv: i915 device instance

2079 *

2080 * This function grabs a power domain reference for the auxiliary power domain

2081 * (for access to the GMBUS and DP AUX blocks) and ensures that it and all its

2082 * parents are powered up. Therefore users should only grab a reference to the

2083 * innermost power domain they need.

2084 *

2085 * Any power domain reference obtained by this function must have a symmetric

2086 * call to intel_aux_display_runtime_put() to release the reference again.

2087 */

2088 void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv)

2089 {

2090 intel_runtime_pm_get(dev_priv);

2091 }

2092

2093 /**

2094 * intel_aux_display_runtime_put - release an auxiliary power domain reference

2095 * @dev_priv: i915 device instance

2096 *

2097 * This function drops the auxiliary power domain reference obtained by

2098 * intel_aux_display_runtime_get() and might power down the corresponding

2099 * hardware block right away if this is the last reference.

2100 */

2101 void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv)

2102 {

2103 intel_runtime_pm_put(dev_priv);

2104 }

2105

2106 /**

2107 * intel_runtime_pm_get - grab a runtime pm reference

2108 * @dev_priv: i915 device instance

2109 *

2110 * This function grabs a device-level runtime pm reference (mostly used for GEM

2111 * code to ensure the GTT or GT is on) and ensures that it is powered up.

2112 *

2113 * Any runtime pm reference obtained by this function must have a symmetric

2114 * call to intel_runtime_pm_put() to release the reference again.

2115 */

2116 void intel_runtime_pm_get(struct drm_i915_private *dev_priv)

2117 {

2118 struct drm_device *dev = dev_priv->dev;

2119 struct device *device = &dev->pdev->dev;

2120

2121 if (!HAS_RUNTIME_PM(dev))

2122 return;

2123

2124 pm_runtime_get_sync(device);

2125 WARN(dev_priv->pm.suspended, "Device still suspended.\n");

2126 }

2127

2128 /**

2129 * intel_runtime_pm_get_noresume - grab a runtime pm reference

2130 * @dev_priv: i915 device instance

2131 *

2132 * This function grabs a device-level runtime pm reference (mostly used for GEM

2133 * code to ensure the GTT or GT is on).

2134 *

2135 * It will _not_ power up the device but instead only check that it's powered

2136 * on. Therefore it is only valid to call this functions from contexts where

2137 * the device is known to be powered up and where trying to power it up would

2138 * result in hilarity and deadlocks. That pretty much means only the system

2139 * suspend/resume code where this is used to grab runtime pm references for

2140 * delayed setup down in work items.

2141 *

2142 * Any runtime pm reference obtained by this function must have a symmetric

2143 * call to intel_runtime_pm_put() to release the reference again.

2144 */

2145 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv)

2146 {

2147 struct drm_device *dev = dev_priv->dev;

2148 struct device *device = &dev->pdev->dev;

2149

2150 if (!HAS_RUNTIME_PM(dev))

2151 return;

2152

2153 WARN(dev_priv->pm.suspended, "Getting nosync-ref while suspended.\n");

2154 pm_runtime_get_noresume(device);

2155 }

2156

2157 /**

2158 * intel_runtime_pm_put - release a runtime pm reference

2159 * @dev_priv: i915 device instance

2160 *

2161 * This function drops the device-level runtime pm reference obtained by

2162 * intel_runtime_pm_get() and might power down the corresponding

2163 * hardware block right away if this is the last reference.

2164 */

2165 void intel_runtime_pm_put(struct drm_i915_private *dev_priv)

2166 {

2167 struct drm_device *dev = dev_priv->dev;

2168 struct device *device = &dev->pdev->dev;

2169

2170 if (!HAS_RUNTIME_PM(dev))

2171 return;

2172

2173 pm_runtime_mark_last_busy(device);

2174 pm_runtime_put_autosuspend(device);

2175 }

2176

2177 /**

2178 * intel_runtime_pm_enable - enable runtime pm

2179 * @dev_priv: i915 device instance

2180 *

2181 * This function enables runtime pm at the end of the driver load sequence.

2182 *

2183 * Note that this function does currently not enable runtime pm for the

2184 * subordinate display power domains. That is only done on the first modeset

2185 * using intel_display_set_init_power().

2186 */

2187 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv)

2188 {

2189 struct drm_device *dev = dev_priv->dev;

2190 struct device *device = &dev->pdev->dev;

2191

2192 if (!HAS_RUNTIME_PM(dev))

2193 return;

2194

2195 /*

2196 * RPM depends on RC6 to save restore the GT HW context, so make RC6 a

2197 * requirement.

2198 */

2199 if (!intel_enable_rc6(dev)) {

2200 DRM_INFO("RC6 disabled, disabling runtime PM support\n");

2201 return;

2202 }

2203

2204 pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */

2205 pm_runtime_mark_last_busy(device);

2206 pm_runtime_use_autosuspend(device);

2207

2208 pm_runtime_put_autosuspend(device);

2209 }

2210