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1 /*

3 */

5 /*

6 * This file handles the architecture-dependent parts of initialization

7 */

9 #include <linux/errno.h>

10 #include <linux/sched.h>

11 #include <linux/kernel.h>

12 #include <linux/mm.h>

13 #include <linux/stddef.h>

14 #include <linux/unistd.h>

15 #include <linux/ptrace.h>

16 #include <linux/slab.h>

17 #include <linux/user.h>

18 #include <linux/screen_info.h>

19 #include <linux/ioport.h>

20 #include <linux/delay.h>

21 #include <linux/init.h>

22 #include <linux/initrd.h>

23 #include <linux/highmem.h>

24 #include <linux/bootmem.h>

25 #include <linux/module.h>

26 #include <asm/processor.h>

27 #include <linux/console.h>

28 #include <linux/seq_file.h>

29 #include <linux/crash_dump.h>

30 #include <linux/root_dev.h>

31 #include <linux/pci.h>

32 #include <linux/efi.h>

33 #include <linux/acpi.h>

34 #include <linux/kallsyms.h>

35 #include <linux/edd.h>

36 #include <linux/mmzone.h>

37 #include <linux/kexec.h>

38 #include <linux/cpufreq.h>

39 #include <linux/dmi.h>

40 #include <linux/dma-mapping.h>

41 #include <linux/ctype.h>

42 #include <linux/uaccess.h>

43 #include <linux/init_ohci1394_dma.h>

45 #include <asm/mtrr.h>

46 #include <asm/uaccess.h>

47 #include <asm/system.h>

48 #include <asm/vsyscall.h>

49 #include <asm/io.h>

50 #include <asm/smp.h>

51 #include <asm/msr.h>

52 #include <asm/desc.h>

53 #include <video/edid.h>

54 #include <asm/e820.h>

55 #include <asm/dma.h>

56 #include <asm/gart.h>

57 #include <asm/mpspec.h>

58 #include <asm/mmu_context.h>

59 #include <asm/proto.h>

60 #include <asm/setup.h>

61 #include <asm/mach_apic.h>

62 #include <asm/numa.h>

63 #include <asm/sections.h>

64 #include <asm/dmi.h>

65 #include <asm/cacheflush.h>

66 #include <asm/mce.h>

67 #include <asm/ds.h>

68 #include <asm/topology.h>

70 #ifdef CONFIG_PARAVIRT

71 #include <asm/paravirt.h>

72 #else

73 #define ARCH_SETUP

74 #endif

76 /*

77 * Machine setup..

78 */

80 struct cpuinfo_x86 boot_cpu_data __read_mostly;

81 EXPORT_SYMBOL(boot_cpu_data);

83 __u32 cleared_cpu_caps[NCAPINTS] __cpuinitdata;

85 unsigned long mmu_cr4_features;

87 /* Boot loader ID as an integer, for the benefit of proc_dointvec */

88 int bootloader_type;

90 unsigned long saved_video_mode;

92 int force_mwait __cpuinitdata;

94 /*

95 * Early DMI memory

96 */

97 int dmi_alloc_index;

98 char dmi_alloc_data[DMI_MAX_DATA];

100 /*

101 * Setup options

102 */

103 struct screen_info screen_info;

104 EXPORT_SYMBOL(screen_info);

105 struct sys_desc_table_struct {

106 unsigned short length;

107 unsigned char table[0];

108 };

109

110 struct edid_info edid_info;

111 EXPORT_SYMBOL_GPL(edid_info);

112

113 extern int root_mountflags;

114

115 char __initdata command_line[COMMAND_LINE_SIZE];

116

117 struct resource standard_io_resources[] = {

118 { .name = "dma1", .start = 0x00, .end = 0x1f,

119 .flags = IORESOURCE_BUSY | IORESOURCE_IO },

120 { .name = "pic1", .start = 0x20, .end = 0x21,

121 .flags = IORESOURCE_BUSY | IORESOURCE_IO },

122 { .name = "timer0", .start = 0x40, .end = 0x43,

123 .flags = IORESOURCE_BUSY | IORESOURCE_IO },

124 { .name = "timer1", .start = 0x50, .end = 0x53,

125 .flags = IORESOURCE_BUSY | IORESOURCE_IO },

126 { .name = "keyboard", .start = 0x60, .end = 0x6f,

127 .flags = IORESOURCE_BUSY | IORESOURCE_IO },

128 { .name = "dma page reg", .start = 0x80, .end = 0x8f,

129 .flags = IORESOURCE_BUSY | IORESOURCE_IO },

130 { .name = "pic2", .start = 0xa0, .end = 0xa1,

131 .flags = IORESOURCE_BUSY | IORESOURCE_IO },

132 { .name = "dma2", .start = 0xc0, .end = 0xdf,

133 .flags = IORESOURCE_BUSY | IORESOURCE_IO },

134 { .name = "fpu", .start = 0xf0, .end = 0xff,

135 .flags = IORESOURCE_BUSY | IORESOURCE_IO }

136 };

137

138 #define IORESOURCE_RAM (IORESOURCE_BUSY | IORESOURCE_MEM)

139

140 static struct resource data_resource = {

141 .name = "Kernel data",

142 .start = 0,

143 .end = 0,

144 .flags = IORESOURCE_RAM,

145 };

146 static struct resource code_resource = {

147 .name = "Kernel code",

148 .start = 0,

149 .end = 0,

150 .flags = IORESOURCE_RAM,

151 };

152 static struct resource bss_resource = {

153 .name = "Kernel bss",

154 .start = 0,

155 .end = 0,

156 .flags = IORESOURCE_RAM,

157 };

158

159 static void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c);

160

161 #ifdef CONFIG_PROC_VMCORE

162 /* elfcorehdr= specifies the location of elf core header

163 * stored by the crashed kernel. This option will be passed

164 * by kexec loader to the capture kernel.

165 */

166 static int __init setup_elfcorehdr(char *arg)

167 {

168 char *end;

169 if (!arg)

170 return -EINVAL;

171 elfcorehdr_addr = memparse(arg, &end);

172 return end > arg ? 0 : -EINVAL;

173 }

174 early_param("elfcorehdr", setup_elfcorehdr);

175 #endif

176

177 #ifndef CONFIG_NUMA

178 static void __init

179 contig_initmem_init(unsigned long start_pfn, unsigned long end_pfn)

180 {

181 unsigned long bootmap_size, bootmap;

182

183 bootmap_size = bootmem_bootmap_pages(end_pfn)<<PAGE_SHIFT;

184 bootmap = find_e820_area(0, end_pfn<<PAGE_SHIFT, bootmap_size,

185 PAGE_SIZE);

186 if (bootmap == -1L)

187 panic("Cannot find bootmem map of size %ld\n", bootmap_size);

188 bootmap_size = init_bootmem(bootmap >> PAGE_SHIFT, end_pfn);

189 e820_register_active_regions(0, start_pfn, end_pfn);

190 free_bootmem_with_active_regions(0, end_pfn);

191 reserve_bootmem(bootmap, bootmap_size, BOOTMEM_DEFAULT);

192 }

193 #endif

194

195 #if defined(CONFIG_EDD) || defined(CONFIG_EDD_MODULE)

196 struct edd edd;

197 #ifdef CONFIG_EDD_MODULE

198 EXPORT_SYMBOL(edd);

199 #endif

200 /**

201 * copy_edd() - Copy the BIOS EDD information

202 * from boot_params into a safe place.

203 *

204 */

205 static inline void copy_edd(void)

206 {

207 memcpy(edd.mbr_signature, boot_params.edd_mbr_sig_buffer,

208 sizeof(edd.mbr_signature));

209 memcpy(edd.edd_info, boot_params.eddbuf, sizeof(edd.edd_info));

210 edd.mbr_signature_nr = boot_params.edd_mbr_sig_buf_entries;

211 edd.edd_info_nr = boot_params.eddbuf_entries;

212 }

213 #else

214 static inline void copy_edd(void)

215 {

216 }

217 #endif

218

219 #ifdef CONFIG_KEXEC

220 static void __init reserve_crashkernel(void)

221 {

222 unsigned long long total_mem;

223 unsigned long long crash_size, crash_base;

224 int ret;

225

226 total_mem = ((unsigned long long)max_low_pfn - min_low_pfn) << PAGE_SHIFT;

227

228 ret = parse_crashkernel(boot_command_line, total_mem,

229 &crash_size, &crash_base);

230 if (ret == 0 && crash_size) {

231 if (crash_base <= 0) {

232 printk(KERN_INFO "crashkernel reservation failed - "

233 "you have to specify a base address\n");

234 return;

235 }

236

237 if (reserve_bootmem(crash_base, crash_size,

238 BOOTMEM_EXCLUSIVE) < 0) {

239 printk(KERN_INFO "crashkernel reservation failed - "

240 "memory is in use\n");

241 return;

242 }

243

244 printk(KERN_INFO "Reserving %ldMB of memory at %ldMB "

245 "for crashkernel (System RAM: %ldMB)\n",

246 (unsigned long)(crash_size >> 20),

247 (unsigned long)(crash_base >> 20),

248 (unsigned long)(total_mem >> 20));

249 crashk_res.start = crash_base;

250 crashk_res.end = crash_base + crash_size - 1;

251 insert_resource(&iomem_resource, &crashk_res);

252 }

253 }

254 #else

255 static inline void __init reserve_crashkernel(void)

256 {}

257 #endif

258

259 /* Overridden in paravirt.c if CONFIG_PARAVIRT */

260 void __attribute__((weak)) __init memory_setup(void)

261 {

262 machine_specific_memory_setup();

263 }

264

265 /*

266 * setup_arch - architecture-specific boot-time initializations

267 *

268 * Note: On x86_64, fixmaps are ready for use even before this is called.

269 */

270 void __init setup_arch(char **cmdline_p)

271 {

272 unsigned i;

273

274 printk(KERN_INFO "Command line: %s\n", boot_command_line);

275

276 ROOT_DEV = old_decode_dev(boot_params.hdr.root_dev);

277 screen_info = boot_params.screen_info;

278 edid_info = boot_params.edid_info;

279 saved_video_mode = boot_params.hdr.vid_mode;

280 bootloader_type = boot_params.hdr.type_of_loader;

281

282 #ifdef CONFIG_BLK_DEV_RAM

283 rd_image_start = boot_params.hdr.ram_size & RAMDISK_IMAGE_START_MASK;

284 rd_prompt = ((boot_params.hdr.ram_size & RAMDISK_PROMPT_FLAG) != 0);

285 rd_doload = ((boot_params.hdr.ram_size & RAMDISK_LOAD_FLAG) != 0);

286 #endif

287 #ifdef CONFIG_EFI

288 if (!strncmp((char *)&boot_params.efi_info.efi_loader_signature,

289 "EL64", 4))

290 efi_enabled = 1;

291 #endif

292

293 ARCH_SETUP

294

295 memory_setup();

296 copy_edd();

297

298 if (!boot_params.hdr.root_flags)

299 root_mountflags &= ~MS_RDONLY;

300 init_mm.start_code = (unsigned long) &_text;

301 init_mm.end_code = (unsigned long) &_etext;

302 init_mm.end_data = (unsigned long) &_edata;

303 init_mm.brk = (unsigned long) &_end;

304

305 code_resource.start = virt_to_phys(&_text);

306 code_resource.end = virt_to_phys(&_etext)-1;

307 data_resource.start = virt_to_phys(&_etext);

308 data_resource.end = virt_to_phys(&_edata)-1;

309 bss_resource.start = virt_to_phys(&__bss_start);

310 bss_resource.end = virt_to_phys(&__bss_stop)-1;

311

312 early_identify_cpu(&boot_cpu_data);

313

314 strlcpy(command_line, boot_command_line, COMMAND_LINE_SIZE);

315 *cmdline_p = command_line;

316

317 parse_early_param();

318

319 #ifdef CONFIG_PROVIDE_OHCI1394_DMA_INIT

320 if (init_ohci1394_dma_early)

321 init_ohci1394_dma_on_all_controllers();

322 #endif

323

324 finish_e820_parsing();

325

326 /* after parse_early_param, so could debug it */

327 insert_resource(&iomem_resource, &code_resource);

328 insert_resource(&iomem_resource, &data_resource);

329 insert_resource(&iomem_resource, &bss_resource);

330

331 early_gart_iommu_check();

332

333 e820_register_active_regions(0, 0, -1UL);

334 /*

335 * partially used pages are not usable - thus

336 * we are rounding upwards:

337 */

338 end_pfn = e820_end_of_ram();

339 /* update e820 for memory not covered by WB MTRRs */

340 mtrr_bp_init();

341 if (mtrr_trim_uncached_memory(end_pfn)) {

342 e820_register_active_regions(0, 0, -1UL);

343 end_pfn = e820_end_of_ram();

344 }

345

346 num_physpages = end_pfn;

347

348 check_efer();

349

350 init_memory_mapping(0, (end_pfn_map << PAGE_SHIFT));

351 if (efi_enabled)

352 efi_init();

353

354 #ifdef CONFIG_PARAVIRT

355 vsmp_init();

356 #endif

357

358 dmi_scan_machine();

359

360 io_delay_init();

361

362 #ifdef CONFIG_SMP

363 /* setup to use the early static init tables during kernel startup */

364 x86_cpu_to_apicid_early_ptr = (void *)x86_cpu_to_apicid_init;

365 x86_bios_cpu_apicid_early_ptr = (void *)x86_bios_cpu_apicid_init;

366 #ifdef CONFIG_NUMA

367 x86_cpu_to_node_map_early_ptr = (void *)x86_cpu_to_node_map_init;

368 #endif

369 #endif

370

371 #ifdef CONFIG_ACPI

372 /*

373 * Initialize the ACPI boot-time table parser (gets the RSDP and SDT).

374 * Call this early for SRAT node setup.

375 */

376 acpi_boot_table_init();

377 #endif

378

379 /* How many end-of-memory variables you have, grandma! */

380 max_low_pfn = end_pfn;

381 max_pfn = end_pfn;

382 high_memory = (void *)__va(end_pfn * PAGE_SIZE - 1) + 1;

383

384 /* Remove active ranges so rediscovery with NUMA-awareness happens */

385 remove_all_active_ranges();

386

387 #ifdef CONFIG_ACPI_NUMA

388 /*

389 * Parse SRAT to discover nodes.

390 */

391 acpi_numa_init();

392 #endif

393

394 #ifdef CONFIG_NUMA

395 numa_initmem_init(0, end_pfn);

396 #else

397 contig_initmem_init(0, end_pfn);

398 #endif

399

400 early_res_to_bootmem();

401

402 #ifdef CONFIG_ACPI_SLEEP

403 /*

404 * Reserve low memory region for sleep support.

405 */

406 acpi_reserve_bootmem();

407 #endif

408

409 if (efi_enabled)

410 efi_reserve_bootmem();

411

412 /*

413 * Find and reserve possible boot-time SMP configuration:

414 */

415 find_smp_config();

416 #ifdef CONFIG_BLK_DEV_INITRD

417 if (boot_params.hdr.type_of_loader && boot_params.hdr.ramdisk_image) {

418 unsigned long ramdisk_image = boot_params.hdr.ramdisk_image;

419 unsigned long ramdisk_size = boot_params.hdr.ramdisk_size;

420 unsigned long ramdisk_end = ramdisk_image + ramdisk_size;

421 unsigned long end_of_mem = end_pfn << PAGE_SHIFT;

422

423 if (ramdisk_end <= end_of_mem) {

424 reserve_bootmem_generic(ramdisk_image, ramdisk_size);

425 initrd_start = ramdisk_image + PAGE_OFFSET;

426 initrd_end = initrd_start+ramdisk_size;

427 } else {

428 /* Assumes everything on node 0 */

429 free_bootmem(ramdisk_image, ramdisk_size);

430 printk(KERN_ERR "initrd extends beyond end of memory "

431 "(0x%08lx > 0x%08lx)\ndisabling initrd\n",

432 ramdisk_end, end_of_mem);

433 initrd_start = 0;

434 }

435 }

436 #endif

437 reserve_crashkernel();

438 paging_init();

439 map_vsyscall();

440

441 early_quirks();

442

443 #ifdef CONFIG_ACPI

444 /*

445 * Read APIC and some other early information from ACPI tables.

446 */

447 acpi_boot_init();

448 #endif

449

450 init_cpu_to_node();

451

452 /*

453 * get boot-time SMP configuration:

454 */

455 if (smp_found_config)

456 get_smp_config();

457 init_apic_mappings();

458 ioapic_init_mappings();

459

460 /*

461 * We trust e820 completely. No explicit ROM probing in memory.

462 */

463 e820_reserve_resources();

464 e820_mark_nosave_regions();

465

466 /* request I/O space for devices used on all i[345]86 PCs */

467 for (i = 0; i < ARRAY_SIZE(standard_io_resources); i++)

468 request_resource(&ioport_resource, &standard_io_resources[i]);

469

470 e820_setup_gap();

471

472 #ifdef CONFIG_VT

473 #if defined(CONFIG_VGA_CONSOLE)

474 if (!efi_enabled || (efi_mem_type(0xa0000) != EFI_CONVENTIONAL_MEMORY))

475 conswitchp = &vga_con;

476 #elif defined(CONFIG_DUMMY_CONSOLE)

477 conswitchp = &dummy_con;

478 #endif

479 #endif

480 }

481

482 static int __cpuinit get_model_name(struct cpuinfo_x86 *c)

483 {

484 unsigned int *v;

485

486 if (c->extended_cpuid_level < 0x80000004)

487 return 0;

488

489 v = (unsigned int *) c->x86_model_id;

490 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);

491 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);

492 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);

493 c->x86_model_id[48] = 0;

494 return 1;

495 }

496

497

498 static void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)

499 {

500 unsigned int n, dummy, eax, ebx, ecx, edx;

501

502 n = c->extended_cpuid_level;

503

504 if (n >= 0x80000005) {

505 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);

506 printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), "

507 "D cache %dK (%d bytes/line)\n",

508 edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);

509 c->x86_cache_size = (ecx>>24) + (edx>>24);

510 /* On K8 L1 TLB is inclusive, so don't count it */

511 c->x86_tlbsize = 0;

512 }

513

514 if (n >= 0x80000006) {

515 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);

516 ecx = cpuid_ecx(0x80000006);

517 c->x86_cache_size = ecx >> 16;

518 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);

519

520 printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",

521 c->x86_cache_size, ecx & 0xFF);

522 }

523 if (n >= 0x80000008) {

524 cpuid(0x80000008, &eax, &dummy, &dummy, &dummy);

525 c->x86_virt_bits = (eax >> 8) & 0xff;

526 c->x86_phys_bits = eax & 0xff;

527 }

528 }

529

530 #ifdef CONFIG_NUMA

531 static int __cpuinit nearby_node(int apicid)

532 {

533 int i, node;

534

535 for (i = apicid - 1; i >= 0; i--) {

536 node = apicid_to_node[i];

537 if (node != NUMA_NO_NODE && node_online(node))

538 return node;

539 }

540 for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) {

541 node = apicid_to_node[i];

542 if (node != NUMA_NO_NODE && node_online(node))

543 return node;

544 }

545 return first_node(node_online_map); /* Shouldn't happen */

546 }

547 #endif

548

549 /*

550 * On a AMD dual core setup the lower bits of the APIC id distingush the cores.

551 * Assumes number of cores is a power of two.

552 */

553 static void __cpuinit amd_detect_cmp(struct cpuinfo_x86 *c)

554 {

555 #ifdef CONFIG_SMP

556 unsigned bits;

557 #ifdef CONFIG_NUMA

558 int cpu = smp_processor_id();

559 int node = 0;

560 unsigned apicid = hard_smp_processor_id();

561 #endif

562 bits = c->x86_coreid_bits;

563

564 /* Low order bits define the core id (index of core in socket) */

565 c->cpu_core_id = c->phys_proc_id & ((1 << bits)-1);

566 /* Convert the APIC ID into the socket ID */

567 c->phys_proc_id = phys_pkg_id(bits);

568

569 #ifdef CONFIG_NUMA

570 node = c->phys_proc_id;

571 if (apicid_to_node[apicid] != NUMA_NO_NODE)

572 node = apicid_to_node[apicid];

573 if (!node_online(node)) {

574 /* Two possibilities here:

575 - The CPU is missing memory and no node was created.

576 In that case try picking one from a nearby CPU

577 - The APIC IDs differ from the HyperTransport node IDs

578 which the K8 northbridge parsing fills in.

579 Assume they are all increased by a constant offset,

580 but in the same order as the HT nodeids.

581 If that doesn't result in a usable node fall back to the

582 path for the previous case. */

583

584 int ht_nodeid = apicid - (cpu_data(0).phys_proc_id << bits);

585

586 if (ht_nodeid >= 0 &&

587 apicid_to_node[ht_nodeid] != NUMA_NO_NODE)

588 node = apicid_to_node[ht_nodeid];

589 /* Pick a nearby node */

590 if (!node_online(node))

591 node = nearby_node(apicid);

592 }

593 numa_set_node(cpu, node);

594

595 printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node);

596 #endif

597 #endif

598 }

599

600 static void __cpuinit early_init_amd_mc(struct cpuinfo_x86 *c)

601 {

602 #ifdef CONFIG_SMP

603 unsigned bits, ecx;

604

605 /* Multi core CPU? */

606 if (c->extended_cpuid_level < 0x80000008)

607 return;

608

609 ecx = cpuid_ecx(0x80000008);

610

611 c->x86_max_cores = (ecx & 0xff) + 1;

612

613 /* CPU telling us the core id bits shift? */

614 bits = (ecx >> 12) & 0xF;

615

616 /* Otherwise recompute */

617 if (bits == 0) {

618 while ((1 << bits) < c->x86_max_cores)

619 bits++;

620 }

621

622 c->x86_coreid_bits = bits;

623

624 #endif

625 }

626

627 #define ENABLE_C1E_MASK 0x18000000

628 #define CPUID_PROCESSOR_SIGNATURE 1

629 #define CPUID_XFAM 0x0ff00000

630 #define CPUID_XFAM_K8 0x00000000

631 #define CPUID_XFAM_10H 0x00100000

632 #define CPUID_XFAM_11H 0x00200000

633 #define CPUID_XMOD 0x000f0000

634 #define CPUID_XMOD_REV_F 0x00040000

635

636 /* AMD systems with C1E don't have a working lAPIC timer. Check for that. */

637 static __cpuinit int amd_apic_timer_broken(void)

638 {

639 u32 lo, hi, eax = cpuid_eax(CPUID_PROCESSOR_SIGNATURE);

640

641 switch (eax & CPUID_XFAM) {

642 case CPUID_XFAM_K8:

643 if ((eax & CPUID_XMOD) < CPUID_XMOD_REV_F)

644 break;

645 case CPUID_XFAM_10H:

646 case CPUID_XFAM_11H:

647 rdmsr(MSR_K8_ENABLE_C1E, lo, hi);

648 if (lo & ENABLE_C1E_MASK)

649 return 1;

650 break;

651 default:

652 /* err on the side of caution */

653 return 1;

654 }

655 return 0;

656 }

657

658 static void __cpuinit early_init_amd(struct cpuinfo_x86 *c)

659 {

660 early_init_amd_mc(c);

661

662 /* c->x86_power is 8000_0007 edx. Bit 8 is constant TSC */

663 if (c->x86_power & (1<<8))

664 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);

665 }

666

667 static void __cpuinit init_amd(struct cpuinfo_x86 *c)

668 {

669 unsigned level;

670

671 #ifdef CONFIG_SMP

672 unsigned long value;

673

674 /*

675 * Disable TLB flush filter by setting HWCR.FFDIS on K8

676 * bit 6 of msr C001_0015

677 *

678 * Errata 63 for SH-B3 steppings

679 * Errata 122 for all steppings (F+ have it disabled by default)

680 */

681 if (c->x86 == 15) {

682 rdmsrl(MSR_K8_HWCR, value);

683 value |= 1 << 6;

684 wrmsrl(MSR_K8_HWCR, value);

685 }

686 #endif

687

688 /* Bit 31 in normal CPUID used for nonstandard 3DNow ID;

689 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */

690 clear_bit(0*32+31, (unsigned long *)&c->x86_capability);

691

692 /* On C+ stepping K8 rep microcode works well for copy/memset */

693 level = cpuid_eax(1);

694 if (c->x86 == 15 && ((level >= 0x0f48 && level < 0x0f50) ||

695 level >= 0x0f58))

696 set_cpu_cap(c, X86_FEATURE_REP_GOOD);

697 if (c->x86 == 0x10 || c->x86 == 0x11)

698 set_cpu_cap(c, X86_FEATURE_REP_GOOD);

699

700 /* Enable workaround for FXSAVE leak */

701 if (c->x86 >= 6)

702 set_cpu_cap(c, X86_FEATURE_FXSAVE_LEAK);

703

704 level = get_model_name(c);

705 if (!level) {

706 switch (c->x86) {

707 case 15:

708 /* Should distinguish Models here, but this is only

709 a fallback anyways. */

710 strcpy(c->x86_model_id, "Hammer");

711 break;

712 }

713 }

714 display_cacheinfo(c);

715

716 /* Multi core CPU? */

717 if (c->extended_cpuid_level >= 0x80000008)

718 amd_detect_cmp(c);

719

720 if (c->extended_cpuid_level >= 0x80000006 &&

721 (cpuid_edx(0x80000006) & 0xf000))

722 num_cache_leaves = 4;

723 else

724 num_cache_leaves = 3;

725

726 if (c->x86 == 0xf || c->x86 == 0x10 || c->x86 == 0x11)

727 set_cpu_cap(c, X86_FEATURE_K8);

728

729 /* MFENCE stops RDTSC speculation */

730 set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC);

731

732 if (amd_apic_timer_broken())

733 disable_apic_timer = 1;

734 }

735

736 void __cpuinit detect_ht(struct cpuinfo_x86 *c)

737 {

738 #ifdef CONFIG_SMP

739 u32 eax, ebx, ecx, edx;

740 int index_msb, core_bits;

741

742 cpuid(1, &eax, &ebx, &ecx, &edx);

743

744

745 if (!cpu_has(c, X86_FEATURE_HT))

746 return;

747 if (cpu_has(c, X86_FEATURE_CMP_LEGACY))

748 goto out;

749

750 smp_num_siblings = (ebx & 0xff0000) >> 16;

751

752 if (smp_num_siblings == 1) {

753 printk(KERN_INFO "CPU: Hyper-Threading is disabled\n");

754 } else if (smp_num_siblings > 1) {

755

756 if (smp_num_siblings > NR_CPUS) {

757 printk(KERN_WARNING "CPU: Unsupported number of "

758 "siblings %d", smp_num_siblings);

759 smp_num_siblings = 1;

760 return;

761 }

762

763 index_msb = get_count_order(smp_num_siblings);

764 c->phys_proc_id = phys_pkg_id(index_msb);

765

766 smp_num_siblings = smp_num_siblings / c->x86_max_cores;

767

768 index_msb = get_count_order(smp_num_siblings);

769

770 core_bits = get_count_order(c->x86_max_cores);

771

772 c->cpu_core_id = phys_pkg_id(index_msb) &

773 ((1 << core_bits) - 1);

774 }

775 out:

776 if ((c->x86_max_cores * smp_num_siblings) > 1) {

777 printk(KERN_INFO "CPU: Physical Processor ID: %d\n",

778 c->phys_proc_id);

779 printk(KERN_INFO "CPU: Processor Core ID: %d\n",

780 c->cpu_core_id);

781 }

782

783 #endif

784 }

785

786 /*

787 * find out the number of processor cores on the die

788 */

789 static int __cpuinit intel_num_cpu_cores(struct cpuinfo_x86 *c)

790 {

791 unsigned int eax, t;

792

793 if (c->cpuid_level < 4)

794 return 1;

795

796 cpuid_count(4, 0, &eax, &t, &t, &t);

797

798 if (eax & 0x1f)

799 return ((eax >> 26) + 1);

800 else

801 return 1;

802 }

803

804 static void __cpuinit srat_detect_node(void)

805 {

806 #ifdef CONFIG_NUMA

807 unsigned node;

808 int cpu = smp_processor_id();

809 int apicid = hard_smp_processor_id();

810

811 /* Don't do the funky fallback heuristics the AMD version employs

812 for now. */

813 node = apicid_to_node[apicid];

814 if (node == NUMA_NO_NODE || !node_online(node))

815 node = first_node(node_online_map);

816 numa_set_node(cpu, node);

817

818 printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node);

819 #endif

820 }

821

822 static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)

823 {

824 if ((c->x86 == 0xf && c->x86_model >= 0x03) ||

825 (c->x86 == 0x6 && c->x86_model >= 0x0e))

826 set_bit(X86_FEATURE_CONSTANT_TSC, &c->x86_capability);

827 }

828

829 static void __cpuinit init_intel(struct cpuinfo_x86 *c)

830 {

831 /* Cache sizes */

832 unsigned n;

833

834 init_intel_cacheinfo(c);

835 if (c->cpuid_level > 9) {

836 unsigned eax = cpuid_eax(10);

837 /* Check for version and the number of counters */

838 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))

839 set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);

840 }

841

842 if (cpu_has_ds) {

843 unsigned int l1, l2;

844 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);

845 if (!(l1 & (1<<11)))

846 set_cpu_cap(c, X86_FEATURE_BTS);

847 if (!(l1 & (1<<12)))

848 set_cpu_cap(c, X86_FEATURE_PEBS);

849 }

850

851

852 if (cpu_has_bts)

853 ds_init_intel(c);

854

855 n = c->extended_cpuid_level;

856 if (n >= 0x80000008) {

857 unsigned eax = cpuid_eax(0x80000008);

858 c->x86_virt_bits = (eax >> 8) & 0xff;

859 c->x86_phys_bits = eax & 0xff;

860 /* CPUID workaround for Intel 0F34 CPU */

861 if (c->x86_vendor == X86_VENDOR_INTEL &&

862 c->x86 == 0xF && c->x86_model == 0x3 &&

863 c->x86_mask == 0x4)

864 c->x86_phys_bits = 36;

865 }

866

867 if (c->x86 == 15)

868 c->x86_cache_alignment = c->x86_clflush_size * 2;

869 if (c->x86 == 6)

870 set_cpu_cap(c, X86_FEATURE_REP_GOOD);

871 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);

872 c->x86_max_cores = intel_num_cpu_cores(c);

873

874 srat_detect_node();

875 }

876

877 static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)

878 {

879 char *v = c->x86_vendor_id;

880

881 if (!strcmp(v, "AuthenticAMD"))

882 c->x86_vendor = X86_VENDOR_AMD;

883 else if (!strcmp(v, "GenuineIntel"))

884 c->x86_vendor = X86_VENDOR_INTEL;

885 else

886 c->x86_vendor = X86_VENDOR_UNKNOWN;

887 }

888

889 /* Do some early cpuid on the boot CPU to get some parameter that are

890 needed before check_bugs. Everything advanced is in identify_cpu

891 below. */

892 static void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c)

893 {

894 u32 tfms, xlvl;

895

896 c->loops_per_jiffy = loops_per_jiffy;

897 c->x86_cache_size = -1;

898 c->x86_vendor = X86_VENDOR_UNKNOWN;

899 c->x86_model = c->x86_mask = 0; /* So far unknown... */

900 c->x86_vendor_id[0] = '\0'; /* Unset */

901 c->x86_model_id[0] = '\0'; /* Unset */

902 c->x86_clflush_size = 64;

903 c->x86_cache_alignment = c->x86_clflush_size;

904 c->x86_max_cores = 1;

905 c->x86_coreid_bits = 0;

906 c->extended_cpuid_level = 0;

907 memset(&c->x86_capability, 0, sizeof c->x86_capability);

908

909 /* Get vendor name */

910 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,

911 (unsigned int *)&c->x86_vendor_id[0],

912 (unsigned int *)&c->x86_vendor_id[8],

913 (unsigned int *)&c->x86_vendor_id[4]);

914

915 get_cpu_vendor(c);

916

917 /* Initialize the standard set of capabilities */

918 /* Note that the vendor-specific code below might override */

919

920 /* Intel-defined flags: level 0x00000001 */

921 if (c->cpuid_level >= 0x00000001) {

922 __u32 misc;

923 cpuid(0x00000001, &tfms, &misc, &c->x86_capability[4],

924 &c->x86_capability[0]);

925 c->x86 = (tfms >> 8) & 0xf;

926 c->x86_model = (tfms >> 4) & 0xf;

927 c->x86_mask = tfms & 0xf;

928 if (c->x86 == 0xf)

929 c->x86 += (tfms >> 20) & 0xff;

930 if (c->x86 >= 0x6)

931 c->x86_model += ((tfms >> 16) & 0xF) << 4;

932 if (c->x86_capability[0] & (1<<19))

933 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;

934 } else {

935 /* Have CPUID level 0 only - unheard of */

936 c->x86 = 4;

937 }

938

939 #ifdef CONFIG_SMP

940 c->phys_proc_id = (cpuid_ebx(1) >> 24) & 0xff;

941 #endif

942 /* AMD-defined flags: level 0x80000001 */

943 xlvl = cpuid_eax(0x80000000);

944 c->extended_cpuid_level = xlvl;

945 if ((xlvl & 0xffff0000) == 0x80000000) {

946 if (xlvl >= 0x80000001) {

947 c->x86_capability[1] = cpuid_edx(0x80000001);

948 c->x86_capability[6] = cpuid_ecx(0x80000001);

949 }

950 if (xlvl >= 0x80000004)

951 get_model_name(c); /* Default name */

952 }

953

954 /* Transmeta-defined flags: level 0x80860001 */

955 xlvl = cpuid_eax(0x80860000);

956 if ((xlvl & 0xffff0000) == 0x80860000) {

957 /* Don't set x86_cpuid_level here for now to not confuse. */

958 if (xlvl >= 0x80860001)

959 c->x86_capability[2] = cpuid_edx(0x80860001);

960 }

961

962 c->extended_cpuid_level = cpuid_eax(0x80000000);

963 if (c->extended_cpuid_level >= 0x80000007)

964 c->x86_power = cpuid_edx(0x80000007);

965

966 switch (c->x86_vendor) {

967 case X86_VENDOR_AMD:

968 early_init_amd(c);

969 break;

970 case X86_VENDOR_INTEL:

971 early_init_intel(c);

972 break;

973 }

974

975 }

976

977 /*

978 * This does the hard work of actually picking apart the CPU stuff...

979 */

980 void __cpuinit identify_cpu(struct cpuinfo_x86 *c)

981 {

982 int i;

983

984 early_identify_cpu(c);

985

986 init_scattered_cpuid_features(c);

987

988 c->apicid = phys_pkg_id(0);

989

990 /*

991 * Vendor-specific initialization. In this section we

992 * canonicalize the feature flags, meaning if there are

993 * features a certain CPU supports which CPUID doesn't

994 * tell us, CPUID claiming incorrect flags, or other bugs,

995 * we handle them here.

996 *

997 * At the end of this section, c->x86_capability better

998 * indicate the features this CPU genuinely supports!

999 */

1000 switch (c->x86_vendor) {

1001 case X86_VENDOR_AMD:

1002 init_amd(c);

1003 break;

1004

1005 case X86_VENDOR_INTEL:

1006 init_intel(c);

1007 break;

1008

1009 case X86_VENDOR_UNKNOWN:

1010 default:

1011 display_cacheinfo(c);

1012 break;

1013 }

1014

1015 detect_ht(c);

1016

1017 /*

1018 * On SMP, boot_cpu_data holds the common feature set between

1019 * all CPUs; so make sure that we indicate which features are

1020 * common between the CPUs. The first time this routine gets

1021 * executed, c == &boot_cpu_data.

1022 */

1023 if (c != &boot_cpu_data) {

1024 /* AND the already accumulated flags with these */

1025 for (i = 0; i < NCAPINTS; i++)

1026 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];

1027 }

1028

1029 /* Clear all flags overriden by options */

1030 for (i = 0; i < NCAPINTS; i++)

1031 c->x86_capability[i] &= ~cleared_cpu_caps[i];

1032

1033 #ifdef CONFIG_X86_MCE

1034 mcheck_init(c);

1035 #endif

1036 select_idle_routine(c);

1037

1038 if (c != &boot_cpu_data)

1039 mtrr_ap_init();

1040 #ifdef CONFIG_NUMA

1041 numa_add_cpu(smp_processor_id());

1042 #endif

1043

1044 }

1045

1046 static __init int setup_noclflush(char *arg)

1047 {

1048 setup_clear_cpu_cap(X86_FEATURE_CLFLSH);

1049 return 1;

1050 }

1051 __setup("noclflush", setup_noclflush);

1052

1053 void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)

1054 {

1055 if (c->x86_model_id[0])

1056 printk(KERN_CONT "%s", c->x86_model_id);

1057

1058 if (c->x86_mask || c->cpuid_level >= 0)

1059 printk(KERN_CONT " stepping %02x\n", c->x86_mask);

1060 else

1061 printk(KERN_CONT "\n");

1062 }

1063

1064 static __init int setup_disablecpuid(char *arg)

1065 {

1066 int bit;

1067 if (get_option(&arg, &bit) && bit < NCAPINTS*32)

1068 setup_clear_cpu_cap(bit);

1069 else

1070 return 0;

1071 return 1;

1072 }

1073 __setup("clearcpuid=", setup_disablecpuid);