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1 --- a/arch/mips/ar231x/Makefile
2 +++ b/arch/mips/ar231x/Makefile
3 @@ -14,3 +14,4 @@ obj-$(CONFIG_EARLY_PRINTK) += early_prin
4
5 obj-$(CONFIG_ATHEROS_AR5312) += ar5312.o
6 obj-$(CONFIG_ATHEROS_AR2315) += ar2315.o
7 +obj-$(CONFIG_ATHEROS_AR2315_PCI) += pci.o
8 --- /dev/null
9 +++ b/arch/mips/ar231x/pci.c
10 @@ -0,0 +1,337 @@
11 +/*
12 + * This program is free software; you can redistribute it and/or
13 + * modify it under the terms of the GNU General Public License
14 + * as published by the Free Software Foundation; either version 2
15 + * of the License, or (at your option) any later version.
16 + *
17 + * This program is distributed in the hope that it will be useful,
18 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 + * GNU General Public License for more details.
21 + *
22 + * You should have received a copy of the GNU General Public License
23 + * along with this program; if not, see <http://www.gnu.org/licenses/>.
24 + */
25 +
26 +/**
27 + * Both AR2315 and AR2316 chips have PCI interface unit, which supports DMA
28 + * and interrupt. PCI interface supports MMIO access method, but does not
29 + * seem to support I/O ports.
30 + *
31 + * Read/write operation in the region 0x80000000-0xBFFFFFFF causes
32 + * a memory read/write command on the PCI bus. 30 LSBs of address on
33 + * the bus are taken from memory read/write request and 2 MSBs are
34 + * determined by PCI unit configuration.
35 + *
36 + * To work with the configuration space instead of memory is necessary set
37 + * the CFG_SEL bit in the PCI_MISC_CONFIG register.
38 + *
39 + * Devices on the bus can perform DMA requests via chip BAR1. PCI host
40 + * controller BARs are programmend as if an external device is programmed.
41 + * Which means that during configuration, IDSEL pin of the chip should be
42 + * asserted.
43 + *
44 + * We know (and support) only one board that uses the PCI interface -
45 + * Fonera 2.0g (FON2202). It has a USB EHCI controller connected to the
46 + * AR2315 PCI bus. IDSEL pin of USB controller is connected to AD[13] line
47 + * and IDSEL pin of AR125 is connected to AD[16] line.
48 + */
49 +
50 +#include <linux/types.h>
51 +#include <linux/pci.h>
52 +#include <linux/kernel.h>
53 +#include <linux/init.h>
54 +#include <linux/mm.h>
55 +#include <linux/delay.h>
56 +#include <linux/irq.h>
57 +#include <linux/io.h>
58 +#include <asm/paccess.h>
59 +#include <ar231x_platform.h>
60 +#include <ar231x.h>
61 +#include <ar2315_regs.h>
62 +#include "devices.h"
63 +
64 +/* Arbitrary size of memory region to access the configuration space */
65 +#define AR2315_PCI_CFG_SIZE 0x00100000
66 +
67 +#define AR2315_PCI_HOST_SLOT 3
68 +#define AR2315_PCI_HOST_DEVID ((0xff18 << 16) | PCI_VENDOR_ID_ATHEROS)
69 +
70 +static void __iomem *ar2315_pci_cfg_mem;
71 +
72 +static int ar2315_pci_cfg_access(int devfn, int where, int size, u32 *ptr,
73 + bool write)
74 +{
75 + int func = PCI_FUNC(devfn);
76 + int dev = PCI_SLOT(devfn);
77 + u32 addr = (1 << (13 + dev)) | (func << 8) | (where & ~3);
78 + u32 mask = 0xffffffff >> 8 * (4 - size);
79 + u32 sh = (where & 3) * 8;
80 + u32 value, isr;
81 +
82 + /* Prevent access past the remapped area */
83 + if (addr >= AR2315_PCI_CFG_SIZE || dev > 18)
84 + return PCIBIOS_DEVICE_NOT_FOUND;
85 +
86 + /* Clear pending errors */
87 + ar231x_write_reg(AR2315_PCI_ISR, AR2315_PCI_INT_ABORT);
88 + /* Select Configuration access */
89 + ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, 0, AR2315_PCIMISC_CFG_SEL);
90 +
91 + mb(); /* PCI must see space change before we begin */
92 +
93 + value = __raw_readl(ar2315_pci_cfg_mem + addr);
94 +
95 + isr = ar231x_read_reg(AR2315_PCI_ISR);
96 + if (isr & AR2315_PCI_INT_ABORT)
97 + goto exit_err;
98 +
99 + if (write) {
100 + value = (value & ~(mask << sh)) | *ptr << sh;
101 + __raw_writel(value, ar2315_pci_cfg_mem + addr);
102 + isr = ar231x_read_reg(AR2315_PCI_ISR);
103 + if (isr & AR2315_PCI_INT_ABORT)
104 + goto exit_err;
105 + } else {
106 + *ptr = (value >> sh) & mask;
107 + }
108 +
109 + goto exit;
110 +
111 +exit_err:
112 + ar231x_write_reg(AR2315_PCI_ISR, AR2315_PCI_INT_ABORT);
113 + if (!write)
114 + *ptr = 0xffffffff;
115 +
116 +exit:
117 + /* Select Memory access */
118 + ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_CFG_SEL, 0);
119 +
120 + return isr & AR2315_PCI_INT_ABORT ? PCIBIOS_DEVICE_NOT_FOUND :
121 + PCIBIOS_SUCCESSFUL;
122 +}
123 +
124 +static inline int ar2315_pci_local_cfg_rd(unsigned devfn, int where, u32 *val)
125 +{
126 + return ar2315_pci_cfg_access(devfn, where, sizeof(u32), val, false);
127 +}
128 +
129 +static inline int ar2315_pci_local_cfg_wr(unsigned devfn, int where, u32 val)
130 +{
131 + return ar2315_pci_cfg_access(devfn, where, sizeof(u32), &val, true);
132 +}
133 +
134 +static int ar2315_pci_cfg_read(struct pci_bus *bus, unsigned int devfn,
135 + int where, int size, u32 *value)
136 +{
137 + if (PCI_SLOT(devfn) == AR2315_PCI_HOST_SLOT)
138 + return PCIBIOS_DEVICE_NOT_FOUND;
139 +
140 + return ar2315_pci_cfg_access(devfn, where, size, value, 0);
141 +}
142 +
143 +static int ar2315_pci_cfg_write(struct pci_bus *bus, unsigned int devfn,
144 + int where, int size, u32 value)
145 +{
146 + if (PCI_SLOT(devfn) == AR2315_PCI_HOST_SLOT)
147 + return PCIBIOS_DEVICE_NOT_FOUND;
148 +
149 + return ar2315_pci_cfg_access(devfn, where, size, &value, 1);
150 +}
151 +
152 +static struct pci_ops ar2315_pci_ops = {
153 + .read = ar2315_pci_cfg_read,
154 + .write = ar2315_pci_cfg_write,
155 +};
156 +
157 +static struct resource ar2315_mem_resource = {
158 + .name = "ar2315-pci-mem",
159 + .start = AR2315_PCIEXT,
160 + .end = AR2315_PCIEXT + AR2315_PCIEXT_SZ - 1,
161 + .flags = IORESOURCE_MEM,
162 +};
163 +
164 +/* PCI controller does not support I/O ports */
165 +static struct resource ar2315_io_resource = {
166 + .name = "ar2315-pci-io",
167 + .start = 0,
168 + .end = 0,
169 + .flags = IORESOURCE_IO,
170 +};
171 +
172 +static struct pci_controller ar2315_pci_controller = {
173 + .pci_ops = &ar2315_pci_ops,
174 + .mem_resource = &ar2315_mem_resource,
175 + .io_resource = &ar2315_io_resource,
176 + .mem_offset = 0x00000000UL,
177 + .io_offset = 0x00000000UL,
178 +};
179 +
180 +int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
181 +{
182 + return AR2315_PCI_IRQ_EXT;
183 +}
184 +
185 +int pcibios_plat_dev_init(struct pci_dev *dev)
186 +{
187 + return 0;
188 +}
189 +
190 +static int ar2315_pci_host_setup(void)
191 +{
192 + unsigned devfn = PCI_DEVFN(AR2315_PCI_HOST_SLOT, 0);
193 + int res;
194 + u32 id;
195 +
196 + res = ar2315_pci_local_cfg_rd(devfn, PCI_VENDOR_ID, &id);
197 + if (res != PCIBIOS_SUCCESSFUL || id != AR2315_PCI_HOST_DEVID)
198 + return -ENODEV;
199 +
200 + /* Program MBARs */
201 + ar2315_pci_local_cfg_wr(devfn, PCI_BASE_ADDRESS_0, HOST_PCI_MBAR0);
202 + ar2315_pci_local_cfg_wr(devfn, PCI_BASE_ADDRESS_1, HOST_PCI_MBAR1);
203 + ar2315_pci_local_cfg_wr(devfn, PCI_BASE_ADDRESS_2, HOST_PCI_MBAR2);
204 +
205 + /* Run */
206 + ar2315_pci_local_cfg_wr(devfn, PCI_COMMAND, PCI_COMMAND_MEMORY |
207 + PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL |
208 + PCI_COMMAND_INVALIDATE | PCI_COMMAND_PARITY |
209 + PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK);
210 +
211 + return 0;
212 +}
213 +
214 +static void ar2315_pci_irq_handler(unsigned irq, struct irq_desc *desc)
215 +{
216 + u32 pending = ar231x_read_reg(AR2315_PCI_ISR) &
217 + ar231x_read_reg(AR2315_PCI_IMR);
218 +
219 + if (pending & AR2315_PCI_INT_EXT)
220 + generic_handle_irq(AR2315_PCI_IRQ_EXT);
221 + else if (pending & AR2315_PCI_INT_ABORT)
222 + generic_handle_irq(AR2315_PCI_IRQ_ABORT);
223 + else
224 + spurious_interrupt();
225 +}
226 +
227 +static void ar2315_pci_irq_mask(struct irq_data *d)
228 +{
229 + u32 m = 1 << (d->irq - AR2315_PCI_IRQ_BASE + AR2315_PCI_IRQ_SHIFT);
230 +
231 + ar231x_mask_reg(AR2315_PCI_IMR, m, 0);
232 +}
233 +
234 +static void ar2315_pci_irq_mask_ack(struct irq_data *d)
235 +{
236 + u32 m = 1 << (d->irq - AR2315_PCI_IRQ_BASE + AR2315_PCI_IRQ_SHIFT);
237 +
238 + ar231x_mask_reg(AR2315_PCI_IMR, m, 0);
239 + ar231x_write_reg(AR2315_PCI_ISR, m);
240 +}
241 +
242 +static void ar2315_pci_irq_unmask(struct irq_data *d)
243 +{
244 + u32 m = 1 << (d->irq - AR2315_PCI_IRQ_BASE + AR2315_PCI_IRQ_SHIFT);
245 +
246 + ar231x_mask_reg(AR2315_PCI_IMR, 0, m);
247 +}
248 +
249 +static struct irq_chip ar2315_pci_irq_chip = {
250 + .name = "AR2315-PCI",
251 + .irq_mask = ar2315_pci_irq_mask,
252 + .irq_mask_ack = ar2315_pci_irq_mask_ack,
253 + .irq_unmask = ar2315_pci_irq_unmask,
254 +};
255 +
256 +static void ar2315_pci_irq_init(void)
257 +{
258 + int i;
259 +
260 + ar231x_mask_reg(AR2315_PCI_IER, AR2315_PCI_IER_ENABLE, 0);
261 + ar231x_mask_reg(AR2315_PCI_IMR, (AR2315_PCI_INT_ABORT |
262 + AR2315_PCI_INT_EXT), 0);
263 +
264 + for (i = 0; i < AR2315_PCI_IRQ_COUNT; ++i) {
265 + int irq = AR2315_PCI_IRQ_BASE + i;
266 +
267 + irq_set_chip_and_handler(irq, &ar2315_pci_irq_chip,
268 + handle_level_irq);
269 + }
270 +
271 + irq_set_chained_handler(AR2315_IRQ_LCBUS_PCI, ar2315_pci_irq_handler);
272 +
273 + /* Clear any pending Abort or external Interrupts
274 + * and enable interrupt processing */
275 + ar231x_write_reg(AR2315_PCI_ISR, (AR2315_PCI_INT_ABORT |
276 + AR2315_PCI_INT_EXT));
277 + ar231x_mask_reg(AR2315_PCI_IER, 0, AR2315_PCI_IER_ENABLE);
278 +}
279 +
280 +static int __init
281 +ar2315_pci_init(void)
282 +{
283 + u32 reg;
284 + int res;
285 +
286 + if (ar231x_devtype != DEV_TYPE_AR2315)
287 + return -ENODEV;
288 +
289 + /* Remap PCI config space */
290 + ar2315_pci_cfg_mem = ioremap_nocache(AR2315_PCIEXT,
291 + AR2315_PCI_CFG_SIZE);
292 + if (!ar2315_pci_cfg_mem) {
293 + pr_err("ar2315-pci: failed to remap PCI config space\n");
294 + return -ENOMEM;
295 + }
296 +
297 + /* Reset PCI DMA logic */
298 + reg = ar231x_mask_reg(AR2315_RESET, 0, AR2315_RESET_PCIDMA);
299 + msleep(20);
300 + reg &= ~AR2315_RESET_PCIDMA;
301 + ar231x_write_reg(AR2315_RESET, reg);
302 + msleep(20);
303 +
304 + ar231x_mask_reg(AR2315_ENDIAN_CTL, 0,
305 + AR2315_CONFIG_PCIAHB | AR2315_CONFIG_PCIAHB_BRIDGE);
306 +
307 + ar231x_write_reg(AR2315_PCICLK, AR2315_PCICLK_PLLC_CLKM |
308 + (AR2315_PCICLK_IN_FREQ_DIV_6 << AR2315_PCICLK_DIV_S));
309 + ar231x_mask_reg(AR2315_AHB_ARB_CTL, 0, AR2315_ARB_PCI);
310 + ar231x_mask_reg(AR2315_IF_CTL, AR2315_IF_PCI_CLK_MASK | AR2315_IF_MASK,
311 + AR2315_IF_PCI | AR2315_IF_PCI_HOST |
312 + AR2315_IF_PCI_INTR | (AR2315_IF_PCI_CLK_OUTPUT_CLK <<
313 + AR2315_IF_PCI_CLK_SHIFT));
314 +
315 + /* Reset the PCI bus by setting bits 5-4 in PCI_MCFG */
316 + ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_RST_MODE,
317 + AR2315_PCIRST_LOW);
318 + msleep(100);
319 +
320 + /* Bring the PCI out of reset */
321 + ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_RST_MODE,
322 + AR2315_PCIRST_HIGH | AR2315_PCICACHE_DIS | 0x8);
323 +
324 + ar231x_write_reg(AR2315_PCI_UNCACHE_CFG,
325 + 0x1E | /* 1GB uncached */
326 + (1 << 5) | /* Enable uncached */
327 + (0x2 << 30) /* Base: 0x80000000 */);
328 + ar231x_read_reg(AR2315_PCI_UNCACHE_CFG);
329 +
330 + msleep(500);
331 +
332 + res = ar2315_pci_host_setup();
333 + if (res)
334 + goto error;
335 +
336 + ar2315_pci_irq_init();
337 +
338 + register_pci_controller(&ar2315_pci_controller);
339 +
340 + return 0;
341 +
342 +error:
343 + iounmap(ar2315_pci_cfg_mem);
344 + return res;
345 +}
346 +
347 +arch_initcall(ar2315_pci_init);
348 --- a/arch/mips/ar231x/Kconfig
349 +++ b/arch/mips/ar231x/Kconfig
350 @@ -7,3 +7,10 @@ config ATHEROS_AR2315
351 bool "Atheros 2315+ support"
352 depends on ATHEROS_AR231X
353 default y
354 +
355 +config ATHEROS_AR2315_PCI
356 + bool "PCI support"
357 + depends on ATHEROS_AR2315
358 + select HW_HAS_PCI
359 + select PCI
360 + default y
361 --- a/arch/mips/ar231x/ar2315.c
362 +++ b/arch/mips/ar231x/ar2315.c
363 @@ -104,6 +104,10 @@ ar2315_irq_dispatch(void)
364 do_IRQ(AR2315_IRQ_WLAN0_INTRS);
365 else if (pending & CAUSEF_IP4)
366 do_IRQ(AR2315_IRQ_ENET0_INTRS);
367 +#ifdef CONFIG_ATHEROS_AR2315_PCI
368 + else if (pending & CAUSEF_IP5)
369 + do_IRQ(AR2315_IRQ_LCBUS_PCI);
370 +#endif
371 else if (pending & CAUSEF_IP2)
372 do_IRQ(AR2315_IRQ_MISC_INTRS);
373 else if (pending & CAUSEF_IP7)
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