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1 /*

2 * VFIO PCI config space virtualization

3 *

5 * Author: Alex Williamson <alex.williamson@redhat.com>

6 *

7 * This program is free software; you can redistribute it and/or modify

8 * it under the terms of the GNU General Public License version 2 as

9 * published by the Free Software Foundation.

10 *

11 * Derived from original vfio:

13 * Author: Tom Lyon, pugs@cisco.com

14 */

16 /*

17 * This code handles reading and writing of PCI configuration registers.

18 * This is hairy because we want to allow a lot of flexibility to the

19 * user driver, but cannot trust it with all of the config fields.

20 * Tables determine which fields can be read and written, as well as

21 * which fields are 'virtualized' - special actions and translations to

22 * make it appear to the user that he has control, when in fact things

23 * must be negotiated with the underlying OS.

24 */

26 #include <linux/fs.h>

27 #include <linux/pci.h>

28 #include <linux/uaccess.h>

29 #include <linux/vfio.h>

31 #include "vfio_pci_private.h"

33 #define PCI_CFG_SPACE_SIZE 256

35 /* Useful "pseudo" capabilities */

36 #define PCI_CAP_ID_BASIC 0

37 #define PCI_CAP_ID_INVALID 0xFF

39 #define is_bar(offset) \

40 ((offset >= PCI_BASE_ADDRESS_0 && offset < PCI_BASE_ADDRESS_5 + 4) || \

41 (offset >= PCI_ROM_ADDRESS && offset < PCI_ROM_ADDRESS + 4))

43 /*

44 * Lengths of PCI Config Capabilities

45 * 0: Removed from the user visible capability list

46 * FF: Variable length

47 */

48 static u8 pci_cap_length[] = {

49 [PCI_CAP_ID_BASIC] = PCI_STD_HEADER_SIZEOF, /* pci config header */

50 [PCI_CAP_ID_PM] = PCI_PM_SIZEOF,

51 [PCI_CAP_ID_AGP] = PCI_AGP_SIZEOF,

52 [PCI_CAP_ID_VPD] = PCI_CAP_VPD_SIZEOF,

53 [PCI_CAP_ID_SLOTID] = 0, /* bridge - don't care */

54 [PCI_CAP_ID_MSI] = 0xFF, /* 10, 14, 20, or 24 */

55 [PCI_CAP_ID_CHSWP] = 0, /* cpci - not yet */

56 [PCI_CAP_ID_PCIX] = 0xFF, /* 8 or 24 */

57 [PCI_CAP_ID_HT] = 0xFF, /* hypertransport */

58 [PCI_CAP_ID_VNDR] = 0xFF, /* variable */

59 [PCI_CAP_ID_DBG] = 0, /* debug - don't care */

60 [PCI_CAP_ID_CCRC] = 0, /* cpci - not yet */

61 [PCI_CAP_ID_SHPC] = 0, /* hotswap - not yet */

62 [PCI_CAP_ID_SSVID] = 0, /* bridge - don't care */

63 [PCI_CAP_ID_AGP3] = 0, /* AGP8x - not yet */

64 [PCI_CAP_ID_SECDEV] = 0, /* secure device not yet */

65 [PCI_CAP_ID_EXP] = 0xFF, /* 20 or 44 */

66 [PCI_CAP_ID_MSIX] = PCI_CAP_MSIX_SIZEOF,

67 [PCI_CAP_ID_SATA] = 0xFF,

68 [PCI_CAP_ID_AF] = PCI_CAP_AF_SIZEOF,

69 };

71 /*

72 * Lengths of PCIe/PCI-X Extended Config Capabilities

73 * 0: Removed or masked from the user visible capabilty list

74 * FF: Variable length

75 */

76 static u16 pci_ext_cap_length[] = {

77 [PCI_EXT_CAP_ID_ERR] = PCI_ERR_ROOT_COMMAND,

78 [PCI_EXT_CAP_ID_VC] = 0xFF,

79 [PCI_EXT_CAP_ID_DSN] = PCI_EXT_CAP_DSN_SIZEOF,

80 [PCI_EXT_CAP_ID_PWR] = PCI_EXT_CAP_PWR_SIZEOF,

81 [PCI_EXT_CAP_ID_RCLD] = 0, /* root only - don't care */

82 [PCI_EXT_CAP_ID_RCILC] = 0, /* root only - don't care */

83 [PCI_EXT_CAP_ID_RCEC] = 0, /* root only - don't care */

84 [PCI_EXT_CAP_ID_MFVC] = 0xFF,

85 [PCI_EXT_CAP_ID_VC9] = 0xFF, /* same as CAP_ID_VC */

86 [PCI_EXT_CAP_ID_RCRB] = 0, /* root only - don't care */

87 [PCI_EXT_CAP_ID_VNDR] = 0xFF,

88 [PCI_EXT_CAP_ID_CAC] = 0, /* obsolete */

89 [PCI_EXT_CAP_ID_ACS] = 0xFF,

90 [PCI_EXT_CAP_ID_ARI] = PCI_EXT_CAP_ARI_SIZEOF,

91 [PCI_EXT_CAP_ID_ATS] = PCI_EXT_CAP_ATS_SIZEOF,

92 [PCI_EXT_CAP_ID_SRIOV] = PCI_EXT_CAP_SRIOV_SIZEOF,

93 [PCI_EXT_CAP_ID_MRIOV] = 0, /* not yet */

94 [PCI_EXT_CAP_ID_MCAST] = PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF,

95 [PCI_EXT_CAP_ID_PRI] = PCI_EXT_CAP_PRI_SIZEOF,

96 [PCI_EXT_CAP_ID_AMD_XXX] = 0, /* not yet */

97 [PCI_EXT_CAP_ID_REBAR] = 0xFF,

98 [PCI_EXT_CAP_ID_DPA] = 0xFF,

99 [PCI_EXT_CAP_ID_TPH] = 0xFF,

100 [PCI_EXT_CAP_ID_LTR] = PCI_EXT_CAP_LTR_SIZEOF,

101 [PCI_EXT_CAP_ID_SECPCI] = 0, /* not yet */

102 [PCI_EXT_CAP_ID_PMUX] = 0, /* not yet */

103 [PCI_EXT_CAP_ID_PASID] = 0, /* not yet */

104 };

105

106 /*

107 * Read/Write Permission Bits - one bit for each bit in capability

108 * Any field can be read if it exists, but what is read depends on

109 * whether the field is 'virtualized', or just pass thru to the

110 * hardware. Any virtualized field is also virtualized for writes.

111 * Writes are only permitted if they have a 1 bit here.

112 */

113 struct perm_bits {

114 u8 *virt; /* read/write virtual data, not hw */

115 u8 *write; /* writeable bits */

116 int (*readfn)(struct vfio_pci_device *vdev, int pos, int count,

117 struct perm_bits *perm, int offset, __le32 *val);

118 int (*writefn)(struct vfio_pci_device *vdev, int pos, int count,

119 struct perm_bits *perm, int offset, __le32 val);

120 };

121

122 #define NO_VIRT 0

123 #define ALL_VIRT 0xFFFFFFFFU

124 #define NO_WRITE 0

125 #define ALL_WRITE 0xFFFFFFFFU

126

127 static int vfio_user_config_read(struct pci_dev *pdev, int offset,

128 __le32 *val, int count)

129 {

130 int ret = -EINVAL;

131 u32 tmp_val = 0;

132

133 switch (count) {

134 case 1:

135 {

136 u8 tmp;

137 ret = pci_user_read_config_byte(pdev, offset, &tmp);

138 tmp_val = tmp;

139 break;

140 }

141 case 2:

142 {

143 u16 tmp;

144 ret = pci_user_read_config_word(pdev, offset, &tmp);

145 tmp_val = tmp;

146 break;

147 }

148 case 4:

149 ret = pci_user_read_config_dword(pdev, offset, &tmp_val);

150 break;

151 }

152

153 *val = cpu_to_le32(tmp_val);

154

155 return pcibios_err_to_errno(ret);

156 }

157

158 static int vfio_user_config_write(struct pci_dev *pdev, int offset,

159 __le32 val, int count)

160 {

161 int ret = -EINVAL;

162 u32 tmp_val = le32_to_cpu(val);

163

164 switch (count) {

165 case 1:

166 ret = pci_user_write_config_byte(pdev, offset, tmp_val);

167 break;

168 case 2:

169 ret = pci_user_write_config_word(pdev, offset, tmp_val);

170 break;

171 case 4:

172 ret = pci_user_write_config_dword(pdev, offset, tmp_val);

173 break;

174 }

175

176 return pcibios_err_to_errno(ret);

177 }

178

179 static int vfio_default_config_read(struct vfio_pci_device *vdev, int pos,

180 int count, struct perm_bits *perm,

181 int offset, __le32 *val)

182 {

183 __le32 virt = 0;

184

185 memcpy(val, vdev->vconfig + pos, count);

186

187 memcpy(&virt, perm->virt + offset, count);

188

189 /* Any non-virtualized bits? */

190 if (cpu_to_le32(~0U >> (32 - (count * 8))) != virt) {

191 struct pci_dev *pdev = vdev->pdev;

192 __le32 phys_val = 0;

193 int ret;

194

195 ret = vfio_user_config_read(pdev, pos, &phys_val, count);

196 if (ret)

197 return ret;

198

199 *val = (phys_val & ~virt) | (*val & virt);

200 }

201

202 return count;

203 }

204

205 static int vfio_default_config_write(struct vfio_pci_device *vdev, int pos,

206 int count, struct perm_bits *perm,

207 int offset, __le32 val)

208 {

209 __le32 virt = 0, write = 0;

210

211 memcpy(&write, perm->write + offset, count);

212

213 if (!write)

214 return count; /* drop, no writable bits */

215

216 memcpy(&virt, perm->virt + offset, count);

217

218 /* Virtualized and writable bits go to vconfig */

219 if (write & virt) {

220 __le32 virt_val = 0;

221

222 memcpy(&virt_val, vdev->vconfig + pos, count);

223

224 virt_val &= ~(write & virt);

225 virt_val |= (val & (write & virt));

226

227 memcpy(vdev->vconfig + pos, &virt_val, count);

228 }

229

230 /* Non-virtualzed and writable bits go to hardware */

231 if (write & ~virt) {

232 struct pci_dev *pdev = vdev->pdev;

233 __le32 phys_val = 0;

234 int ret;

235

236 ret = vfio_user_config_read(pdev, pos, &phys_val, count);

237 if (ret)

238 return ret;

239

240 phys_val &= ~(write & ~virt);

241 phys_val |= (val & (write & ~virt));

242

243 ret = vfio_user_config_write(pdev, pos, phys_val, count);

244 if (ret)

245 return ret;

246 }

247

248 return count;

249 }

250

251 /* Allow direct read from hardware, except for capability next pointer */

252 static int vfio_direct_config_read(struct vfio_pci_device *vdev, int pos,

253 int count, struct perm_bits *perm,

254 int offset, __le32 *val)

255 {

256 int ret;

257

258 ret = vfio_user_config_read(vdev->pdev, pos, val, count);

259 if (ret)

260 return pcibios_err_to_errno(ret);

261

262 if (pos >= PCI_CFG_SPACE_SIZE) { /* Extended cap header mangling */

263 if (offset < 4)

264 memcpy(val, vdev->vconfig + pos, count);

265 } else if (pos >= PCI_STD_HEADER_SIZEOF) { /* Std cap mangling */

266 if (offset == PCI_CAP_LIST_ID && count > 1)

267 memcpy(val, vdev->vconfig + pos,

268 min(PCI_CAP_FLAGS, count));

269 else if (offset == PCI_CAP_LIST_NEXT)

270 memcpy(val, vdev->vconfig + pos, 1);

271 }

272

273 return count;

274 }

275

276 /* Raw access skips any kind of virtualization */

277 static int vfio_raw_config_write(struct vfio_pci_device *vdev, int pos,

278 int count, struct perm_bits *perm,

279 int offset, __le32 val)

280 {

281 int ret;

282

283 ret = vfio_user_config_write(vdev->pdev, pos, val, count);

284 if (ret)

285 return ret;

286

287 return count;

288 }

289

290 static int vfio_raw_config_read(struct vfio_pci_device *vdev, int pos,

291 int count, struct perm_bits *perm,

292 int offset, __le32 *val)

293 {

294 int ret;

295

296 ret = vfio_user_config_read(vdev->pdev, pos, val, count);

297 if (ret)

298 return pcibios_err_to_errno(ret);

299

300 return count;

301 }

302

303 /* Default capability regions to read-only, no-virtualization */

304 static struct perm_bits cap_perms[PCI_CAP_ID_MAX + 1] = {

305 [0 ... PCI_CAP_ID_MAX] = { .readfn = vfio_direct_config_read }

306 };

307 static struct perm_bits ecap_perms[PCI_EXT_CAP_ID_MAX + 1] = {

308 [0 ... PCI_EXT_CAP_ID_MAX] = { .readfn = vfio_direct_config_read }

309 };

310 /*

311 * Default unassigned regions to raw read-write access. Some devices

312 * require this to function as they hide registers between the gaps in

313 * config space (be2net). Like MMIO and I/O port registers, we have

314 * to trust the hardware isolation.

315 */

316 static struct perm_bits unassigned_perms = {

317 .readfn = vfio_raw_config_read,

318 .writefn = vfio_raw_config_write

319 };

320

321 static void free_perm_bits(struct perm_bits *perm)

322 {

323 kfree(perm->virt);

324 kfree(perm->write);

325 perm->virt = NULL;

326 perm->write = NULL;

327 }

328

329 static int alloc_perm_bits(struct perm_bits *perm, int size)

330 {

331 /*

332 * Round up all permission bits to the next dword, this lets us

333 * ignore whether a read/write exceeds the defined capability

334 * structure. We can do this because:

335 * - Standard config space is already dword aligned

336 * - Capabilities are all dword alinged (bits 0:1 of next reserved)

337 * - Express capabilities defined as dword aligned

338 */

339 size = round_up(size, 4);

340

341 /*

342 * Zero state is

343 * - All Readable, None Writeable, None Virtualized

344 */

345 perm->virt = kzalloc(size, GFP_KERNEL);

346 perm->write = kzalloc(size, GFP_KERNEL);

347 if (!perm->virt || !perm->write) {

348 free_perm_bits(perm);

349 return -ENOMEM;

350 }

351

352 perm->readfn = vfio_default_config_read;

353 perm->writefn = vfio_default_config_write;

354

355 return 0;

356 }

357

358 /*

359 * Helper functions for filling in permission tables

360 */

361 static inline void p_setb(struct perm_bits *p, int off, u8 virt, u8 write)

362 {

363 p->virt[off] = virt;

364 p->write[off] = write;

365 }

366

367 /* Handle endian-ness - pci and tables are little-endian */

368 static inline void p_setw(struct perm_bits *p, int off, u16 virt, u16 write)

369 {

370 *(__le16 *)(&p->virt[off]) = cpu_to_le16(virt);

371 *(__le16 *)(&p->write[off]) = cpu_to_le16(write);

372 }

373

374 /* Handle endian-ness - pci and tables are little-endian */

375 static inline void p_setd(struct perm_bits *p, int off, u32 virt, u32 write)

376 {

377 *(__le32 *)(&p->virt[off]) = cpu_to_le32(virt);

378 *(__le32 *)(&p->write[off]) = cpu_to_le32(write);

379 }

380

381 /*

382 * Restore the *real* BARs after we detect a FLR or backdoor reset.

383 * (backdoor = some device specific technique that we didn't catch)

384 */

385 static void vfio_bar_restore(struct vfio_pci_device *vdev)

386 {

387 struct pci_dev *pdev = vdev->pdev;

388 u32 *rbar = vdev->rbar;

389 int i;

390

391 if (pdev->is_virtfn)

392 return;

393

394 pr_info("%s: %s reset recovery - restoring bars\n",

395 __func__, dev_name(&pdev->dev));

396

397 for (i = PCI_BASE_ADDRESS_0; i <= PCI_BASE_ADDRESS_5; i += 4, rbar++)

398 pci_user_write_config_dword(pdev, i, *rbar);

399

400 pci_user_write_config_dword(pdev, PCI_ROM_ADDRESS, *rbar);

401 }

402

403 static __le32 vfio_generate_bar_flags(struct pci_dev *pdev, int bar)

404 {

405 unsigned long flags = pci_resource_flags(pdev, bar);

406 u32 val;

407

408 if (flags & IORESOURCE_IO)

409 return cpu_to_le32(PCI_BASE_ADDRESS_SPACE_IO);

410

411 val = PCI_BASE_ADDRESS_SPACE_MEMORY;

412

413 if (flags & IORESOURCE_PREFETCH)

414 val |= PCI_BASE_ADDRESS_MEM_PREFETCH;

415

416 if (flags & IORESOURCE_MEM_64)

417 val |= PCI_BASE_ADDRESS_MEM_TYPE_64;

418

419 return cpu_to_le32(val);

420 }

421

422 /*

423 * Pretend we're hardware and tweak the values of the *virtual* PCI BARs

424 * to reflect the hardware capabilities. This implements BAR sizing.

425 */

426 static void vfio_bar_fixup(struct vfio_pci_device *vdev)

427 {

428 struct pci_dev *pdev = vdev->pdev;

429 int i;

430 __le32 *bar;

431 u64 mask;

432

433 bar = (__le32 *)&vdev->vconfig[PCI_BASE_ADDRESS_0];

434

435 for (i = PCI_STD_RESOURCES; i <= PCI_STD_RESOURCE_END; i++, bar++) {

436 if (!pci_resource_start(pdev, i)) {

437 *bar = 0; /* Unmapped by host = unimplemented to user */

438 continue;

439 }

440

441 mask = ~(pci_resource_len(pdev, i) - 1);

442

443 *bar &= cpu_to_le32((u32)mask);

444 *bar |= vfio_generate_bar_flags(pdev, i);

445

446 if (*bar & cpu_to_le32(PCI_BASE_ADDRESS_MEM_TYPE_64)) {

447 bar++;

448 *bar &= cpu_to_le32((u32)(mask >> 32));

449 i++;

450 }

451 }

452

453 bar = (__le32 *)&vdev->vconfig[PCI_ROM_ADDRESS];

454

455 /*

456 * NB. we expose the actual BAR size here, regardless of whether

457 * we can read it. When we report the REGION_INFO for the ROM

458 * we report what PCI tells us is the actual ROM size.

459 */

460 if (pci_resource_start(pdev, PCI_ROM_RESOURCE)) {

461 mask = ~(pci_resource_len(pdev, PCI_ROM_RESOURCE) - 1);

462 mask |= PCI_ROM_ADDRESS_ENABLE;

463 *bar &= cpu_to_le32((u32)mask);

464 } else

465 *bar = 0;

466

467 vdev->bardirty = false;

468 }

469

470 static int vfio_basic_config_read(struct vfio_pci_device *vdev, int pos,

471 int count, struct perm_bits *perm,

472 int offset, __le32 *val)

473 {

474 if (is_bar(offset)) /* pos == offset for basic config */

475 vfio_bar_fixup(vdev);

476

477 count = vfio_default_config_read(vdev, pos, count, perm, offset, val);

478

479 /* Mask in virtual memory enable for SR-IOV devices */

480 if (offset == PCI_COMMAND && vdev->pdev->is_virtfn) {

481 u16 cmd = le16_to_cpu(*(__le16 *)&vdev->vconfig[PCI_COMMAND]);

482 u32 tmp_val = le32_to_cpu(*val);

483

484 tmp_val |= cmd & PCI_COMMAND_MEMORY;

485 *val = cpu_to_le32(tmp_val);

486 }

487

488 return count;

489 }

490

491 static int vfio_basic_config_write(struct vfio_pci_device *vdev, int pos,

492 int count, struct perm_bits *perm,

493 int offset, __le32 val)

494 {

495 struct pci_dev *pdev = vdev->pdev;

496 __le16 *virt_cmd;

497 u16 new_cmd = 0;

498 int ret;

499

500 virt_cmd = (__le16 *)&vdev->vconfig[PCI_COMMAND];

501

502 if (offset == PCI_COMMAND) {

503 bool phys_mem, virt_mem, new_mem, phys_io, virt_io, new_io;

504 u16 phys_cmd;

505

506 ret = pci_user_read_config_word(pdev, PCI_COMMAND, &phys_cmd);

507 if (ret)

508 return ret;

509

510 new_cmd = le32_to_cpu(val);

511

512 phys_mem = !!(phys_cmd & PCI_COMMAND_MEMORY);

513 virt_mem = !!(le16_to_cpu(*virt_cmd) & PCI_COMMAND_MEMORY);

514 new_mem = !!(new_cmd & PCI_COMMAND_MEMORY);

515

516 phys_io = !!(phys_cmd & PCI_COMMAND_IO);

517 virt_io = !!(le16_to_cpu(*virt_cmd) & PCI_COMMAND_IO);

518 new_io = !!(new_cmd & PCI_COMMAND_IO);

519

520 /*

521 * If the user is writing mem/io enable (new_mem/io) and we

522 * think it's already enabled (virt_mem/io), but the hardware

523 * shows it disabled (phys_mem/io, then the device has

524 * undergone some kind of backdoor reset and needs to be

525 * restored before we allow it to enable the bars.

526 * SR-IOV devices will trigger this, but we catch them later

527 */

528 if ((new_mem && virt_mem && !phys_mem) ||

529 (new_io && virt_io && !phys_io))

530 vfio_bar_restore(vdev);

531 }

532

533 count = vfio_default_config_write(vdev, pos, count, perm, offset, val);

534 if (count < 0)

535 return count;

536

537 /*

538 * Save current memory/io enable bits in vconfig to allow for

539 * the test above next time.

540 */

541 if (offset == PCI_COMMAND) {

542 u16 mask = PCI_COMMAND_MEMORY | PCI_COMMAND_IO;

543

544 *virt_cmd &= cpu_to_le16(~mask);

545 *virt_cmd |= cpu_to_le16(new_cmd & mask);

546 }

547

548 /* Emulate INTx disable */

549 if (offset >= PCI_COMMAND && offset <= PCI_COMMAND + 1) {

550 bool virt_intx_disable;

551

552 virt_intx_disable = !!(le16_to_cpu(*virt_cmd) &

553 PCI_COMMAND_INTX_DISABLE);

554

555 if (virt_intx_disable && !vdev->virq_disabled) {

556 vdev->virq_disabled = true;

557 vfio_pci_intx_mask(vdev);

558 } else if (!virt_intx_disable && vdev->virq_disabled) {

559 vdev->virq_disabled = false;

560 vfio_pci_intx_unmask(vdev);

561 }

562 }

563

564 if (is_bar(offset))

565 vdev->bardirty = true;

566

567 return count;

568 }

569

570 /* Permissions for the Basic PCI Header */

571 static int __init init_pci_cap_basic_perm(struct perm_bits *perm)

572 {

573 if (alloc_perm_bits(perm, PCI_STD_HEADER_SIZEOF))

574 return -ENOMEM;

575

576 perm->readfn = vfio_basic_config_read;

577 perm->writefn = vfio_basic_config_write;

578

579 /* Virtualized for SR-IOV functions, which just have FFFF */

580 p_setw(perm, PCI_VENDOR_ID, (u16)ALL_VIRT, NO_WRITE);

581 p_setw(perm, PCI_DEVICE_ID, (u16)ALL_VIRT, NO_WRITE);

582

583 /*

584 * Virtualize INTx disable, we use it internally for interrupt

585 * control and can emulate it for non-PCI 2.3 devices.

586 */

587 p_setw(perm, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE, (u16)ALL_WRITE);

588

589 /* Virtualize capability list, we might want to skip/disable */

590 p_setw(perm, PCI_STATUS, PCI_STATUS_CAP_LIST, NO_WRITE);

591

592 /* No harm to write */

593 p_setb(perm, PCI_CACHE_LINE_SIZE, NO_VIRT, (u8)ALL_WRITE);

594 p_setb(perm, PCI_LATENCY_TIMER, NO_VIRT, (u8)ALL_WRITE);

595 p_setb(perm, PCI_BIST, NO_VIRT, (u8)ALL_WRITE);

596

597 /* Virtualize all bars, can't touch the real ones */

598 p_setd(perm, PCI_BASE_ADDRESS_0, ALL_VIRT, ALL_WRITE);

599 p_setd(perm, PCI_BASE_ADDRESS_1, ALL_VIRT, ALL_WRITE);

600 p_setd(perm, PCI_BASE_ADDRESS_2, ALL_VIRT, ALL_WRITE);

601 p_setd(perm, PCI_BASE_ADDRESS_3, ALL_VIRT, ALL_WRITE);

602 p_setd(perm, PCI_BASE_ADDRESS_4, ALL_VIRT, ALL_WRITE);

603 p_setd(perm, PCI_BASE_ADDRESS_5, ALL_VIRT, ALL_WRITE);

604 p_setd(perm, PCI_ROM_ADDRESS, ALL_VIRT, ALL_WRITE);

605

606 /* Allow us to adjust capability chain */

607 p_setb(perm, PCI_CAPABILITY_LIST, (u8)ALL_VIRT, NO_WRITE);

608

609 /* Sometimes used by sw, just virtualize */

610 p_setb(perm, PCI_INTERRUPT_LINE, (u8)ALL_VIRT, (u8)ALL_WRITE);

611 return 0;

612 }

613

614 static int vfio_pm_config_write(struct vfio_pci_device *vdev, int pos,

615 int count, struct perm_bits *perm,

616 int offset, __le32 val)

617 {

618 count = vfio_default_config_write(vdev, pos, count, perm, offset, val);

619 if (count < 0)

620 return count;

621

622 if (offset == PCI_PM_CTRL) {

623 pci_power_t state;

624

625 switch (le32_to_cpu(val) & PCI_PM_CTRL_STATE_MASK) {

626 case 0:

627 state = PCI_D0;

628 break;

629 case 1:

630 state = PCI_D1;

631 break;

632 case 2:

633 state = PCI_D2;

634 break;

635 case 3:

636 state = PCI_D3hot;

637 break;

638 }

639

640 pci_set_power_state(vdev->pdev, state);

641 }

642

643 return count;

644 }

645

646 /* Permissions for the Power Management capability */

647 static int __init init_pci_cap_pm_perm(struct perm_bits *perm)

648 {

649 if (alloc_perm_bits(perm, pci_cap_length[PCI_CAP_ID_PM]))

650 return -ENOMEM;

651

652 perm->writefn = vfio_pm_config_write;

653

654 /*

655 * We always virtualize the next field so we can remove

656 * capabilities from the chain if we want to.

657 */

658 p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE);

659

660 /*

661 * Power management is defined *per function*, so we can let

662 * the user change power state, but we trap and initiate the

663 * change ourselves, so the state bits are read-only.

664 */

665 p_setd(perm, PCI_PM_CTRL, NO_VIRT, ~PCI_PM_CTRL_STATE_MASK);

666 return 0;

667 }

668

669 /* Permissions for PCI-X capability */

670 static int __init init_pci_cap_pcix_perm(struct perm_bits *perm)

671 {

672 /* Alloc 24, but only 8 are used in v0 */

673 if (alloc_perm_bits(perm, PCI_CAP_PCIX_SIZEOF_V2))

674 return -ENOMEM;

675

676 p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE);

677

678 p_setw(perm, PCI_X_CMD, NO_VIRT, (u16)ALL_WRITE);

679 p_setd(perm, PCI_X_ECC_CSR, NO_VIRT, ALL_WRITE);

680 return 0;

681 }

682

683 /* Permissions for PCI Express capability */

684 static int __init init_pci_cap_exp_perm(struct perm_bits *perm)

685 {

686 /* Alloc larger of two possible sizes */

687 if (alloc_perm_bits(perm, PCI_CAP_EXP_ENDPOINT_SIZEOF_V2))

688 return -ENOMEM;

689

690 p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE);

691

692 /*

693 * Allow writes to device control fields (includes FLR!)

694 * but not to devctl_phantom which could confuse IOMMU

695 * or to the ARI bit in devctl2 which is set at probe time

696 */

697 p_setw(perm, PCI_EXP_DEVCTL, NO_VIRT, ~PCI_EXP_DEVCTL_PHANTOM);

698 p_setw(perm, PCI_EXP_DEVCTL2, NO_VIRT, ~PCI_EXP_DEVCTL2_ARI);

699 return 0;

700 }

701

702 /* Permissions for Advanced Function capability */

703 static int __init init_pci_cap_af_perm(struct perm_bits *perm)

704 {

705 if (alloc_perm_bits(perm, pci_cap_length[PCI_CAP_ID_AF]))

706 return -ENOMEM;

707

708 p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE);

709 p_setb(perm, PCI_AF_CTRL, NO_VIRT, PCI_AF_CTRL_FLR);

710 return 0;

711 }

712

713 /* Permissions for Advanced Error Reporting extended capability */

714 static int __init init_pci_ext_cap_err_perm(struct perm_bits *perm)

715 {

716 u32 mask;

717

718 if (alloc_perm_bits(perm, pci_ext_cap_length[PCI_EXT_CAP_ID_ERR]))

719 return -ENOMEM;

720

721 /*

722 * Virtualize the first dword of all express capabilities

723 * because it includes the next pointer. This lets us later

724 * remove capabilities from the chain if we need to.

725 */

726 p_setd(perm, 0, ALL_VIRT, NO_WRITE);

727

728 /* Writable bits mask */

729 mask = PCI_ERR_UNC_TRAIN | /* Training */

730 PCI_ERR_UNC_DLP | /* Data Link Protocol */

731 PCI_ERR_UNC_SURPDN | /* Surprise Down */

732 PCI_ERR_UNC_POISON_TLP | /* Poisoned TLP */

733 PCI_ERR_UNC_FCP | /* Flow Control Protocol */

734 PCI_ERR_UNC_COMP_TIME | /* Completion Timeout */

735 PCI_ERR_UNC_COMP_ABORT | /* Completer Abort */

736 PCI_ERR_UNC_UNX_COMP | /* Unexpected Completion */

737 PCI_ERR_UNC_RX_OVER | /* Receiver Overflow */

738 PCI_ERR_UNC_MALF_TLP | /* Malformed TLP */

739 PCI_ERR_UNC_ECRC | /* ECRC Error Status */

740 PCI_ERR_UNC_UNSUP | /* Unsupported Request */

741 PCI_ERR_UNC_ACSV | /* ACS Violation */

742 PCI_ERR_UNC_INTN | /* internal error */

743 PCI_ERR_UNC_MCBTLP | /* MC blocked TLP */

744 PCI_ERR_UNC_ATOMEG | /* Atomic egress blocked */

745 PCI_ERR_UNC_TLPPRE; /* TLP prefix blocked */

746 p_setd(perm, PCI_ERR_UNCOR_STATUS, NO_VIRT, mask);

747 p_setd(perm, PCI_ERR_UNCOR_MASK, NO_VIRT, mask);

748 p_setd(perm, PCI_ERR_UNCOR_SEVER, NO_VIRT, mask);

749

750 mask = PCI_ERR_COR_RCVR | /* Receiver Error Status */

751 PCI_ERR_COR_BAD_TLP | /* Bad TLP Status */

752 PCI_ERR_COR_BAD_DLLP | /* Bad DLLP Status */

753 PCI_ERR_COR_REP_ROLL | /* REPLAY_NUM Rollover */

754 PCI_ERR_COR_REP_TIMER | /* Replay Timer Timeout */

755 PCI_ERR_COR_ADV_NFAT | /* Advisory Non-Fatal */

756 PCI_ERR_COR_INTERNAL | /* Corrected Internal */

757 PCI_ERR_COR_LOG_OVER; /* Header Log Overflow */

758 p_setd(perm, PCI_ERR_COR_STATUS, NO_VIRT, mask);

759 p_setd(perm, PCI_ERR_COR_MASK, NO_VIRT, mask);

760

761 mask = PCI_ERR_CAP_ECRC_GENE | /* ECRC Generation Enable */

762 PCI_ERR_CAP_ECRC_CHKE; /* ECRC Check Enable */

763 p_setd(perm, PCI_ERR_CAP, NO_VIRT, mask);

764 return 0;

765 }

766

767 /* Permissions for Power Budgeting extended capability */

768 static int __init init_pci_ext_cap_pwr_perm(struct perm_bits *perm)

769 {

770 if (alloc_perm_bits(perm, pci_ext_cap_length[PCI_EXT_CAP_ID_PWR]))

771 return -ENOMEM;

772

773 p_setd(perm, 0, ALL_VIRT, NO_WRITE);

774

775 /* Writing the data selector is OK, the info is still read-only */

776 p_setb(perm, PCI_PWR_DATA, NO_VIRT, (u8)ALL_WRITE);

777 return 0;

778 }

779

780 /*

781 * Initialize the shared permission tables

782 */

783 void vfio_pci_uninit_perm_bits(void)

784 {

785 free_perm_bits(&cap_perms[PCI_CAP_ID_BASIC]);

786

787 free_perm_bits(&cap_perms[PCI_CAP_ID_PM]);

788 free_perm_bits(&cap_perms[PCI_CAP_ID_PCIX]);

789 free_perm_bits(&cap_perms[PCI_CAP_ID_EXP]);

790 free_perm_bits(&cap_perms[PCI_CAP_ID_AF]);

791

792 free_perm_bits(&ecap_perms[PCI_EXT_CAP_ID_ERR]);

793 free_perm_bits(&ecap_perms[PCI_EXT_CAP_ID_PWR]);

794 }

795

796 int __init vfio_pci_init_perm_bits(void)

797 {

798 int ret;

799

800 /* Basic config space */

801 ret = init_pci_cap_basic_perm(&cap_perms[PCI_CAP_ID_BASIC]);

802

803 /* Capabilities */

804 ret |= init_pci_cap_pm_perm(&cap_perms[PCI_CAP_ID_PM]);

805 cap_perms[PCI_CAP_ID_VPD].writefn = vfio_raw_config_write;

806 ret |= init_pci_cap_pcix_perm(&cap_perms[PCI_CAP_ID_PCIX]);

807 cap_perms[PCI_CAP_ID_VNDR].writefn = vfio_raw_config_write;

808 ret |= init_pci_cap_exp_perm(&cap_perms[PCI_CAP_ID_EXP]);

809 ret |= init_pci_cap_af_perm(&cap_perms[PCI_CAP_ID_AF]);

810

811 /* Extended capabilities */

812 ret |= init_pci_ext_cap_err_perm(&ecap_perms[PCI_EXT_CAP_ID_ERR]);

813 ret |= init_pci_ext_cap_pwr_perm(&ecap_perms[PCI_EXT_CAP_ID_PWR]);

814 ecap_perms[PCI_EXT_CAP_ID_VNDR].writefn = vfio_raw_config_write;

815

816 if (ret)

817 vfio_pci_uninit_perm_bits();

818

819 return ret;

820 }

821

822 static int vfio_find_cap_start(struct vfio_pci_device *vdev, int pos)

823 {

824 u8 cap;

825 int base = (pos >= PCI_CFG_SPACE_SIZE) ? PCI_CFG_SPACE_SIZE :

826 PCI_STD_HEADER_SIZEOF;

827 cap = vdev->pci_config_map[pos];

828

829 if (cap == PCI_CAP_ID_BASIC)

830 return 0;

831

832 /* XXX Can we have to abutting capabilities of the same type? */

833 while (pos - 1 >= base && vdev->pci_config_map[pos - 1] == cap)

834 pos--;

835

836 return pos;

837 }

838

839 static int vfio_msi_config_read(struct vfio_pci_device *vdev, int pos,

840 int count, struct perm_bits *perm,

841 int offset, __le32 *val)

842 {

843 /* Update max available queue size from msi_qmax */

844 if (offset <= PCI_MSI_FLAGS && offset + count >= PCI_MSI_FLAGS) {

845 __le16 *flags;

846 int start;

847

848 start = vfio_find_cap_start(vdev, pos);

849

850 flags = (__le16 *)&vdev->vconfig[start];

851

852 *flags &= cpu_to_le16(~PCI_MSI_FLAGS_QMASK);

853 *flags |= cpu_to_le16(vdev->msi_qmax << 1);

854 }

855

856 return vfio_default_config_read(vdev, pos, count, perm, offset, val);

857 }

858

859 static int vfio_msi_config_write(struct vfio_pci_device *vdev, int pos,

860 int count, struct perm_bits *perm,

861 int offset, __le32 val)

862 {

863 count = vfio_default_config_write(vdev, pos, count, perm, offset, val);

864 if (count < 0)

865 return count;

866

867 /* Fixup and write configured queue size and enable to hardware */

868 if (offset <= PCI_MSI_FLAGS && offset + count >= PCI_MSI_FLAGS) {

869 __le16 *pflags;

870 u16 flags;

871 int start, ret;

872

873 start = vfio_find_cap_start(vdev, pos);

874

875 pflags = (__le16 *)&vdev->vconfig[start + PCI_MSI_FLAGS];

876

877 flags = le16_to_cpu(*pflags);

878

879 /* MSI is enabled via ioctl */

880 if (!is_msi(vdev))

881 flags &= ~PCI_MSI_FLAGS_ENABLE;

882

883 /* Check queue size */

884 if ((flags & PCI_MSI_FLAGS_QSIZE) >> 4 > vdev->msi_qmax) {

885 flags &= ~PCI_MSI_FLAGS_QSIZE;

886 flags |= vdev->msi_qmax << 4;

887 }

888

889 /* Write back to virt and to hardware */

890 *pflags = cpu_to_le16(flags);

891 ret = pci_user_write_config_word(vdev->pdev,

892 start + PCI_MSI_FLAGS,

893 flags);

894 if (ret)

895 return pcibios_err_to_errno(ret);

896 }

897

898 return count;

899 }

900

901 /*

902 * MSI determination is per-device, so this routine gets used beyond

903 * initialization time. Don't add __init

904 */

905 static int init_pci_cap_msi_perm(struct perm_bits *perm, int len, u16 flags)

906 {

907 if (alloc_perm_bits(perm, len))

908 return -ENOMEM;

909

910 perm->readfn = vfio_msi_config_read;

911 perm->writefn = vfio_msi_config_write;

912

913 p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE);

914

915 /*

916 * The upper byte of the control register is reserved,

917 * just setup the lower byte.

918 */

919 p_setb(perm, PCI_MSI_FLAGS, (u8)ALL_VIRT, (u8)ALL_WRITE);

920 p_setd(perm, PCI_MSI_ADDRESS_LO, ALL_VIRT, ALL_WRITE);

921 if (flags & PCI_MSI_FLAGS_64BIT) {

922 p_setd(perm, PCI_MSI_ADDRESS_HI, ALL_VIRT, ALL_WRITE);

923 p_setw(perm, PCI_MSI_DATA_64, (u16)ALL_VIRT, (u16)ALL_WRITE);

924 if (flags & PCI_MSI_FLAGS_MASKBIT) {

925 p_setd(perm, PCI_MSI_MASK_64, NO_VIRT, ALL_WRITE);

926 p_setd(perm, PCI_MSI_PENDING_64, NO_VIRT, ALL_WRITE);

927 }

928 } else {

929 p_setw(perm, PCI_MSI_DATA_32, (u16)ALL_VIRT, (u16)ALL_WRITE);

930 if (flags & PCI_MSI_FLAGS_MASKBIT) {

931 p_setd(perm, PCI_MSI_MASK_32, NO_VIRT, ALL_WRITE);

932 p_setd(perm, PCI_MSI_PENDING_32, NO_VIRT, ALL_WRITE);

933 }

934 }

935 return 0;

936 }

937

938 /* Determine MSI CAP field length; initialize msi_perms on 1st call per vdev */

939 static int vfio_msi_cap_len(struct vfio_pci_device *vdev, u8 pos)

940 {

941 struct pci_dev *pdev = vdev->pdev;

942 int len, ret;

943 u16 flags;

944

945 ret = pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &flags);

946 if (ret)

947 return pcibios_err_to_errno(ret);

948

949 len = 10; /* Minimum size */

950 if (flags & PCI_MSI_FLAGS_64BIT)

951 len += 4;

952 if (flags & PCI_MSI_FLAGS_MASKBIT)

953 len += 10;

954

955 if (vdev->msi_perm)

956 return len;

957

958 vdev->msi_perm = kmalloc(sizeof(struct perm_bits), GFP_KERNEL);

959 if (!vdev->msi_perm)

960 return -ENOMEM;

961

962 ret = init_pci_cap_msi_perm(vdev->msi_perm, len, flags);

963 if (ret)

964 return ret;

965

966 return len;

967 }

968

969 /* Determine extended capability length for VC (2 & 9) and MFVC */

970 static int vfio_vc_cap_len(struct vfio_pci_device *vdev, u16 pos)

971 {

972 struct pci_dev *pdev = vdev->pdev;

973 u32 tmp;

974 int ret, evcc, phases, vc_arb;

975 int len = PCI_CAP_VC_BASE_SIZEOF;

976

977 ret = pci_read_config_dword(pdev, pos + PCI_VC_PORT_REG1, &tmp);

978 if (ret)

979 return pcibios_err_to_errno(ret);

980

981 evcc = tmp & PCI_VC_REG1_EVCC; /* extended vc count */

982 ret = pci_read_config_dword(pdev, pos + PCI_VC_PORT_REG2, &tmp);

983 if (ret)

984 return pcibios_err_to_errno(ret);

985

986 if (tmp & PCI_VC_REG2_128_PHASE)

987 phases = 128;

988 else if (tmp & PCI_VC_REG2_64_PHASE)

989 phases = 64;

990 else if (tmp & PCI_VC_REG2_32_PHASE)

991 phases = 32;

992 else

993 phases = 0;

994

995 vc_arb = phases * 4;

996

997 /*

998 * Port arbitration tables are root & switch only;

999 * function arbitration tables are function 0 only.

1000 * In either case, we'll never let user write them so

1001 * we don't care how big they are

1002 */

1003 len += (1 + evcc) * PCI_CAP_VC_PER_VC_SIZEOF;

1004 if (vc_arb) {

1005 len = round_up(len, 16);

1006 len += vc_arb / 8;

1007 }

1008 return len;

1009 }

1010

1011 static int vfio_cap_len(struct vfio_pci_device *vdev, u8 cap, u8 pos)

1012 {

1013 struct pci_dev *pdev = vdev->pdev;

1014 u16 word;

1015 u8 byte;

1016 int ret;

1017

1018 switch (cap) {

1019 case PCI_CAP_ID_MSI:

1020 return vfio_msi_cap_len(vdev, pos);

1021 case PCI_CAP_ID_PCIX:

1022 ret = pci_read_config_word(pdev, pos + PCI_X_CMD, &word);

1023 if (ret)

1024 return pcibios_err_to_errno(ret);

1025

1026 if (PCI_X_CMD_VERSION(word)) {

1027 vdev->extended_caps = true;

1028 return PCI_CAP_PCIX_SIZEOF_V2;

1029 } else

1030 return PCI_CAP_PCIX_SIZEOF_V0;

1031 case PCI_CAP_ID_VNDR:

1032 /* length follows next field */

1033 ret = pci_read_config_byte(pdev, pos + PCI_CAP_FLAGS, &byte);

1034 if (ret)

1035 return pcibios_err_to_errno(ret);

1036

1037 return byte;

1038 case PCI_CAP_ID_EXP:

1039 /* length based on version */

1040 ret = pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, &word);

1041 if (ret)

1042 return pcibios_err_to_errno(ret);

1043

1044 vdev->extended_caps = true;

1045

1046 if ((word & PCI_EXP_FLAGS_VERS) == 1)

1047 return PCI_CAP_EXP_ENDPOINT_SIZEOF_V1;

1048 else

1049 return PCI_CAP_EXP_ENDPOINT_SIZEOF_V2;

1050 case PCI_CAP_ID_HT:

1051 ret = pci_read_config_byte(pdev, pos + 3, &byte);

1052 if (ret)

1053 return pcibios_err_to_errno(ret);

1054

1055 return (byte & HT_3BIT_CAP_MASK) ?

1056 HT_CAP_SIZEOF_SHORT : HT_CAP_SIZEOF_LONG;

1057 case PCI_CAP_ID_SATA:

1058 ret = pci_read_config_byte(pdev, pos + PCI_SATA_REGS, &byte);

1059 if (ret)

1060 return pcibios_err_to_errno(ret);

1061

1062 byte &= PCI_SATA_REGS_MASK;

1063 if (byte == PCI_SATA_REGS_INLINE)

1064 return PCI_SATA_SIZEOF_LONG;

1065 else

1066 return PCI_SATA_SIZEOF_SHORT;

1067 default:

1068 pr_warn("%s: %s unknown length for pci cap 0x%x@0x%x\n",

1069 dev_name(&pdev->dev), __func__, cap, pos);

1070 }

1071

1072 return 0;

1073 }

1074

1075 static int vfio_ext_cap_len(struct vfio_pci_device *vdev, u16 ecap, u16 epos)

1076 {

1077 struct pci_dev *pdev = vdev->pdev;

1078 u8 byte;

1079 u32 dword;

1080 int ret;

1081

1082 switch (ecap) {

1083 case PCI_EXT_CAP_ID_VNDR:

1084 ret = pci_read_config_dword(pdev, epos + PCI_VSEC_HDR, &dword);

1085 if (ret)

1086 return pcibios_err_to_errno(ret);

1087

1088 return dword >> PCI_VSEC_HDR_LEN_SHIFT;

1089 case PCI_EXT_CAP_ID_VC:

1090 case PCI_EXT_CAP_ID_VC9:

1091 case PCI_EXT_CAP_ID_MFVC:

1092 return vfio_vc_cap_len(vdev, epos);

1093 case PCI_EXT_CAP_ID_ACS:

1094 ret = pci_read_config_byte(pdev, epos + PCI_ACS_CAP, &byte);

1095 if (ret)

1096 return pcibios_err_to_errno(ret);

1097

1098 if (byte & PCI_ACS_EC) {

1099 int bits;

1100

1101 ret = pci_read_config_byte(pdev,

1102 epos + PCI_ACS_EGRESS_BITS,

1103 &byte);

1104 if (ret)

1105 return pcibios_err_to_errno(ret);

1106

1107 bits = byte ? round_up(byte, 32) : 256;

1108 return 8 + (bits / 8);

1109 }

1110 return 8;

1111

1112 case PCI_EXT_CAP_ID_REBAR:

1113 ret = pci_read_config_byte(pdev, epos + PCI_REBAR_CTRL, &byte);

1114 if (ret)

1115 return pcibios_err_to_errno(ret);

1116

1117 byte &= PCI_REBAR_CTRL_NBAR_MASK;

1118 byte >>= PCI_REBAR_CTRL_NBAR_SHIFT;

1119

1120 return 4 + (byte * 8);

1121 case PCI_EXT_CAP_ID_DPA:

1122 ret = pci_read_config_byte(pdev, epos + PCI_DPA_CAP, &byte);

1123 if (ret)

1124 return pcibios_err_to_errno(ret);

1125

1126 byte &= PCI_DPA_CAP_SUBSTATE_MASK;

1127 byte = round_up(byte + 1, 4);

1128 return PCI_DPA_BASE_SIZEOF + byte;

1129 case PCI_EXT_CAP_ID_TPH:

1130 ret = pci_read_config_dword(pdev, epos + PCI_TPH_CAP, &dword);

1131 if (ret)

1132 return pcibios_err_to_errno(ret);

1133

1134 if ((dword & PCI_TPH_CAP_LOC_MASK) == PCI_TPH_LOC_CAP) {

1135 int sts;

1136

1137 sts = byte & PCI_TPH_CAP_ST_MASK;

1138 sts >>= PCI_TPH_CAP_ST_SHIFT;

1139 return PCI_TPH_BASE_SIZEOF + round_up(sts * 2, 4);

1140 }

1141 return PCI_TPH_BASE_SIZEOF;

1142 default:

1143 pr_warn("%s: %s unknown length for pci ecap 0x%x@0x%x\n",

1144 dev_name(&pdev->dev), __func__, ecap, epos);

1145 }

1146

1147 return 0;

1148 }

1149

1150 static int vfio_fill_vconfig_bytes(struct vfio_pci_device *vdev,

1151 int offset, int size)

1152 {

1153 struct pci_dev *pdev = vdev->pdev;

1154 int ret = 0;

1155

1156 /*

1157 * We try to read physical config space in the largest chunks

1158 * we can, assuming that all of the fields support dword access.

1159 * pci_save_state() makes this same assumption and seems to do ok.

1160 */

1161 while (size) {

1162 int filled;

1163

1164 if (size >= 4 && !(offset % 4)) {

1165 __le32 *dwordp = (__le32 *)&vdev->vconfig[offset];

1166 u32 dword;

1167

1168 ret = pci_read_config_dword(pdev, offset, &dword);

1169 if (ret)

1170 return ret;

1171 *dwordp = cpu_to_le32(dword);

1172 filled = 4;

1173 } else if (size >= 2 && !(offset % 2)) {

1174 __le16 *wordp = (__le16 *)&vdev->vconfig[offset];

1175 u16 word;

1176

1177 ret = pci_read_config_word(pdev, offset, &word);

1178 if (ret)

1179 return ret;

1180 *wordp = cpu_to_le16(word);

1181 filled = 2;

1182 } else {

1183 u8 *byte = &vdev->vconfig[offset];

1184 ret = pci_read_config_byte(pdev, offset, byte);

1185 if (ret)

1186 return ret;

1187 filled = 1;

1188 }

1189

1190 offset += filled;

1191 size -= filled;

1192 }

1193

1194 return ret;

1195 }

1196

1197 static int vfio_cap_init(struct vfio_pci_device *vdev)

1198 {

1199 struct pci_dev *pdev = vdev->pdev;

1200 u8 *map = vdev->pci_config_map;

1201 u16 status;

1202 u8 pos, *prev, cap;

1203 int loops, ret, caps = 0;

1204

1205 /* Any capabilities? */

1206 ret = pci_read_config_word(pdev, PCI_STATUS, &status);

1207 if (ret)

1208 return ret;

1209

1210 if (!(status & PCI_STATUS_CAP_LIST))

1211 return 0; /* Done */

1212

1213 ret = pci_read_config_byte(pdev, PCI_CAPABILITY_LIST, &pos);

1214 if (ret)

1215 return ret;

1216

1217 /* Mark the previous position in case we want to skip a capability */

1218 prev = &vdev->vconfig[PCI_CAPABILITY_LIST];

1219

1220 /* We can bound our loop, capabilities are dword aligned */

1221 loops = (PCI_CFG_SPACE_SIZE - PCI_STD_HEADER_SIZEOF) / PCI_CAP_SIZEOF;

1222 while (pos && loops--) {

1223 u8 next;

1224 int i, len = 0;

1225

1226 ret = pci_read_config_byte(pdev, pos, &cap);

1227 if (ret)

1228 return ret;

1229

1230 ret = pci_read_config_byte(pdev,

1231 pos + PCI_CAP_LIST_NEXT, &next);

1232 if (ret)

1233 return ret;

1234

1235 if (cap <= PCI_CAP_ID_MAX) {

1236 len = pci_cap_length[cap];

1237 if (len == 0xFF) { /* Variable length */

1238 len = vfio_cap_len(vdev, cap, pos);

1239 if (len < 0)

1240 return len;

1241 }

1242 }

1243

1244 if (!len) {

1245 pr_info("%s: %s hiding cap 0x%x\n",

1246 __func__, dev_name(&pdev->dev), cap);

1247 *prev = next;

1248 pos = next;

1249 continue;

1250 }

1251

1252 /* Sanity check, do we overlap other capabilities? */

1253 for (i = 0; i < len; i++) {

1254 if (likely(map[pos + i] == PCI_CAP_ID_INVALID))

1255 continue;

1256

1257 pr_warn("%s: %s pci config conflict @0x%x, was cap 0x%x now cap 0x%x\n",

1258 __func__, dev_name(&pdev->dev),

1259 pos + i, map[pos + i], cap);

1260 }

1261

1262 memset(map + pos, cap, len);

1263 ret = vfio_fill_vconfig_bytes(vdev, pos, len);

1264 if (ret)

1265 return ret;

1266

1267 prev = &vdev->vconfig[pos + PCI_CAP_LIST_NEXT];

1268 pos = next;

1269 caps++;

1270 }

1271

1272 /* If we didn't fill any capabilities, clear the status flag */

1273 if (!caps) {

1274 __le16 *vstatus = (__le16 *)&vdev->vconfig[PCI_STATUS];

1275 *vstatus &= ~cpu_to_le16(PCI_STATUS_CAP_LIST);

1276 }

1277

1278 return 0;

1279 }

1280

1281 static int vfio_ecap_init(struct vfio_pci_device *vdev)

1282 {

1283 struct pci_dev *pdev = vdev->pdev;

1284 u8 *map = vdev->pci_config_map;

1285 u16 epos;

1286 __le32 *prev = NULL;

1287 int loops, ret, ecaps = 0;

1288

1289 if (!vdev->extended_caps)

1290 return 0;

1291

1292 epos = PCI_CFG_SPACE_SIZE;

1293

1294 loops = (pdev->cfg_size - PCI_CFG_SPACE_SIZE) / PCI_CAP_SIZEOF;

1295

1296 while (loops-- && epos >= PCI_CFG_SPACE_SIZE) {

1297 u32 header;

1298 u16 ecap;

1299 int i, len = 0;

1300 bool hidden = false;

1301

1302 ret = pci_read_config_dword(pdev, epos, &header);

1303 if (ret)

1304 return ret;

1305

1306 ecap = PCI_EXT_CAP_ID(header);

1307

1308 if (ecap <= PCI_EXT_CAP_ID_MAX) {

1309 len = pci_ext_cap_length[ecap];

1310 if (len == 0xFF) {

1311 len = vfio_ext_cap_len(vdev, ecap, epos);

1312 if (len < 0)

1313 return ret;

1314 }

1315 }

1316

1317 if (!len) {

1318 pr_info("%s: %s hiding ecap 0x%x@0x%x\n",

1319 __func__, dev_name(&pdev->dev), ecap, epos);

1320

1321 /* If not the first in the chain, we can skip over it */

1322 if (prev) {

1323 u32 val = epos = PCI_EXT_CAP_NEXT(header);

1324 *prev &= cpu_to_le32(~(0xffcU << 20));

1325 *prev |= cpu_to_le32(val << 20);

1326 continue;

1327 }

1328

1329 /*

1330 * Otherwise, fill in a placeholder, the direct

1331 * readfn will virtualize this automatically

1332 */

1333 len = PCI_CAP_SIZEOF;

1334 hidden = true;

1335 }

1336

1337 for (i = 0; i < len; i++) {

1338 if (likely(map[epos + i] == PCI_CAP_ID_INVALID))

1339 continue;

1340

1341 pr_warn("%s: %s pci config conflict @0x%x, was ecap 0x%x now ecap 0x%x\n",

1342 __func__, dev_name(&pdev->dev),

1343 epos + i, map[epos + i], ecap);

1344 }

1345

1346 /*

1347 * Even though ecap is 2 bytes, we're currently a long way

1348 * from exceeding 1 byte capabilities. If we ever make it

1349 * up to 0xFF we'll need to up this to a two-byte, byte map.

1350 */

1351 BUILD_BUG_ON(PCI_EXT_CAP_ID_MAX >= PCI_CAP_ID_INVALID);

1352

1353 memset(map + epos, ecap, len);

1354 ret = vfio_fill_vconfig_bytes(vdev, epos, len);

1355 if (ret)

1356 return ret;

1357

1358 /*

1359 * If we're just using this capability to anchor the list,

1360 * hide the real ID. Only count real ecaps. XXX PCI spec

1361 * indicates to use cap id = 0, version = 0, next = 0 if

1362 * ecaps are absent, hope users check all the way to next.

1363 */

1364 if (hidden)

1365 *(__le32 *)&vdev->vconfig[epos] &=

1366 cpu_to_le32((0xffcU << 20));

1367 else

1368 ecaps++;

1369

1370 prev = (__le32 *)&vdev->vconfig[epos];

1371 epos = PCI_EXT_CAP_NEXT(header);

1372 }

1373

1374 if (!ecaps)

1375 *(u32 *)&vdev->vconfig[PCI_CFG_SPACE_SIZE] = 0;

1376

1377 return 0;

1378 }

1379

1380 /*

1381 * For each device we allocate a pci_config_map that indicates the

1382 * capability occupying each dword and thus the struct perm_bits we

1383 * use for read and write. We also allocate a virtualized config

1384 * space which tracks reads and writes to bits that we emulate for

1385 * the user. Initial values filled from device.

1386 *

1387 * Using shared stuct perm_bits between all vfio-pci devices saves

1388 * us from allocating cfg_size buffers for virt and write for every

1389 * device. We could remove vconfig and allocate individual buffers

1390 * for each area requring emulated bits, but the array of pointers

1391 * would be comparable in size (at least for standard config space).

1392 */

1393 int vfio_config_init(struct vfio_pci_device *vdev)

1394 {

1395 struct pci_dev *pdev = vdev->pdev;

1396 u8 *map, *vconfig;

1397 int ret;

1398

1399 /*

1400 * Config space, caps and ecaps are all dword aligned, so we could

1401 * use one byte per dword to record the type. However, there are

1402 * no requiremenst on the length of a capability, so the gap between

1403 * capabilities needs byte granularity.

1404 */

1405 map = kmalloc(pdev->cfg_size, GFP_KERNEL);

1406 if (!map)

1407 return -ENOMEM;

1408

1409 vconfig = kmalloc(pdev->cfg_size, GFP_KERNEL);

1410 if (!vconfig) {

1411 kfree(map);

1412 return -ENOMEM;

1413 }

1414

1415 vdev->pci_config_map = map;

1416 vdev->vconfig = vconfig;

1417

1418 memset(map, PCI_CAP_ID_BASIC, PCI_STD_HEADER_SIZEOF);

1419 memset(map + PCI_STD_HEADER_SIZEOF, PCI_CAP_ID_INVALID,

1420 pdev->cfg_size - PCI_STD_HEADER_SIZEOF);

1421

1422 ret = vfio_fill_vconfig_bytes(vdev, 0, PCI_STD_HEADER_SIZEOF);

1423 if (ret)

1424 goto out;

1425

1426 vdev->bardirty = true;

1427

1428 /*

1429 * XXX can we just pci_load_saved_state/pci_restore_state?

1430 * may need to rebuild vconfig after that

1431 */

1432

1433 /* For restore after reset */

1434 vdev->rbar[0] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_0]);

1435 vdev->rbar[1] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_1]);

1436 vdev->rbar[2] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_2]);

1437 vdev->rbar[3] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_3]);

1438 vdev->rbar[4] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_4]);

1439 vdev->rbar[5] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_5]);

1440 vdev->rbar[6] = le32_to_cpu(*(__le32 *)&vconfig[PCI_ROM_ADDRESS]);

1441

1442 if (pdev->is_virtfn) {

1443 *(__le16 *)&vconfig[PCI_VENDOR_ID] = cpu_to_le16(pdev->vendor);

1444 *(__le16 *)&vconfig[PCI_DEVICE_ID] = cpu_to_le16(pdev->device);

1445 }

1446

1447 ret = vfio_cap_init(vdev);

1448 if (ret)

1449 goto out;

1450

1451 ret = vfio_ecap_init(vdev);

1452 if (ret)

1453 goto out;

1454

1455 return 0;

1456

1457 out:

1458 kfree(map);

1459 vdev->pci_config_map = NULL;

1460 kfree(vconfig);

1461 vdev->vconfig = NULL;

1462 return pcibios_err_to_errno(ret);

1463 }

1464

1465 void vfio_config_free(struct vfio_pci_device *vdev)

1466 {

1467 kfree(vdev->vconfig);

1468 vdev->vconfig = NULL;

1469 kfree(vdev->pci_config_map);

1470 vdev->pci_config_map = NULL;

1471 kfree(vdev->msi_perm);

1472 vdev->msi_perm = NULL;

1473 }

1474

1475 /*

1476 * Find the remaining number of bytes in a dword that match the given

1477 * position. Stop at either the end of the capability or the dword boundary.

1478 */

1479 static size_t vfio_pci_cap_remaining_dword(struct vfio_pci_device *vdev,

1480 loff_t pos)

1481 {

1482 u8 cap = vdev->pci_config_map[pos];

1483 size_t i;

1484

1485 for (i = 1; (pos + i) % 4 && vdev->pci_config_map[pos + i] == cap; i++)

1486 /* nop */;

1487

1488 return i;

1489 }

1490

1491 static ssize_t vfio_config_do_rw(struct vfio_pci_device *vdev, char __user *buf,

1492 size_t count, loff_t *ppos, bool iswrite)

1493 {

1494 struct pci_dev *pdev = vdev->pdev;

1495 struct perm_bits *perm;

1496 __le32 val = 0;

1497 int cap_start = 0, offset;

1498 u8 cap_id;

1499 ssize_t ret;

1500

1501 if (*ppos < 0 || *ppos >= pdev->cfg_size ||

1502 *ppos + count > pdev->cfg_size)

1503 return -EFAULT;

1504

1505 /*

1506 * Chop accesses into aligned chunks containing no more than a

1507 * single capability. Caller increments to the next chunk.

1508 */

1509 count = min(count, vfio_pci_cap_remaining_dword(vdev, *ppos));

1510 if (count >= 4 && !(*ppos % 4))

1511 count = 4;

1512 else if (count >= 2 && !(*ppos % 2))

1513 count = 2;

1514 else

1515 count = 1;

1516

1517 ret = count;

1518

1519 cap_id = vdev->pci_config_map[*ppos];

1520

1521 if (cap_id == PCI_CAP_ID_INVALID) {

1522 perm = &unassigned_perms;

1523 cap_start = *ppos;

1524 } else {

1525 if (*ppos >= PCI_CFG_SPACE_SIZE) {

1526 WARN_ON(cap_id > PCI_EXT_CAP_ID_MAX);

1527

1528 perm = &ecap_perms[cap_id];

1529 cap_start = vfio_find_cap_start(vdev, *ppos);

1530 } else {

1531 WARN_ON(cap_id > PCI_CAP_ID_MAX);

1532

1533 perm = &cap_perms[cap_id];

1534

1535 if (cap_id == PCI_CAP_ID_MSI)

1536 perm = vdev->msi_perm;

1537

1538 if (cap_id > PCI_CAP_ID_BASIC)

1539 cap_start = vfio_find_cap_start(vdev, *ppos);

1540 }

1541 }

1542

1543 WARN_ON(!cap_start && cap_id != PCI_CAP_ID_BASIC);

1544 WARN_ON(cap_start > *ppos);

1545

1546 offset = *ppos - cap_start;

1547

1548 if (iswrite) {

1549 if (!perm->writefn)

1550 return ret;

1551

1552 if (copy_from_user(&val, buf, count))

1553 return -EFAULT;

1554

1555 ret = perm->writefn(vdev, *ppos, count, perm, offset, val);

1556 } else {

1557 if (perm->readfn) {

1558 ret = perm->readfn(vdev, *ppos, count,

1559 perm, offset, &val);

1560 if (ret < 0)

1561 return ret;

1562 }

1563

1564 if (copy_to_user(buf, &val, count))

1565 return -EFAULT;

1566 }

1567

1568 return ret;

1569 }

1570

1571 ssize_t vfio_pci_config_rw(struct vfio_pci_device *vdev, char __user *buf,

1572 size_t count, loff_t *ppos, bool iswrite)

1573 {

1574 size_t done = 0;

1575 int ret = 0;

1576 loff_t pos = *ppos;

1577

1578 pos &= VFIO_PCI_OFFSET_MASK;

1579

1580 while (count) {

1581 ret = vfio_config_do_rw(vdev, buf, count, &pos, iswrite);

1582 if (ret < 0)

1583 return ret;

1584

1585 count -= ret;

1586 done += ret;

1587 buf += ret;

1588 pos += ret;

1589 }

1590

1591 *ppos += done;

1592

1593 return done;

1594 }