Antonio Nino Diaz [Tue, 25 Sep 2018 08:39:51 +0000 (09:39 +0100)]
Remove all other deprecated interfaces and files
Change-Id: Icd1cdd42afdc78895a9be6c46b414b0a155cfa63
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Antonio Nino Diaz [Mon, 24 Sep 2018 21:07:58 +0000 (22:07 +0100)]
drivers: cadence: cdns: Fix flush function
It is still a placeholder, but now it is registered correctly by the
macro finish_console_register.
Change-Id: Ic78c966d9be606cbc1a53cec43ead23b32963afe
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Antonio Nino Diaz [Mon, 24 Sep 2018 16:29:01 +0000 (17:29 +0100)]
console: Remove deprecated files
Change-Id: Ib9eebbdff6f7868e1d1b8c41761cacc7501a25bd
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Antonio Nino Diaz [Mon, 24 Sep 2018 10:14:58 +0000 (11:14 +0100)]
cci400: Remove deprecated driver
This driver is deprecated.
Change-Id: Ic6e154a5756e779743b17a329eed4570ccc61389
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Antonio Nino Diaz [Mon, 24 Sep 2018 10:40:12 +0000 (11:40 +0100)]
tzc400: Remove deprecated interfaces
Change-Id: I9874883ec33dbf293f607f9779d7c56f23cb8023
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Antonio Nino Diaz [Mon, 24 Sep 2018 16:28:13 +0000 (17:28 +0100)]
xlat: Remove deprecated interfaces
Change-Id: I83de2ae3e0795e6fec3c1e5b37c441b64b0c9cb6
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Antonio Nino Diaz [Mon, 24 Sep 2018 16:27:55 +0000 (17:27 +0100)]
context_mgmt: Remove deprecated interfaces
Change-Id: I2d4a21a80a768bc422e9707e6d7e98d20a716275
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Antonio Nino Diaz [Mon, 24 Sep 2018 16:26:25 +0000 (17:26 +0100)]
Remove deprecated bl1_init_bl2_mem_layout()
Change-Id: I8ec8b4439ca1d7606aae069c2c576a9a8b18c92c
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Antonio Nino Diaz [Mon, 24 Sep 2018 16:24:41 +0000 (17:24 +0100)]
Remove deprecated early platform setup interfaces
The affected interfaces are bl31_early_platform_setup(),
sp_min_early_platform_setup() and bl2_early_platform_setup().
Change-Id: I50c01ec68bcbe97fe4e5d101bcd0f763358b8e1e
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Antonio Nino Diaz [Mon, 24 Sep 2018 16:23:24 +0000 (17:23 +0100)]
gic: Remove deprecated driver and interfaces
Change-Id: I567a406edb090ae9d109382f6874846a79dd7473
Co-authored-by: Roberto Vargas <roberto.vargas@arm.com>
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Antonio Nino Diaz [Tue, 25 Sep 2018 08:41:08 +0000 (09:41 +0100)]
tbbr: Use USE_TBBR_DEFS=1 by default
Change-Id: I2885b0d8cb9bb16da1fa96a30e46cccde434dc42
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Roberto Vargas [Mon, 24 Sep 2018 16:20:48 +0000 (17:20 +0100)]
Remove build option LOAD_IMAGE_V2
The code of LOAD_IMAGE_V2=0 has been removed.
Change-Id: Iea03e5bebb90c66889bdb23f85c07d0c9717fffe
Co-authored-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Antonio Nino Diaz [Mon, 24 Sep 2018 16:18:33 +0000 (17:18 +0100)]
PSCI: Remove deprecated file plat_psci_common.c
Change-Id: I9fd8016527ad7706494f34356fdae8efacef5f72
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Roberto Vargas [Mon, 24 Sep 2018 16:14:46 +0000 (17:14 +0100)]
PSCI: Remove platform compatibility layer
Change-Id: I40d040aa05bcbf11536a96ce59827711456b93a8
Co-authored-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
dp-arm [Fri, 30 Dec 2016 14:33:24 +0000 (14:33 +0000)]
fip_create: Remove fip_create compatibility script
A compatibility script has been provided for about 2 years. Users should
have migrated to fiptool by now so remove the compat script.
Change-Id: I643e0c40a9e3fb428bad3be04a82cb431aad74dc
Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
Dimitris Papastamos [Fri, 28 Sep 2018 13:23:50 +0000 (14:23 +0100)]
Merge pull request #1594 from ARM-software/revert-1586-topics/ep/scp_bl2_size
Revert "sgm: increase SCP_BL2 maximum size"
Dimitris Papastamos [Fri, 28 Sep 2018 13:23:26 +0000 (14:23 +0100)]
Revert "sgm: increase SCP_BL2 maximum size"
Dimitris Papastamos [Fri, 28 Sep 2018 12:58:21 +0000 (13:58 +0100)]
Merge pull request #1593 from shawnguo2/mmc_fix_R2_response
drivers: mmc: Fix R2 response type definition
Dimitris Papastamos [Fri, 28 Sep 2018 12:57:45 +0000 (13:57 +0100)]
Merge pull request #1592 from shawnguo2/fix-recovery-build
poplar: fix build error with POPLAR_RECOVERY=1
Dimitris Papastamos [Fri, 28 Sep 2018 12:56:59 +0000 (13:56 +0100)]
Merge pull request #1586 from Elieva/topics/ep/scp_bl2_size
sgm: increase SCP_BL2 maximum size
Shawn Guo [Fri, 28 Sep 2018 06:21:01 +0000 (14:21 +0800)]
drivers: mmc: Fix R2 response type definition
The Poplar is broken on eMMC initialization because of commit
2a82a9c95f6c ("drivers: emmc: dw_mmc: Add response flag into response ID
definition"). It changes the driver behavior on response type handling
in dw_send_cmd(), because MMC_RESPONSE_R(2) and MMC_RESPONSE_R2 are
different things. MMC core is still sending the former while we already
changed to check the latter in dw_mmc driver.
This patch fixes R2 response type in MMC core code. It's the same
thing as what commit
94522ff7f6d2 ("drivers: mmc: Fix R3 response type
definition") does for R3 response.
With this fix, Poplar is back to work.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Shawn Guo [Thu, 27 Sep 2018 08:48:00 +0000 (16:48 +0800)]
poplar: fix build error with POPLAR_RECOVERY=1
Commit
eba1b6b3c724 ("plat/poplar: migrate to mmc framework") defines
variable 'info' without !POPLAR_RECOVERY protection, and hence causes
the following unused variable error with POPLAR_RECOVERY=1 build.
plat/hisilicon/poplar/bl1_plat_setup.c: In function ‘bl1_platform_setup’:
plat/hisilicon/poplar/bl1_plat_setup.c:95:25: error: unused variable ‘info’ [-Werror=unused-variable]
struct mmc_device_info info;
^~~~
The patches fixes the build error with POPLAR_RECOVERY=1.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Elieva Pignat [Mon, 24 Sep 2018 13:30:36 +0000 (14:30 +0100)]
sgm: increase SCP_BL2 maximum size
For sgm775 the SCP_BL2 build in debug mode is around 94KiB which
is higher than the maximum size for SCP_BL2.
This patch increase the maximum allowed size for SCP_BL2 to
96KiB.
Change-Id: Ibca0daadba41429301c651ae21cbba87e45ccddf
Signed-off-by: Elieva Pignat <Elieva.Pignat@arm.com>
Soby Mathew [Fri, 21 Sep 2018 12:15:34 +0000 (13:15 +0100)]
Merge pull request #1585 from sandrine-bailleux-arm/sb/doc-fixes
Minor documentation fixes
Soby Mathew [Fri, 21 Sep 2018 12:15:05 +0000 (13:15 +0100)]
Merge pull request #1581 from satheesbalya-arm/sb1_update_minor_version
Update release minor version string
Soby Mathew [Fri, 21 Sep 2018 12:14:33 +0000 (13:14 +0100)]
Merge pull request #1580 from joannafarley-arm/jf/release-1.6-changelogs-Readme
Readme and Change-log updates for v1.6 release
Soby Mathew [Fri, 21 Sep 2018 09:46:22 +0000 (10:46 +0100)]
Merge pull request #1578 from Yann-lms/par_addr_mask_64
aarch32: PAR_ADDR_MASK should explicitly use BIT_64
Sathees Balya [Fri, 21 Sep 2018 09:41:13 +0000 (10:41 +0100)]
Update release minor version string
Change-Id: I67382383fc9d18ab57c7e51f793145cb14c6fec5
Signed-off-by: Sathees Balya <sathees.balya@arm.com>
Joanna Farley [Tue, 11 Sep 2018 14:51:31 +0000 (15:51 +0100)]
Readme and Change-log updates for v1.6 release
Change-Id: I7855c9d3de104975bf3249bdf291c428f001d07a
Signed-off-by: Joanna Farley <joanna.farley@arm.com>
Yann Gautier [Thu, 20 Sep 2018 13:48:52 +0000 (15:48 +0200)]
aarch32: PAR_ADDR_MASK should explicitly use BIT_64
PAR register used here is a 64 bit register.
On AARCH32 BIT macro is BIT_32.
PAR_ADDR_MASK should then use BIT_64 to avoid overflow.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Sandrine Bailleux [Thu, 20 Sep 2018 10:44:39 +0000 (12:44 +0200)]
User guide: Document ENABLE_SPM build flag
Change-Id: Ib9a045200de4fcd00387b114cbbd006e46ad6a8b
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Sandrine Bailleux [Thu, 20 Sep 2018 08:27:13 +0000 (10:27 +0200)]
User guide: Fix link to Linux master tree
Change-Id: Ia67a4786350c1c2ef55125cd6a318ae6d918c08e
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Soby Mathew [Wed, 19 Sep 2018 09:50:46 +0000 (10:50 +0100)]
Merge pull request #1570 from Andre-ARM/allwinner/pmic-fixes
Allwinner PMIC fixes
Andre Przywara [Sun, 9 Sep 2018 00:39:57 +0000 (01:39 +0100)]
drivers: i2c: mentor: move platform code into header files
At the moment we have two I2C stub drivers (for the Allwinner and the
Marvell platform), which #include the actual .c driver file.
Change this into the more usual design, by renaming and moving the stub
drivers into platform specific header files and including these from the
actual driver file. The platform specific include directories make sure
the driver picks up the right header automatically.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Soby Mathew [Tue, 18 Sep 2018 14:20:41 +0000 (15:20 +0100)]
Merge pull request #1577 from antonio-nino-diaz-arm/an/trusty
trusty: Fix return value of trusty_init()
Soby Mathew [Tue, 18 Sep 2018 14:20:16 +0000 (15:20 +0100)]
Merge pull request #1576 from antonio-nino-diaz-arm/an/fix-bl32-init
BL31: Fix warning about BL32 init function
Soby Mathew [Tue, 18 Sep 2018 14:19:54 +0000 (15:19 +0100)]
Merge pull request #1575 from soby-mathew/sm/fix_cryptocell_mem
ARM platforms: Reintroduce coherent memory for BL1 and BL2
Antonio Nino Diaz [Tue, 18 Sep 2018 12:13:24 +0000 (13:13 +0100)]
trusty: Fix return value of trusty_init()
The value used to signal failure is 0. It is needed to return a different
value on success.
Change-Id: I2186aa7dfbfc825bfe7b3d5ae3c4de7af10ee44f
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Soby Mathew [Tue, 18 Sep 2018 10:42:42 +0000 (11:42 +0100)]
ARM platforms: Reintroduce coherent memory for BL1 and BL2
The patch
d323af9 removed the support for coherent memory in BL1 and
BL2 for ARM platforms. But the CryptoCell SBROM integration depends
on use of coherent buffers for passing data from the AP CPU to the
CryptoCell. Hence this patch reintroduces support for coherent
memory in BL1 and BL2 if ARM_CRYPTOCELL_INTEG=1.
Change-Id: I011482dda7f7a3ec9e3e79bfb3f4fa03796f7e02
Signed-Off-by: Soby Mathew <soby.mathew@arm.com>
Antonio Nino Diaz [Tue, 18 Sep 2018 12:10:47 +0000 (13:10 +0100)]
BL31: Fix warning about BL32 init function
The expected value for failure is 0, so the warning only has to be shown
in that case. This is the way the TSPD has done it since it was
introduced, and the way SPM and OP-TEE do it.
Trusty wrongly returns 0 on success.
In the case of TLK, the return value of tlkd_init() is passed from the
secure world in register X1 when calling the SMC TLK_ENTRY_DONE.
Change-Id: I39106d67631ee57f109619f8830bf4b9d96155e6
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Andre Przywara [Sat, 8 Sep 2018 23:38:58 +0000 (00:38 +0100)]
allwinner: sun50i_h6: initialise I2C just before powering down
Even though we initialise the platform part and the I2C controller
itself at boot time, we actually only access the bus on power down.
Meanwhile a rich OS might have configured the I2C pins differently or
even disabled the controller.
So repeat the platform setup and controller initialisation just before
we actually access the bus to power off the system. This is safe,
because at this point the rich OS should no longer be running.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Sat, 8 Sep 2018 23:38:19 +0000 (00:38 +0100)]
allwinner: sun50i_h6: improve I2C setup
Drop the unnecessary check for the I2C pins being already configured as
I2C pins (we actually don't care).
Also avoid resetting *every* peripheral that is covered by the PRCM reset
controller, instead just clear the one line connected to the I2C controller.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Dimitris Papastamos [Wed, 12 Sep 2018 10:19:05 +0000 (11:19 +0100)]
Merge pull request #1572 from iq250vip/tf_log
Allow setting log level back to compile time value
Junhan Zhou [Mon, 10 Sep 2018 20:36:06 +0000 (16:36 -0400)]
Allow setting log level back to compile time value
When using the tf_log_set_max_level() function, one can dynamically
set the log level to a value smaller than then compile time specified
one, but not equal. This means that when the log level have been
lowered, it can't be reset to the previous value. This commit modifies
this function to allow setting the log level back to the compile time
value.
Fixes ARM-software/tf-issues#624
Change-Id: Ib157715c8835982ce4977ba67a48e18ff23d5a61
Signed-off-by: Junhan Zhou <Junhan@mellanox.com>
Dimitris Papastamos [Tue, 11 Sep 2018 13:46:04 +0000 (14:46 +0100)]
Merge pull request #1571 from jeenu-arm/deps
Update dependencies for ARM TF
David Cunado [Tue, 19 Dec 2017 16:33:25 +0000 (16:33 +0000)]
Update dependencies for ARM TF
- Linaro binaries: 18.04
- mbed TLS library: 2.12.0
- FVP model versions: 11.4 build 37
This patch updates the user guide documentation to reflect these
changes to the dependencies.
Change-Id: I454782ca43a0db43aeeef2ab3622f4dea9dfec55
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
Soby Mathew [Mon, 10 Sep 2018 11:44:56 +0000 (12:44 +0100)]
Merge pull request #1569 from soby-mathew/sm/cov_fix_scmi
CSS: Fix overrun if system power level is not available
Soby Mathew [Mon, 10 Sep 2018 11:44:38 +0000 (12:44 +0100)]
Merge pull request #1568 from soby-mathew/sm/fix_ares_err_report
Fix the Cortex-ares errata reporting function name
Soby Mathew [Mon, 10 Sep 2018 10:14:01 +0000 (11:14 +0100)]
Fix the Cortex-ares errata reporting function name
This patch fixes the name of the Cortex-ares errata function which was
previously named `cortex_a72_errata_report` which was an error.
Change-Id: Ia124df4628261021baa8d9a30308bc286d45712b
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
Soby Mathew [Mon, 10 Sep 2018 10:32:49 +0000 (11:32 +0100)]
CSS: Fix overrun if system power level is not available
This patch fixes an array overrun in CSS scmi driver if the
system power domain level is less than 2. This was reported from
https://scan.coverity.com/projects/arm-software-arm-trusted-firmware
CID 308492
Change-Id: I3a59c700490816718d20c71141281f19b2b7e7f7
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
Soby Mathew [Mon, 10 Sep 2018 10:10:12 +0000 (11:10 +0100)]
Merge pull request #1555 from theopolis/tbb-hikey960
hikey960: Add development TBB support
Soby Mathew [Mon, 10 Sep 2018 10:06:16 +0000 (11:06 +0100)]
Merge pull request #1534 from Icenowy/sun50i_h6_pmic
Add support for Allwinner H6 + X-Powers AXP805 PMIC combination
Teddy Reed [Mon, 3 Sep 2018 21:38:50 +0000 (17:38 -0400)]
hikey960: Add development TBB support
This patch adds experimental support for TBB to the HiKey960 board. To
build and test with TBB modify the uefi-tools project platforms.config
+ATF_BUILDFLAGS=TRUSTED_BOARD_BOOT=1 GENERATE_COT=1 SAVE_KEYS=1 \
MBEDTLS_DIR=./mbedtls
Signed-off-by: Teddy Reed <teddy@casualhacking.io>
Dimitris Papastamos [Sat, 8 Sep 2018 23:36:02 +0000 (00:36 +0100)]
Merge pull request #1567 from jeenu-arm/ras-fix
RAS: Fix assert condition
Jeenu Viswambharan [Fri, 7 Sep 2018 15:30:58 +0000 (16:30 +0100)]
RAS: Fix assert condition
Change-Id: Ia02a2dbfd4e25547776e78bed40a91f3452553d7
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
Soby Mathew [Fri, 7 Sep 2018 15:34:02 +0000 (16:34 +0100)]
Merge pull request #1566 from EvanLloyd/non_secure_uart
ARM Platforms:Enable non-secure access to UART1
Icenowy Zheng [Sun, 22 Jul 2018 13:52:50 +0000 (21:52 +0800)]
allwinner: implement system power down on H6 w/ AXP805
The AXP805 PMIC used with H6 is capable of shutting down the system.
Add support for using it to shut down the system power.
The original placeholder power off code is moved to A64 code, as it's
still TODO to implement PMIC operations for A64.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Icenowy Zheng [Sun, 22 Jul 2018 13:30:14 +0000 (21:30 +0800)]
allwinner: sun50i_h6: add initial AXP805 PMIC code
The OTT reference design of Allwinner H6 SoC uses an X-Powers AXP805
PMIC.
Add initial code for it.
Currently it's only detected.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Dimitris Papastamos [Fri, 7 Sep 2018 15:01:03 +0000 (16:01 +0100)]
Merge pull request #1565 from satheesbalya-arm/sb1_2332_fwu_sds_register
juno: Revert FWU update detect mechanism
Icenowy Zheng [Sun, 22 Jul 2018 13:29:02 +0000 (21:29 +0800)]
allwinner: add I2C glue driver
Allwinner 64-bit SoCs all use the Mentor Graphics MI2CV I2C controller
core, with inverted clear quirk.
Add a glue driver for this.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Icenowy Zheng [Sun, 22 Jul 2018 13:27:30 +0000 (21:27 +0800)]
drivers: mentor: mi2cv: add inverted interrupt clear flag quirk
The I2C controller on Allwinner SoCs after A31 has a inverted interrupt
clear flag, which needs to be written 1 (rather than 0 on Marvell SoCs
and old Allwinner SoCs) to clear.
Add such a quirk to mi2cv driver common code.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Icenowy Zheng [Sat, 21 Jul 2018 12:41:12 +0000 (20:41 +0800)]
allwinner: call PMIC setup code
As the ATF may need to do some power initialization on Allwinner
platform with AXP PMICs, call the PMIC setup code in BL31.
Stub of PMIC setup code is added, to prevent undefined reference.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Dimitris Papastamos [Fri, 7 Sep 2018 14:05:54 +0000 (15:05 +0100)]
Merge pull request #1563 from jts-arm/mbed
Improvements to Mbed TLS shared heap code
Dimitris Papastamos [Fri, 7 Sep 2018 14:05:28 +0000 (15:05 +0100)]
Merge pull request #1564 from jeenu-arm/sdei-suspend
SDEI: Mask events after CPU wakeup
Sathees Balya [Mon, 3 Sep 2018 16:41:13 +0000 (17:41 +0100)]
juno: Revert FWU update detect mechanism
The patch
7b56928 unified the FWU mechanism on FVP and Juno
platforms due to issues with MCC firmware not preserving the
NVFLAGS. With MCCv150 firmware, this issue is resolved. Also
writing to the NOR flash while executing from the same flash
in Bypass mode had some stability issues. Hence, since the
MCC firmware issue is resolved, this patch reverts to the
NVFLAGS mechanism to detect FWU. Also, with the introduction
of SDS (Shared Data Structure) by the SCP, the reset syndrome
needs to queried from the appropriate SDS field.
Change-Id: If9c08f1afaaa4fcf197f3186887068103855f554
Signed-off-by: Sathees Balya <sathees.balya@arm.com>
Signed-off-by: Soby Mathew <Soby.Mathew@arm.com>
John Tsichritzis [Fri, 7 Sep 2018 13:05:41 +0000 (14:05 +0100)]
Readjust BL2 size after sharing Mbed TLS heap
After introducing the Mbed TLS shared heap optimisation, reducing BL2
size by 3 pages didn't leave enough space for growth. We give 1 page
back to maximum BL2 size.
Change-Id: I4f05432f00b923693160f69a4e4ec310a37a2b16
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
Alexei Fedorov [Thu, 25 May 2017 14:57:18 +0000 (15:57 +0100)]
ARM Platforms:Enable non-secure access to UART1
Adds an undocumented build option that enables non-secure access to
the PL011 UART1.
This allows a custom build where the UART can be used as a serial debug
port for WinDbg (or other debugger) connection.
This option is not documented in the user guide, as it is provided as a
convenience for Windows debugging, and not intended for general use.
In particular, enabling non-secure access to the UART might allow
a denial of service attack!
Change-Id: I4cd7d59c2cac897cc654ab5e1188ff031114ed3c
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
Signed-off-by: Evan Lloyd <evan.lloyd@arm.com>
John Tsichritzis [Fri, 7 Sep 2018 09:52:12 +0000 (10:52 +0100)]
Add cache flush after BL1 writes heap info to DTB
A cache flush is added in BL1, in Mbed TLS shared heap code. Thus, we
ensure that the heap info written to the DTB always gets written back to
memory. Hence, sharing this info with other images is guaranteed.
Change-Id: I0faada31fe7a83854cd5e2cf277ba519e3f050d5
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
John Tsichritzis [Fri, 7 Sep 2018 09:42:37 +0000 (10:42 +0100)]
Additional runtime check for DTB presence in BL2
In Mbed TLS shared heap code, an additional sanity check is introduced
in BL2. Currently, when BL2 shares heap with BL1, it expects the heap
info to be found in the DTB. If for any reason the DTB is missing, BL2
cannot have the heap address and, hence, Mbed TLS cannot proceed. So,
BL2 cannot continue executing and it will eventually crash. With this
change we ensure that if the DTB is missing BL2 will panic() instead of
having an unpredictable crash.
Change-Id: I3045ae43e54b7fe53f23e7c2d4d00e3477b6a446
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
John Tsichritzis [Fri, 7 Sep 2018 09:38:01 +0000 (10:38 +0100)]
Slight improvements in Mbed TLS shared heap helpers
This patch, firstly, makes the error messages consistent to how printed
strings are usually formatted. Secondly, it removes an unnecessary #if
directive.
Change-Id: Idbb8ef0070562634766b683ac65f8160c9d109e6
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
Dimitris Papastamos [Fri, 7 Sep 2018 08:54:33 +0000 (09:54 +0100)]
Merge pull request #1562 from antonio-nino-diaz-arm/an/bl31-warn
Convert BL31 error message into warning
Jeenu Viswambharan [Thu, 1 Feb 2018 08:05:36 +0000 (08:05 +0000)]
SDEI: Mask events after CPU wakeup
The specification requires that, after wakeup from a CPU suspend, the
dispatcher must mask all events on the CPU. This patch adds the feature
to the SDEI dispatcher by subscribing to the PSCI suspend to power down
event, and masking all events on the PE.
Change-Id: I9fe1d1bc2a58379ba7bba953a8d8b275fc18902c
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
Antonio Nino Diaz [Thu, 6 Sep 2018 15:47:35 +0000 (16:47 +0100)]
Convert BL31 error message into warning
If BL32 isn't present or it fails to initialize the current code prints
an error message in both debug and release builds. This is too verbose
for release builds, so it has been converted into a warning.
Also, it was missing a newline at the end of the message.
Change-Id: I91e18d5d5864dbb19d47ecd54f174d2d8c06296c
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Icenowy Zheng [Sat, 21 Jul 2018 11:06:46 +0000 (19:06 +0800)]
drivers: mentor: extract MI2CV driver from Marvell driver
The Marvell A8K SoCs use the MI2CV IP core from Mentor Graphics, which
is also used by Allwinner.
As Mentor Graphics allows a lot of customization, the MI2CV in the two
SoC families are not compatible, and driver modifications are needed.
Extract the common code to a MI2CV driver.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Icenowy Zheng [Sat, 21 Jul 2018 10:19:43 +0000 (18:19 +0800)]
marvell: drivers: use anonymous union in I2C driver
The I2C controller found in Marvell A8K SoCs (and some older SoCs) mux
status and baudrate registers into the same address, however, it's a
vendor customization, and the original IP core by Mentor Graphics uses
two different addresses for the two registers.
Use anonymous union in the driver, in order to ease code sharing for
other SoC vendors that use this IP core (Allwinner SoCs that are newly
introduced to mainline ATF use this core).
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Dimitris Papastamos [Wed, 5 Sep 2018 14:42:15 +0000 (15:42 +0100)]
Merge pull request #1561 from jeenu-arm/bakery-barrier
Add missing barriers to Bakery Locks
Dimitris Papastamos [Wed, 5 Sep 2018 13:41:53 +0000 (14:41 +0100)]
Merge pull request #1558 from jenswi-linaro/qemu-update
Qemu updates
Jeenu Viswambharan [Wed, 8 Aug 2018 13:10:55 +0000 (14:10 +0100)]
Add missing barriers to Bakery Locks
With the current implementation, it's possible for a contender to
observe accesses in the Critical Section before acquiring or releasing
the lock. Insert fencing in the locking and release codes to prevent any
reorder.
Fixes ARM-software/tf-issues#609
Change-Id: I773b82aa41dd544a2d3dbacb9a4b42c9eb767bbb
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
Jeenu Viswambharan [Wed, 5 Sep 2018 13:23:27 +0000 (14:23 +0100)]
ARMv7: Alias dmbld() to dmb()
'dmb ld' is not a recognized instruction for ARMv7. Since generic code
may use 'dmb ld', alias it to 'dmb' when building for ARMv7.
Change-Id: I502f360cb6412897ca9580b725d9f79469a7612e
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
Dimitris Papastamos [Wed, 5 Sep 2018 11:20:10 +0000 (12:20 +0100)]
Merge pull request #1515 from bryanodonoghue/atf-master+linaro-warp7-squash-v4
Atf master+linaro warp7 squash v4
Dimitris Papastamos [Wed, 5 Sep 2018 11:19:03 +0000 (12:19 +0100)]
Merge pull request #1554 from jts-arm/mbed
Mbed TLS shared heap
Dimitris Papastamos [Wed, 5 Sep 2018 11:18:37 +0000 (12:18 +0100)]
Merge pull request #1560 from vwadekar/denver-fixes-918
Recent Denver CPU fixes from downstream
Dimitris Papastamos [Wed, 5 Sep 2018 11:18:01 +0000 (12:18 +0100)]
Merge pull request #1557 from sivadur/integration
Xilinx latest platform related changes
Dimitris Papastamos [Wed, 5 Sep 2018 10:31:19 +0000 (11:31 +0100)]
Merge pull request #1556 from jts-arm/docs
Fix broken links in documentation
Varun Wadekar [Tue, 28 Aug 2018 16:11:30 +0000 (09:11 -0700)]
cpus: denver: Implement static workaround for CVE-2018-3639
For Denver CPUs, this approach enables the mitigation during EL3
initialization, following every PE reset. No mechanism is provided to
disable the mitigation at runtime.
This approach permanently mitigates the EL3 software stack only. Other
software components are responsible to enable it for their exception
levels.
TF-A implements this approach for the Denver CPUs with DENVER_MIDR_PN3
and earlier:
* By setting bit 11 (Disable speculative store buffering) of
`ACTLR_EL3`
* By setting bit 9 (Disable speculative memory disambiguation) of
`ACTLR_EL3`
TF-A implements this approach for the Denver CPUs with DENVER_MIDR_PN4
and later:
* By setting bit 18 (Disable speculative store buffering) of
`ACTLR_EL3`
* By setting bit 17 (Disable speculative memory disambiguation) of
`ACTLR_EL3`
Change-Id: If1de96605ce3f7b0aff5fab2c828e5aecb687555
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Varun Wadekar [Mon, 25 Jun 2018 18:36:47 +0000 (11:36 -0700)]
cpus: denver: reset power state to 'C1' on boot
Denver CPUs expect the power state field to be reset to 'C1'
during boot. This patch updates the reset handler to reset the
ACTLR_.PMSTATE field to 'C1' state during CPU boot.
Change-Id: I7cb629627a4dd1a30ec5cbb3a5e90055244fe30c
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Varun Wadekar [Wed, 28 Feb 2018 02:30:31 +0000 (18:30 -0800)]
denver: use plat_my_core_pos() to get core position
The current functions to disable and enable Dynamic Code Optimizer
(DCO) assume that all denver cores are in the same cluster. They
ignore AFF1 field of the mpidr_el1 register, which leads to
incorect logical core id calculation.
This patch calls the platform handler, plat_my_core_pos(), to get
the logical core id to disable/enable DCO for the core.
Original change by: Krishna Sitaraman <ksitaraman@nvidia.com>
Change-Id: I45fbd1f1eb032cc1db677a4fdecc554548b4a830
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Bryan O'Donoghue [Mon, 23 Jul 2018 14:59:47 +0000 (15:59 +0100)]
maintainers: Add entries for imx7/WaARP7 and associated shared code
This patch adds me to various maintainer activities in the ATF tree
associated with the NXP i.MX7 generally and WaARP7 in particular.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Bryan O'Donoghue [Mon, 23 Jul 2018 13:27:59 +0000 (14:27 +0100)]
docs: warp7: Add description for the i.MX7 WaRP7 platform
This patch describes the boot-flow and building of the WaRP7 TF-A port.
What it describes is booting and unsigned TF-A.
A very brief section has been added on signing BL2 which is in no-way
comprehensive. For a comprehensive description of the signing process try
the Boundary Devices blog on the matter.
https://boundarydevices.com/high-assurance-boot-hab-dummies/
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Jens Wiklander [Tue, 4 Sep 2018 12:07:19 +0000 (14:07 +0200)]
plat: qemu: update the early platform setup API
Replaces deprecated early platform setup APIs
* Replaces bl31_early_platform_setup() with bl31_early_platform_setup2()
* Replaces bl2_early_platform_setup() with bl2_early_platform_setup2()
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Bryan O'Donoghue [Fri, 27 Jul 2018 12:50:15 +0000 (13:50 +0100)]
warp7: Add warp7 platform to the build
Previous changes in this series made the necessary driver additions and
updates. With those changes in-place we can add the platform.mk and
bl2_el3_setup.c to drive the boot process.
After this commit its possible to build a fully-functional TF-A for the
WaRP7 and boot from the BootROM to the Linux command prompt in secure or
non-secure mode.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Bryan O'Donoghue [Wed, 4 Jul 2018 12:16:35 +0000 (13:16 +0100)]
warp7: panic: hab: Call into BootROM failsafe on panic path
This patch adds a callback into the BootROM's provided High Assurance Boot
(HAB) failsafe function when panicking i.e. the call is done without making
use of stack.
The HAB failsafe function allows a piece of software to call into the
BootROM and place the processor into failsafe mode.
Failsafe mode is a special mode which presents a serial download protocol
interface over UART or USB at the time of writing.
If the board has been set into secure mode, then only a signed binary can
be used to recover the board.
Thus failsafe gives a putatively secure method of performing a secure
recovery over UART or USB.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Ryan Harkin <ryan.harkin@linaro.org>
Bryan O'Donoghue [Mon, 11 Jun 2018 12:39:20 +0000 (13:39 +0100)]
warp7: mem_params_desc: Add boot entries to mem params array
This patch adds entries to the mem params array for
- BL32
- BL32_EXTRA1
- BL32_EXTRA2
- BL33
- HW_CONFIG_ID
BL32 is marked as bootable to indicate that OPTEE is the thing that should
be booted next.
In our model OPTEE chain-loads onto u-boot so only BL32 is bootable.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Bryan O'Donoghue [Thu, 24 May 2018 12:00:57 +0000 (13:00 +0100)]
warp7: io_storage: Add initial stub warp7_io_storage.c
This commit adds support for parsing a FIP pre-loaded by a previous
boot-phase such as u-boot or via ATF reading directly from eMMC.
[bod: squashing several patches from Rui, Jun and bod]
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Jun Nie <jun.nie@linaro.org>
Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Bryan O'Donoghue [Fri, 25 May 2018 16:54:01 +0000 (17:54 +0100)]
warp7: Define a platform_def.h
This patch defines a platform_def.h describing
- FIP layout and location
- eMMC device select
- UART identity select
- System clock frequency
- Operational memory map
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>
Signed-off-by: Jun Nie <jun.nie@linaro.org>
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Bryan O'Donoghue [Fri, 25 May 2018 16:20:50 +0000 (17:20 +0100)]
warp7: mem_params_desc: Add a file which exports a REGISTER_BL_IMAGE_DESCS
In order to link even a basic image we need to declare
REGISTER_BL_IMAGE_DESCS. This patch declares an empty structure which is
passed to REGISTER_BL_IMAGE_DESCS(). Later patches will add in some
meaningful data.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Bryan O'Donoghue [Fri, 25 May 2018 16:18:56 +0000 (17:18 +0100)]
warp7: Add a warp7_private.h file
Internal declarations for the WaRP7 port will go here. For now just include
sys/types.h.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Bryan O'Donoghue [Thu, 24 May 2018 18:38:11 +0000 (19:38 +0100)]
warp7: image_load: Add warp7_image_load.c
This commit adds warp7_image_load.c with the functions
- plat_flush_next_bl_params()
- plat_get_bl_image_load_info()
- plat_get_next_bl_params()
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Bryan O'Donoghue [Thu, 24 May 2018 18:32:52 +0000 (19:32 +0100)]
warp7: Add initial warp7_helpers.S
This commit adds a warp7_helpers.S which contains a implementation of:
- platform_mem_init
- plat_get_my_entrypoint
- plat_crash_console_init
- plat_crash_console_putc
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Bryan O'Donoghue [Fri, 25 May 2018 15:45:27 +0000 (16:45 +0100)]
imx: imx_wdog: Add code to initialize the wdog block
The watchdog block on the IMX is mercifully simple. This patch maps the
various registers and bits associated with the block.
We are mostly only really interested in the power-down-enable (PDE) bits in
the block for the purposes of ATF.
The i.MX7 Solo Applications Processor Reference Manual details the PDE bit
as follows:
"Power Down Enable bit. Reset value of this bit is 1, which means the power
down counter inside the WDOG is enabled after reset. The software must
write 0 to this bit to disable the counter within 16 seconds of reset
de-assertion. Once disabled this counter cannot be enabled again. See
Power-down counter event for operation of this counter."
This patch does that zero write in-lieu of later phases in the boot
no-longer have the necessary permissions to rewrite the PDE bit directly.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>