project/bcm63xx/atf.git
6 years agoUpdate dependencies for ARM TF
David Cunado [Tue, 19 Dec 2017 16:33:25 +0000 (16:33 +0000)]
Update dependencies for ARM TF

- Linaro binaries:    18.04
- mbed TLS library:   2.12.0
- FVP model versions: 11.4 build 37

This patch updates the user guide documentation to reflect these
changes to the dependencies.

Change-Id: I454782ca43a0db43aeeef2ab3622f4dea9dfec55
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
6 years agoMerge pull request #1569 from soby-mathew/sm/cov_fix_scmi
Soby Mathew [Mon, 10 Sep 2018 11:44:56 +0000 (12:44 +0100)]
Merge pull request #1569 from soby-mathew/sm/cov_fix_scmi

CSS: Fix overrun if system power level is not available

6 years agoMerge pull request #1568 from soby-mathew/sm/fix_ares_err_report
Soby Mathew [Mon, 10 Sep 2018 11:44:38 +0000 (12:44 +0100)]
Merge pull request #1568 from soby-mathew/sm/fix_ares_err_report

Fix the Cortex-ares errata reporting function name

6 years agoFix the Cortex-ares errata reporting function name
Soby Mathew [Mon, 10 Sep 2018 10:14:01 +0000 (11:14 +0100)]
Fix the Cortex-ares errata reporting function name

This patch fixes the name of the Cortex-ares errata function which was
previously named `cortex_a72_errata_report` which was an error.

Change-Id: Ia124df4628261021baa8d9a30308bc286d45712b
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
6 years agoCSS: Fix overrun if system power level is not available
Soby Mathew [Mon, 10 Sep 2018 10:32:49 +0000 (11:32 +0100)]
CSS: Fix overrun if system power level is not available

This patch fixes an array overrun in CSS scmi driver if the
system power domain level is less than 2. This was reported from
https://scan.coverity.com/projects/arm-software-arm-trusted-firmware

CID 308492

Change-Id: I3a59c700490816718d20c71141281f19b2b7e7f7
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
6 years agoMerge pull request #1555 from theopolis/tbb-hikey960
Soby Mathew [Mon, 10 Sep 2018 10:10:12 +0000 (11:10 +0100)]
Merge pull request #1555 from theopolis/tbb-hikey960

hikey960: Add development TBB support

6 years agoMerge pull request #1534 from Icenowy/sun50i_h6_pmic
Soby Mathew [Mon, 10 Sep 2018 10:06:16 +0000 (11:06 +0100)]
Merge pull request #1534 from Icenowy/sun50i_h6_pmic

Add support for Allwinner H6 + X-Powers AXP805 PMIC combination

6 years agohikey960: Add development TBB support
Teddy Reed [Mon, 3 Sep 2018 21:38:50 +0000 (17:38 -0400)]
hikey960: Add development TBB support

This patch adds experimental support for TBB to the HiKey960 board. To
build and test with TBB modify the uefi-tools project platforms.config

+ATF_BUILDFLAGS=TRUSTED_BOARD_BOOT=1 GENERATE_COT=1 SAVE_KEYS=1 \
  MBEDTLS_DIR=./mbedtls

Signed-off-by: Teddy Reed <teddy@casualhacking.io>
6 years agoMerge pull request #1567 from jeenu-arm/ras-fix
Dimitris Papastamos [Sat, 8 Sep 2018 23:36:02 +0000 (00:36 +0100)]
Merge pull request #1567 from jeenu-arm/ras-fix

RAS: Fix assert condition

6 years agoRAS: Fix assert condition
Jeenu Viswambharan [Fri, 7 Sep 2018 15:30:58 +0000 (16:30 +0100)]
RAS: Fix assert condition

Change-Id: Ia02a2dbfd4e25547776e78bed40a91f3452553d7
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
6 years agoMerge pull request #1566 from EvanLloyd/non_secure_uart
Soby Mathew [Fri, 7 Sep 2018 15:34:02 +0000 (16:34 +0100)]
Merge pull request #1566 from EvanLloyd/non_secure_uart

ARM Platforms:Enable non-secure access to UART1

6 years agoallwinner: implement system power down on H6 w/ AXP805
Icenowy Zheng [Sun, 22 Jul 2018 13:52:50 +0000 (21:52 +0800)]
allwinner: implement system power down on H6 w/ AXP805

The AXP805 PMIC used with H6 is capable of shutting down the system.

Add support for using it to shut down the system power.

The original placeholder power off code is moved to A64 code, as it's
still TODO to implement PMIC operations for A64.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
6 years agoallwinner: sun50i_h6: add initial AXP805 PMIC code
Icenowy Zheng [Sun, 22 Jul 2018 13:30:14 +0000 (21:30 +0800)]
allwinner: sun50i_h6: add initial AXP805 PMIC code

The OTT reference design of Allwinner H6 SoC uses an X-Powers AXP805
PMIC.

Add initial code for it.

Currently it's only detected.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
6 years agoMerge pull request #1565 from satheesbalya-arm/sb1_2332_fwu_sds_register
Dimitris Papastamos [Fri, 7 Sep 2018 15:01:03 +0000 (16:01 +0100)]
Merge pull request #1565 from satheesbalya-arm/sb1_2332_fwu_sds_register

juno: Revert FWU update detect mechanism

6 years agoallwinner: add I2C glue driver
Icenowy Zheng [Sun, 22 Jul 2018 13:29:02 +0000 (21:29 +0800)]
allwinner: add I2C glue driver

Allwinner 64-bit SoCs all use the Mentor Graphics MI2CV I2C controller
core, with inverted clear quirk.

Add a glue driver for this.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
6 years agodrivers: mentor: mi2cv: add inverted interrupt clear flag quirk
Icenowy Zheng [Sun, 22 Jul 2018 13:27:30 +0000 (21:27 +0800)]
drivers: mentor: mi2cv: add inverted interrupt clear flag quirk

The I2C controller on Allwinner SoCs after A31 has a inverted interrupt
clear flag, which needs to be written 1 (rather than 0 on Marvell SoCs
and old Allwinner SoCs) to clear.

Add such a quirk to mi2cv driver common code.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
6 years agoallwinner: call PMIC setup code
Icenowy Zheng [Sat, 21 Jul 2018 12:41:12 +0000 (20:41 +0800)]
allwinner: call PMIC setup code

As the ATF may need to do some power initialization on Allwinner
platform with AXP PMICs, call the PMIC setup code in BL31.

Stub of PMIC setup code is added, to prevent undefined reference.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
6 years agoMerge pull request #1563 from jts-arm/mbed
Dimitris Papastamos [Fri, 7 Sep 2018 14:05:54 +0000 (15:05 +0100)]
Merge pull request #1563 from jts-arm/mbed

Improvements to Mbed TLS shared heap code

6 years agoMerge pull request #1564 from jeenu-arm/sdei-suspend
Dimitris Papastamos [Fri, 7 Sep 2018 14:05:28 +0000 (15:05 +0100)]
Merge pull request #1564 from jeenu-arm/sdei-suspend

SDEI: Mask events after CPU wakeup

6 years agojuno: Revert FWU update detect mechanism
Sathees Balya [Mon, 3 Sep 2018 16:41:13 +0000 (17:41 +0100)]
juno: Revert FWU update detect mechanism

The patch 7b56928 unified the FWU mechanism on FVP and Juno
platforms due to issues with MCC firmware not preserving the
NVFLAGS. With MCCv150 firmware, this issue is resolved. Also
writing to the NOR flash while executing from the same flash
in Bypass mode had some stability issues. Hence, since the
MCC firmware issue is resolved, this patch reverts to the
NVFLAGS mechanism to detect FWU. Also, with the introduction
of SDS (Shared Data Structure) by the SCP, the reset syndrome
needs to queried from the appropriate SDS field.

Change-Id: If9c08f1afaaa4fcf197f3186887068103855f554
Signed-off-by: Sathees Balya <sathees.balya@arm.com>
Signed-off-by: Soby Mathew <Soby.Mathew@arm.com>
6 years agoReadjust BL2 size after sharing Mbed TLS heap
John Tsichritzis [Fri, 7 Sep 2018 13:05:41 +0000 (14:05 +0100)]
Readjust BL2 size after sharing Mbed TLS heap

After introducing the Mbed TLS shared heap optimisation, reducing BL2
size by 3 pages didn't leave enough space for growth. We give 1 page
back to maximum BL2 size.

Change-Id: I4f05432f00b923693160f69a4e4ec310a37a2b16
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
6 years agoARM Platforms:Enable non-secure access to UART1
Alexei Fedorov [Thu, 25 May 2017 14:57:18 +0000 (15:57 +0100)]
ARM Platforms:Enable non-secure access to UART1

Adds an undocumented build option that enables non-secure access to
the PL011 UART1.
This allows a custom build where the UART can be used as a serial debug
port for WinDbg (or other debugger) connection.

This option is not documented in the user guide, as it is provided as a
convenience for Windows debugging, and not intended for general use.
In particular, enabling non-secure access to the UART might allow
a denial of service attack!

Change-Id: I4cd7d59c2cac897cc654ab5e1188ff031114ed3c
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
Signed-off-by: Evan Lloyd <evan.lloyd@arm.com>
6 years agoAdd cache flush after BL1 writes heap info to DTB
John Tsichritzis [Fri, 7 Sep 2018 09:52:12 +0000 (10:52 +0100)]
Add cache flush after BL1 writes heap info to DTB

A cache flush is added in BL1, in Mbed TLS shared heap code. Thus, we
ensure that the heap info written to the DTB always gets written back to
memory.  Hence, sharing this info with other images is guaranteed.

Change-Id: I0faada31fe7a83854cd5e2cf277ba519e3f050d5
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
6 years agoAdditional runtime check for DTB presence in BL2
John Tsichritzis [Fri, 7 Sep 2018 09:42:37 +0000 (10:42 +0100)]
Additional runtime check for DTB presence in BL2

In Mbed TLS shared heap code, an additional sanity check is introduced
in BL2. Currently, when BL2 shares heap with BL1, it expects the heap
info to be found in the DTB. If for any reason the DTB is missing, BL2
cannot have the heap address and, hence, Mbed TLS cannot proceed. So,
BL2 cannot continue executing and it will eventually crash.  With this
change we ensure that if the DTB is missing BL2 will panic() instead of
having an unpredictable crash.

Change-Id: I3045ae43e54b7fe53f23e7c2d4d00e3477b6a446
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
6 years agoSlight improvements in Mbed TLS shared heap helpers
John Tsichritzis [Fri, 7 Sep 2018 09:38:01 +0000 (10:38 +0100)]
Slight improvements in Mbed TLS shared heap helpers

This patch, firstly, makes the error messages consistent to how printed
strings are usually formatted. Secondly, it removes an unnecessary #if
directive.

Change-Id: Idbb8ef0070562634766b683ac65f8160c9d109e6
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
6 years agoMerge pull request #1562 from antonio-nino-diaz-arm/an/bl31-warn
Dimitris Papastamos [Fri, 7 Sep 2018 08:54:33 +0000 (09:54 +0100)]
Merge pull request #1562 from antonio-nino-diaz-arm/an/bl31-warn

Convert BL31 error message into warning

6 years agoSDEI: Mask events after CPU wakeup
Jeenu Viswambharan [Thu, 1 Feb 2018 08:05:36 +0000 (08:05 +0000)]
SDEI: Mask events after CPU wakeup

The specification requires that, after wakeup from a CPU suspend, the
dispatcher must mask all events on the CPU. This patch adds the feature
to the SDEI dispatcher by subscribing to the PSCI suspend to power down
event, and masking all events on the PE.

Change-Id: I9fe1d1bc2a58379ba7bba953a8d8b275fc18902c
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
6 years agoConvert BL31 error message into warning
Antonio Nino Diaz [Thu, 6 Sep 2018 15:47:35 +0000 (16:47 +0100)]
Convert BL31 error message into warning

If BL32 isn't present or it fails to initialize the current code prints
an error message in both debug and release builds. This is too verbose
for release builds, so it has been converted into a warning.

Also, it was missing a newline at the end of the message.

Change-Id: I91e18d5d5864dbb19d47ecd54f174d2d8c06296c
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
6 years agodrivers: mentor: extract MI2CV driver from Marvell driver
Icenowy Zheng [Sat, 21 Jul 2018 11:06:46 +0000 (19:06 +0800)]
drivers: mentor: extract MI2CV driver from Marvell driver

The Marvell A8K SoCs use the MI2CV IP core from Mentor Graphics, which
is also used by Allwinner.

As Mentor Graphics allows a lot of customization, the MI2CV in the two
SoC families are not compatible, and driver modifications are needed.

Extract the common code to a MI2CV driver.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
6 years agomarvell: drivers: use anonymous union in I2C driver
Icenowy Zheng [Sat, 21 Jul 2018 10:19:43 +0000 (18:19 +0800)]
marvell: drivers: use anonymous union in I2C driver

The I2C controller found in Marvell A8K SoCs (and some older SoCs) mux
status and baudrate registers into the same address, however, it's a
vendor customization, and the original IP core by Mentor Graphics uses
two different addresses for the two registers.

Use anonymous union in the driver, in order to ease code sharing for
other SoC vendors that use this IP core (Allwinner SoCs that are newly
introduced to mainline ATF use this core).

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
6 years agoMerge pull request #1561 from jeenu-arm/bakery-barrier
Dimitris Papastamos [Wed, 5 Sep 2018 14:42:15 +0000 (15:42 +0100)]
Merge pull request #1561 from jeenu-arm/bakery-barrier

Add missing barriers to Bakery Locks

6 years agoMerge pull request #1558 from jenswi-linaro/qemu-update
Dimitris Papastamos [Wed, 5 Sep 2018 13:41:53 +0000 (14:41 +0100)]
Merge pull request #1558 from jenswi-linaro/qemu-update

Qemu updates

6 years agoAdd missing barriers to Bakery Locks
Jeenu Viswambharan [Wed, 8 Aug 2018 13:10:55 +0000 (14:10 +0100)]
Add missing barriers to Bakery Locks

With the current implementation, it's possible for a contender to
observe accesses in the Critical Section before acquiring or releasing
the lock. Insert fencing in the locking and release codes to prevent any
reorder.

Fixes ARM-software/tf-issues#609

Change-Id: I773b82aa41dd544a2d3dbacb9a4b42c9eb767bbb
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
6 years agoARMv7: Alias dmbld() to dmb()
Jeenu Viswambharan [Wed, 5 Sep 2018 13:23:27 +0000 (14:23 +0100)]
ARMv7: Alias dmbld() to dmb()

'dmb ld' is not a recognized instruction for ARMv7. Since generic code
may use 'dmb ld', alias it to 'dmb' when building for ARMv7.

Change-Id: I502f360cb6412897ca9580b725d9f79469a7612e
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
6 years agoMerge pull request #1515 from bryanodonoghue/atf-master+linaro-warp7-squash-v4
Dimitris Papastamos [Wed, 5 Sep 2018 11:20:10 +0000 (12:20 +0100)]
Merge pull request #1515 from bryanodonoghue/atf-master+linaro-warp7-squash-v4

Atf master+linaro warp7 squash v4

6 years agoMerge pull request #1554 from jts-arm/mbed
Dimitris Papastamos [Wed, 5 Sep 2018 11:19:03 +0000 (12:19 +0100)]
Merge pull request #1554 from jts-arm/mbed

Mbed TLS shared heap

6 years agoMerge pull request #1560 from vwadekar/denver-fixes-918
Dimitris Papastamos [Wed, 5 Sep 2018 11:18:37 +0000 (12:18 +0100)]
Merge pull request #1560 from vwadekar/denver-fixes-918

Recent Denver CPU fixes from downstream

6 years agoMerge pull request #1557 from sivadur/integration
Dimitris Papastamos [Wed, 5 Sep 2018 11:18:01 +0000 (12:18 +0100)]
Merge pull request #1557 from sivadur/integration

Xilinx latest platform related changes

6 years agoMerge pull request #1556 from jts-arm/docs
Dimitris Papastamos [Wed, 5 Sep 2018 10:31:19 +0000 (11:31 +0100)]
Merge pull request #1556 from jts-arm/docs

Fix broken links in documentation

6 years agocpus: denver: Implement static workaround for CVE-2018-3639
Varun Wadekar [Tue, 28 Aug 2018 16:11:30 +0000 (09:11 -0700)]
cpus: denver: Implement static workaround for CVE-2018-3639

For Denver CPUs, this approach enables the mitigation during EL3
initialization, following every PE reset. No mechanism is provided to
disable the mitigation at runtime.

This approach permanently mitigates the EL3 software stack only. Other
software components are responsible to enable it for their exception
levels.

TF-A implements this approach for the Denver CPUs with DENVER_MIDR_PN3
and earlier:

*   By setting bit 11 (Disable speculative store buffering) of
    `ACTLR_EL3`

*   By setting bit 9 (Disable speculative memory disambiguation) of
    `ACTLR_EL3`

TF-A implements this approach for the Denver CPUs with DENVER_MIDR_PN4
and later:

*   By setting bit 18 (Disable speculative store buffering) of
    `ACTLR_EL3`

*   By setting bit 17 (Disable speculative memory disambiguation) of
    `ACTLR_EL3`

Change-Id: If1de96605ce3f7b0aff5fab2c828e5aecb687555
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
6 years agocpus: denver: reset power state to 'C1' on boot
Varun Wadekar [Mon, 25 Jun 2018 18:36:47 +0000 (11:36 -0700)]
cpus: denver: reset power state to 'C1' on boot

Denver CPUs expect the power state field to be reset to 'C1'
during boot. This patch updates the reset handler to reset the
ACTLR_.PMSTATE field to 'C1' state during CPU boot.

Change-Id: I7cb629627a4dd1a30ec5cbb3a5e90055244fe30c
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
6 years agodenver: use plat_my_core_pos() to get core position
Varun Wadekar [Wed, 28 Feb 2018 02:30:31 +0000 (18:30 -0800)]
denver: use plat_my_core_pos() to get core position

The current functions to disable and enable Dynamic Code Optimizer
(DCO) assume that all denver cores are in the same cluster. They
ignore AFF1 field of the mpidr_el1 register, which leads to
incorect logical core id calculation.

This patch calls the platform handler, plat_my_core_pos(), to get
the logical core id to disable/enable DCO for the core.

Original change by: Krishna Sitaraman <ksitaraman@nvidia.com>

Change-Id: I45fbd1f1eb032cc1db677a4fdecc554548b4a830
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
6 years agomaintainers: Add entries for imx7/WaARP7 and associated shared code
Bryan O'Donoghue [Mon, 23 Jul 2018 14:59:47 +0000 (15:59 +0100)]
maintainers: Add entries for imx7/WaARP7 and associated shared code

This patch adds me to various maintainer activities in the ATF tree
associated with the NXP i.MX7 generally and WaARP7 in particular.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
6 years agodocs: warp7: Add description for the i.MX7 WaRP7 platform
Bryan O'Donoghue [Mon, 23 Jul 2018 13:27:59 +0000 (14:27 +0100)]
docs: warp7: Add description for the i.MX7 WaRP7 platform

This patch describes the boot-flow and building of the WaRP7 TF-A port.
What it describes is booting and unsigned TF-A.

A very brief section has been added on signing BL2 which is in no-way
comprehensive. For a comprehensive description of the signing process try
the Boundary Devices blog on the matter.

https://boundarydevices.com/high-assurance-boot-hab-dummies/

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
6 years agoplat: qemu: update the early platform setup API
Jens Wiklander [Tue, 4 Sep 2018 12:07:19 +0000 (14:07 +0200)]
plat: qemu: update the early platform setup API

Replaces deprecated early platform setup APIs

* Replaces bl31_early_platform_setup() with bl31_early_platform_setup2()
* Replaces bl2_early_platform_setup() with bl2_early_platform_setup2()

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
6 years agowarp7: Add warp7 platform to the build
Bryan O'Donoghue [Fri, 27 Jul 2018 12:50:15 +0000 (13:50 +0100)]
warp7: Add warp7 platform to the build

Previous changes in this series made the necessary driver additions and
updates. With those changes in-place we can add the platform.mk and
bl2_el3_setup.c to drive the boot process.

After this commit its possible to build a fully-functional TF-A for the
WaRP7 and boot from the BootROM to the Linux command prompt in secure or
non-secure mode.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
6 years agowarp7: panic: hab: Call into BootROM failsafe on panic path
Bryan O'Donoghue [Wed, 4 Jul 2018 12:16:35 +0000 (13:16 +0100)]
warp7: panic: hab: Call into BootROM failsafe on panic path

This patch adds a callback into the BootROM's provided High Assurance Boot
(HAB) failsafe function when panicking i.e. the call is done without making
use of stack.

The HAB failsafe function allows a piece of software to call into the
BootROM and place the processor into failsafe mode.

Failsafe mode is a special mode which presents a serial download protocol
interface over UART or USB at the time of writing.

If the board has been set into secure mode, then only a signed binary can
be used to recover the board.

Thus failsafe gives a putatively secure method of performing a secure
recovery over UART or USB.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Ryan Harkin <ryan.harkin@linaro.org>
6 years agowarp7: mem_params_desc: Add boot entries to mem params array
Bryan O'Donoghue [Mon, 11 Jun 2018 12:39:20 +0000 (13:39 +0100)]
warp7: mem_params_desc: Add boot entries to mem params array

This patch adds entries to the mem params array for

- BL32
- BL32_EXTRA1
- BL32_EXTRA2
- BL33
- HW_CONFIG_ID

BL32 is marked as bootable to indicate that OPTEE is the thing that should
be booted next.

In our model OPTEE chain-loads onto u-boot so only BL32 is bootable.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
6 years agowarp7: io_storage: Add initial stub warp7_io_storage.c
Bryan O'Donoghue [Thu, 24 May 2018 12:00:57 +0000 (13:00 +0100)]
warp7: io_storage: Add initial stub warp7_io_storage.c

This commit adds support for parsing a FIP pre-loaded by a previous
boot-phase such as u-boot or via ATF reading directly from eMMC.

[bod: squashing several patches from Rui, Jun and bod]

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Jun Nie <jun.nie@linaro.org>
Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
6 years agowarp7: Define a platform_def.h
Bryan O'Donoghue [Fri, 25 May 2018 16:54:01 +0000 (17:54 +0100)]
warp7: Define a platform_def.h

This patch defines a platform_def.h describing

- FIP layout and location
- eMMC device select
- UART identity select
- System clock frequency
- Operational memory map

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>
Signed-off-by: Jun Nie <jun.nie@linaro.org>
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
6 years agowarp7: mem_params_desc: Add a file which exports a REGISTER_BL_IMAGE_DESCS
Bryan O'Donoghue [Fri, 25 May 2018 16:20:50 +0000 (17:20 +0100)]
warp7: mem_params_desc: Add a file which exports a REGISTER_BL_IMAGE_DESCS

In order to link even a basic image we need to declare
REGISTER_BL_IMAGE_DESCS. This patch declares an empty structure which is
passed to REGISTER_BL_IMAGE_DESCS(). Later patches will add in some
meaningful data.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
6 years agowarp7: Add a warp7_private.h file
Bryan O'Donoghue [Fri, 25 May 2018 16:18:56 +0000 (17:18 +0100)]
warp7: Add a warp7_private.h file

Internal declarations for the WaRP7 port will go here. For now just include
sys/types.h.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
6 years agowarp7: image_load: Add warp7_image_load.c
Bryan O'Donoghue [Thu, 24 May 2018 18:38:11 +0000 (19:38 +0100)]
warp7: image_load: Add warp7_image_load.c

This commit adds warp7_image_load.c with the functions

- plat_flush_next_bl_params()
- plat_get_bl_image_load_info()
- plat_get_next_bl_params()

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
6 years agowarp7: Add initial warp7_helpers.S
Bryan O'Donoghue [Thu, 24 May 2018 18:32:52 +0000 (19:32 +0100)]
warp7: Add initial warp7_helpers.S

This commit adds a warp7_helpers.S which contains a implementation of:

- platform_mem_init
- plat_get_my_entrypoint
- plat_crash_console_init
- plat_crash_console_putc

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
6 years agoimx: imx_wdog: Add code to initialize the wdog block
Bryan O'Donoghue [Fri, 25 May 2018 15:45:27 +0000 (16:45 +0100)]
imx: imx_wdog: Add code to initialize the wdog block

The watchdog block on the IMX is mercifully simple. This patch maps the
various registers and bits associated with the block.

We are mostly only really interested in the power-down-enable (PDE) bits in
the block for the purposes of ATF.

The i.MX7 Solo Applications Processor Reference Manual details the PDE bit
as follows:

"Power Down Enable bit. Reset value of this bit is 1, which means the power
down counter inside the WDOG is enabled after reset. The software must
write 0 to this bit to disable the counter within 16 seconds of reset
de-assertion. Once disabled this counter cannot be enabled again. See
Power-down counter event for operation of this counter."

This patch does that zero write in-lieu of later phases in the boot
no-longer have the necessary permissions to rewrite the PDE bit directly.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
6 years agoimx: imx_caam: Add code to initialize the CAAM job-rings to NS-world
Bryan O'Donoghue [Wed, 11 Jul 2018 15:35:17 +0000 (16:35 +0100)]
imx: imx_caam: Add code to initialize the CAAM job-rings to NS-world

This patch defines the most basic part of the CAAM and the only piece of
the CAAM silicon we are really interested in, in ATF, the CAAM control
structure.

The CAAM itself is a huge address space of some 32k, way out of scope for
the purpose we have in ATF.

This patch adds a simple CAAM init function that assigns ownership of the
CAAM job-rings to the non-secure MID with the ownership bit set to
non-secure.

This will allow later logic in the boot process such as OPTEE, u-boot and
Linux to assign job-rings as appropriate, restricting if necessary but
leaving open the main functionality of the CAAM to the Linux NS runtime.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
6 years agoqemu: make LOAD_IMAGE_V2=1 mandatory
Jens Wiklander [Tue, 4 Sep 2018 13:08:48 +0000 (15:08 +0200)]
qemu: make LOAD_IMAGE_V2=1 mandatory

The QEMU platform has only been used with LOAD_IMAGE_V2=1 for some time
now and bit rot has occurred for LOAD_IMAGE_V2=0. To ease the
maintenance make LOAD_IMAGE_V2=1 mandatory and remove the platform
specific code for LOAD_IMAGE_V2=0.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
6 years agozynqmp: Define and enable ARM_XLAT_TABLES_LIB_V1
Siva Durga Prasad Paladugu [Mon, 13 Aug 2018 11:10:04 +0000 (16:40 +0530)]
zynqmp: Define and enable ARM_XLAT_TABLES_LIB_V1

Enable ARM_XLAT_TABLES_LIB_V1 as ZynqMP is using
v1 library of translation tables.

With upstream patch d323af9e3d903d981b42f954844a95a6bfef91ab,
the usage of MAP_REGION_FLAT is referring to definition in file
include/lib/xlat_tables/xlat_tables_v2.h but while preparing
xlat tables in lib/xlat_tables/xlat_tables_common.c it is referring
to include/lib/xlat_tables/xlat_tables.h which is v1 xlat tables.
Also, ZynqMP was using v1 so defined ARM_XLAT_TABLES_LIB_V1 to
use v1 xlat tables everywhere.
This fixes the issue of xlat tables failures as it takes v2
library mmap_region structure in some files and v1 in other
files.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
6 years agoimx: imx_hab: Define a HAB header file
Bryan O'Donoghue [Tue, 3 Jul 2018 14:07:32 +0000 (15:07 +0100)]
imx: imx_hab: Define a HAB header file

The High Assurance Boot or HAB is an on-chip method of providing a
root-of-trust from the reset vector to subsequent stages in the bootup
flow of the Cortex-A7 on the i.MX series of processors.

This patch adds a simple header file with pointer offsets of the provided
set of HAH API callbacks in the BootROM.

The relative offset of the function pointers is a constant and known
quantum, a software-contract between NXP and an implementation which is
defined in the NXP HAB documentation.

All we need is the correct base offset and then we can map the set of
function pointers relative to that offset.

imx_hab_arch.h provides the correct offset and the imx_hab.h hooks the
offset to the pre-determined callbacks.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Ryan Harkin <ryan.harkin@linaro.org>
6 years agoimx7: hab_arch: Provide a hab_arch.h file
Bryan O'Donoghue [Tue, 3 Jul 2018 14:11:33 +0000 (15:11 +0100)]
imx7: hab_arch: Provide a hab_arch.h file

In order to enable compile time differences in HAB interaction, we should
split out the definition of the base address of the HAB API.

Some version of the i.MX series have different offsets from the BootROM
base for the HAB callback table.

This patch defines the header into which we will define the i.MX7 specific
offset. The offset of the i.MX7 function-callback table is simultaneously
defined.

Once done, we can latch a set of common function pointer locations from the
offset given here and if necessary change the offset for different
processors without any other code-change.

For now all we support is i.MX7 so the only offset being defined is that
for the i.MX7.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Ryan Harkin <ryan.harkin@linaro.org>
6 years agoimx: imx_snvs: Add an SNVS core functionality
Bryan O'Donoghue [Fri, 25 May 2018 15:52:03 +0000 (16:52 +0100)]
imx: imx_snvs: Add an SNVS core functionality

This patch adds snvs.c with a imx_snvs_init() function.

imx_snvs_init() sets up permissions of the RTC via the SNVS HPCOMR.

During previous work with OPTEE on the i.MX7 part we discovered that prior
to switching from secure-world to normal-world it is required to apply more
permissive permissions than are defaulted to in order for Linux to be able
to access the RTC and CAAM functionality in general.

This patch pertains to fixing the RTC permissions by way of the
HPCOMR.NPSWA_EN bit.

Once set non-privileged code aka Linux-kernel code has permissions to
access the SNVS where the RTC resides.

Perform that permissions fix in imx_snvs_init() now, with a later patch making
the call from our platform setup code.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
6 years agoimx: imx_snvs: Define a SNVS header and memory map
Bryan O'Donoghue [Mon, 25 Jun 2018 12:15:10 +0000 (13:15 +0100)]
imx: imx_snvs: Define a SNVS header and memory map

This commit defines two things.

- The basic SNVS memory map. At the moment that is total overkill for the
  permission bits we need to set inside the SNVS but, for the sake of
  completeness define the whole SNVS area as a struct.

- The bits of the HPCOMR register

  A permission fix will need to be applied to the SNVS block prior to
  switching on TrustZone. All we need to do is waggle a bit in the HPCOMR
  register. To do that waggle we first need to define the bits of the
  HPCOMR register.

- A imx_snvs_init() function definition

  Declare the snvs_init() function so that it can be called from our
  platform setup code.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
6 years agoimx: imx_csu: Add a simple CSU layer
Bryan O'Donoghue [Fri, 25 May 2018 15:56:52 +0000 (16:56 +0100)]
imx: imx_csu: Add a simple CSU layer

- Add a header to define imx_csu_init().
- Defines the Central Security Unit's Config Security Level
  permission bits.
- Define CSU_CSL_OPEN_ACCESS permission bitmask
- Run a loop to setup peripheral CSU permissions

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
6 years agoimx: imx_aips: Add initial AIPS support
Bryan O'Donoghue [Fri, 25 May 2018 15:43:22 +0000 (16:43 +0100)]
imx: imx_aips: Add initial AIPS support

This patch adds an initial AHB-to-IP TrustZone (AIPS-TZ) initialization
routine. Setting up the AIPSTZ controller is required to inform the SoC
interconnect fabric which bus-masters can read/write and if the read/writes
are buffered.

For our purposes the initial configuration is for everything to be open. We
can lock-down later on as necessary.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
6 years agoimx: imx_io_mux: Define an IO-mux layer
Bryan O'Donoghue [Wed, 20 Jun 2018 15:56:31 +0000 (16:56 +0100)]
imx: imx_io_mux: Define an IO-mux layer

This patch defines:

- The full range of IO-mux register offsets relative to the base address of
  the IO-mux block base address.

- The bits for muxing the UART1 TX/RX lines.

- The bits for muxing the UART6 TX/RX lines.

- The pad control pad bits for the UART

Two functions are provided to configure pad muxes:

- void io_muxc_set_pad_alt_function(pad_mux_offset, alt_function)
  Takes a pad_mux_offset and sets the alt_function bit-mask supplied.
  This will have the effect of switching the pad into one of its defined
  peripheral functions. These peripheral function modes are defined in the
  NXP documentation and need to be referred to in order to correctly
  configure a new alternative-function.

- void io_muxc_set_pad_features(pad_feature_offset, pad_features)
  Takes a pad_feature_offset and applies a pad_features bit-mask to the
  indicated pad.
  This function allows the setting of PAD drive-strength, pull-up values,
  hysteresis glitch filters and slew-rate settings.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
6 years agoimx7: imx7_clock: usb: Initialize the USB core clocks
Bryan O'Donoghue [Fri, 27 Jul 2018 14:03:51 +0000 (15:03 +0100)]
imx7: imx7_clock: usb: Initialize the USB core clocks

This patch initializes USB core clocks for the i.MX7.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
6 years agoimx7: imx7_clock: wdog: Initialize the watchdog clocks
Bryan O'Donoghue [Fri, 27 Jul 2018 13:53:43 +0000 (14:53 +0100)]
imx7: imx7_clock: wdog: Initialize the watchdog clocks

This patch initializes the watchdog clocks for the i.MX7.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
6 years agoimx7: imx7_clock: uart: Add UART clock init logic
Bryan O'Donoghue [Fri, 8 Jun 2018 12:16:29 +0000 (13:16 +0100)]
imx7: imx7_clock: uart: Add UART clock init logic

This patch adds an internal UART init routine that gets called from the
external facing clock init function.

In the first pass this call does an explicit disable of all UART
clock-gates. Later changes will enable only the UART clock-gates we care
about.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
6 years agoimx: imx_clock: usb: Add USB clock API
Bryan O'Donoghue [Mon, 16 Jul 2018 17:21:19 +0000 (18:21 +0100)]
imx: imx_clock: usb: Add USB clock API

This set of patches adds a very minimal layer of USB enabling patches to
clock.c. Unlike the watchdog or UART blocks the USB clocks pertain to PHYs,
the main USB clock etc, not to different instances of the same IP block.

As a result this patch-set takes the clock CCGR clock identifier directly
rather than as an index of an instance of blocks of the same type.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
6 years agoimx: imx_clock: wdog: Add watchdog clock API
Bryan O'Donoghue [Fri, 13 Jul 2018 09:21:40 +0000 (10:21 +0100)]
imx: imx_clock: wdog: Add watchdog clock API

This patch adds a set of functions to enable the clock for each of the
watchdog IP blocks.

Unlike the MMC and UART blocks, the watchdog blocks operate off of the one
root clock, only the clock-gates are enable/disabled individually.

As a consequence the function clock_set_wdog_clk_root_bits() is used to set
the root-slice just once for all of the watchdog blocks.

Future implementations may need to change this model but for now on the one
supported processor and similar NXP SoCs this model should work fine.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
6 years agoimx: imx_clock: mmc: Add USDHC clock API
Jun Nie [Thu, 28 Jun 2018 08:38:11 +0000 (16:38 +0800)]
imx: imx_clock: mmc: Add USDHC clock API

This patch adds an API to configure up the base USDHC clocks, taking a
bit-mask of silicon specific bits as an input from a higher layer in order
to direct the necessary clock source.

Signed-off-by: Jun Nie <jun.nie@linaro.org>
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
6 years agoimx: imx_clock: uart: Add UART clock API
Bryan O'Donoghue [Wed, 30 May 2018 18:56:54 +0000 (19:56 +0100)]
imx: imx_clock: uart: Add UART clock API

This patch adds an API to configure up the base UART clocks, taking a
bit-mask of silicon specific bits as an input from a higher layer in order
to direct the necessary clock source.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
6 years agoimx: imx_clock: Add driver and associated clock register definitions
Bryan O'Donoghue [Fri, 25 May 2018 15:48:39 +0000 (16:48 +0100)]
imx: imx_clock: Add driver and associated clock register definitions

This commit:

- Defines a clock stub with a conjoined header defining the clock
  memory map.

- Defines the CCM Clock Gating Register which comes in a quadrumvirate
  register set to read, set, clear and toggle individual clock gates into
  one of four states based bitmask.

  00: Domain clocks not needed
  01: Domain clocks needed when in RUN
  10: Domain clocks needed when in RUN and WAIT
  11: Domain clocks needed all the time

- Defines clock control register bits

  There are various quadrumvirate register blocks target-root, misc-root,
  post-root, pre-root in the CCM.

  The number of registers is huge but the four registers in each
  quadrumvirate block contain the same bits, so the number of bit
  definitions is actually quite low.

- Defines clock identifiers

  An array of clock gates is provided in the CCM block. In order to index
  that array and thus enable/disable clock gates for the right components,
  we need to provide meaningful names to the indices.

  Section 5.2.5 of the i.MX7 Solo Application Processor Reference Manual
  Rev 0.1 provides the relevant details.

- Defines target mux select bits
  This is a comprehensive definition of the target clock mux select bits.
  These bits are required to correctly select the clock source. Defining
  all of the bits up-front even for unused blocks in ATF means we can
  switch on any block we want at a later date without having to write new
  code in the clock-mux layer.

- Defines identifier indices into root-slice array
  The root-slice array of control registers has a specific set of indices,
  which differ from the clock-gate indices.

- Provides a clock gate enable/disable routine
  Provides a clock-gate enable/disable routine via the set/clr
  registers in a given clock-gate control register block.

  This index passed should be one of the enums associated with CCM and
  depending on enable/disable being passed either set or clr will be
  written to.

  The Domain0 bits are currently the only bits targeted by this write, more
  work may need to be done on the domain bits in subsequent patches as a
  result.

- imx: Adds set/clr routines to clock layer

  Adds a set and clr routine to the clock layer. These routines allow us to
  access the set and clear registers of the "target" block registers. These
  are the registers where we select the clock source from the available list.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
6 years agoimx7: imx_regs: Add a shared imx-regs.h for i.MX7 ATF platforms
Bryan O'Donoghue [Fri, 25 May 2018 15:05:20 +0000 (16:05 +0100)]
imx7: imx_regs: Add a shared imx-regs.h for i.MX7 ATF platforms

In order to have some common code shared between similar SOCs its pretty
common to have IP blocks reused. In reusing those blocks we frequently need
to map compatible blocks to different addresses depending on the SOC.

This patch adds a basic memory map of the i.MX7 based on the "Cortex-A7
Memory Map" section 2.12 of "i.MX7Solo Applications Processor Reference
Manual, Rev 0.1 08/2016"

In memory map terms the i.MX7S and i.MX7D are identical with the D
variant containing two Cortex-A7 cores plus a Cortex-M core and the S
variant containing one Cortex-A7 and one Cortex-M.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
6 years agodrivers: imx: mxc_usdhc: Add USDHC driver to support boot EMMC
Jun Nie [Thu, 28 Jun 2018 08:38:02 +0000 (16:38 +0800)]
drivers: imx: mxc_usdhc: Add USDHC driver to support boot EMMC

Add USDHC driver to support boot EMMC. Only initialization
and single/multiple block read are tested.

[bod: fixed checkpatch.pl complaints]
[bod: changed name to imx_usdhc for namespace consistency]
[bod: squashed antecedent fixes into this one patch]

Signed-off-by: Jun Nie <jun.nie@linaro.org>
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
6 years agozynqmp: Add ATF support for Data blob encryption and decryption
Siva Durga Prasad Paladugu [Tue, 4 Sep 2018 12:35:50 +0000 (18:05 +0530)]
zynqmp: Add ATF support for Data blob encryption and decryption

This patch adds ATF support for AES data blob encrypt/decrypt.
ATF establishes a path to send the address of the structure
to the xilsecure, so that it will pick addresses of the data
and performs the requested operation (encrypt/decrypt) and puts
the result in load address.

where structure contains
- Data blob src address
- load address
- IV address
- Key address - this will actual key addr in case of KUP
else it will be zero.
- Data-size
- Aes-op type
- KeySrc

Signed-off-by: Kalyani Akula <kalyani.akula@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
6 years agozynqmp: Remove emulation platform support
Siva Durga Prasad Paladugu [Tue, 4 Sep 2018 12:32:25 +0000 (18:02 +0530)]
zynqmp: Remove emulation platform support

This patch removes support for emulation platforms
EP108 and Veloce.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
6 years agozynqmp: pm: Correct function header of clock APIs
Rajan Vaja [Mon, 9 Jul 2018 07:01:38 +0000 (00:01 -0700)]
zynqmp: pm: Correct function header of clock APIs

Correct function header of pm_api_clock_getparent() and
pm_api_clock_setparent().

Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Acked-by: Will Wong <WILLW@xilinx.com>
6 years agozynqmp: pm_service: Ignore enable/disable of PLL type clocks
Siva Durga Prasad Paladugu [Tue, 4 Sep 2018 12:19:32 +0000 (17:49 +0530)]
zynqmp: pm_service: Ignore enable/disable of PLL type clocks

PLL type clock is enabled by FSBL on boot-up. PMUFW enable/disable
them based on their user count. So, it should not be handled from ATF.

Put PLL type clock into bypass and reset mode only while changing
PLL rate (FBDIV).

Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Acked-by: Will Wong <WILLW@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
6 years agozynqmp: Add new API for pl configuration readback
Siva Durga Prasad Paladugu [Tue, 4 Sep 2018 12:11:34 +0000 (17:41 +0530)]
zynqmp: Add new API for pl configuration readback

This patch adds new API's for performing pl configuration
readback.

Signed-off-by: Appana Durga Kedareswara rao <appana.durga.rao@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
6 years agozynqmp: pm: Use critical flag instead of initenable
Siva Durga Prasad Paladugu [Tue, 4 Sep 2018 12:07:27 +0000 (17:37 +0530)]
zynqmp: pm: Use critical flag instead of initenable

CCF has already provision to enable clock during registration
through CLK_IS_CRITICAL flag. Use CLK_IS_CRITICAL instead of
init_enable attribute.

Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Acked-by: Jolly Shah <jolly.shah@xilinx.com>
6 years agozynqmp: pm: Correct WDT clock database
Siva Durga Prasad Paladugu [Tue, 4 Sep 2018 12:03:19 +0000 (17:33 +0530)]
zynqmp: pm: Correct WDT clock database

WDT used by APU is FPD_WDT. FPD WDT clock is controlled by
FPD_SLCR.WDT_CLK_SEL register. Correct the same in WDT clock
database.

As per FPD_SLCR.WDT_CLK_SEL register, there can be only two
parents of WDT clock not three. Fix the same by correcting it's
parents in clock database.

Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Acked-by: Jolly Shah <jolly.shah@xilinx.com>
6 years agozynqmp: pm_service: Add support for writing to AFI registers
Siva Durga Prasad Paladugu [Tue, 4 Sep 2018 11:57:12 +0000 (17:27 +0530)]
zynqmp: pm_service: Add support for writing to AFI registers

Add support for writing to AFI registers.
So that after writing a bitstream the interface can be programmed.

Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
Signed-off-by: Appana Durga Kedareswara rao <appana.durga.rao@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
6 years agozynqmp: pm: Add IOCTL to set boot health status
Siva Durga Prasad Paladugu [Tue, 4 Sep 2018 11:42:51 +0000 (17:12 +0530)]
zynqmp: pm: Add IOCTL to set boot health status

Since the MMIO read/write APIs are removed from Linux user space,
Linux cannot directly write to the Global General Storage Register 4
any more to set healthy boot status.

Create an IOCTL to allow Linux to set boot health status.

Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Acked-by: Will Wong <willw@xilinx.com>
6 years agodrivers: mmc: Add missing response type for some commands
Bryan O'Donoghue [Wed, 15 Aug 2018 15:25:30 +0000 (16:25 +0100)]
drivers: mmc: Add missing response type for some commands

Add missing response type for SWITCH command and STOP_TRANSMISSION
so that controller can be configured accordingly.

[bod: ported this change from Jun's eMMC patches to the MMC driver]

Signed-off-by: Jun Nie <jun.nie@linaro.org>
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
6 years agodrivers: mmc: Fix R3 response type definition
Bryan O'Donoghue [Wed, 15 Aug 2018 14:59:07 +0000 (15:59 +0100)]
drivers: mmc: Fix R3 response type definition

The R3 response type definition should be (1 << 0). Make sure we define the
expected response code in the appropriate fashion.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
6 years agodrivers: emmc: dw_mmc: Add response flag into response ID definition
Jun Nie [Thu, 28 Jun 2018 08:38:00 +0000 (16:38 +0800)]
drivers: emmc: dw_mmc: Add response flag into response ID definition

Add response flag into ID definition so that driver does not
need to handle it again.

Signed-off-by: Jun Nie <jun.nie@linaro.org>
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
6 years agozynqmp: pm_service: Add support for resetting ULPI transceiver
Siva Durga Prasad Paladugu [Tue, 4 Sep 2018 11:33:25 +0000 (17:03 +0530)]
zynqmp: pm_service: Add support for resetting ULPI transceiver

To make ULPI transceiver work, a HIGH - LOW - HIGH pulse needs
to be given to resetb pin of ULPI chip. In ZYNQMP, this resetb
pin is being driven by BOOT MODE PIN 1. The BOOT MODE PIN's
are controlled by BOOT_PIN_CTRL register present in CRL_APB
address region. Since CRL_APB can be resticted to secure access,
this pin should be controlled by ATF.

This patch adds the support for the same.

Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
6 years agodrivers: imx: imx_gpt: Add general purpose timer API binding
Jun Nie [Wed, 4 Jul 2018 07:51:20 +0000 (15:51 +0800)]
drivers: imx: imx_gpt: Add general purpose timer API binding

Add delay timer API so that it can be called by delay timer
layer and used as delay timer globally.

[bod: changed name from imx_delay_timer -> imx_gpt ]

Signed-off-by: Jun Nie <jun.nie@linaro.org>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
6 years agoFix broken links in documentation
John Tsichritzis [Tue, 4 Sep 2018 09:56:53 +0000 (10:56 +0100)]
Fix broken links in documentation

Change-Id: Ic58f88fa4e5fc0004a33357915ff80db30954441
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
6 years agoSupport shared Mbed TLS heap for SGM
John Tsichritzis [Wed, 22 Aug 2018 11:55:41 +0000 (12:55 +0100)]
Support shared Mbed TLS heap for SGM

Change-Id: Ibbfedb6601feff51dfb82c1d94850716c5a36d24
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
6 years agoSupport shared Mbed TLS heap for SGI
John Tsichritzis [Wed, 22 Aug 2018 11:36:37 +0000 (12:36 +0100)]
Support shared Mbed TLS heap for SGI

Change-Id: Iac454c745543842bfeed004aee7a3f4fb94d37e1
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
6 years agoReduce BL2 size for FVP
John Tsichritzis [Mon, 3 Sep 2018 14:06:44 +0000 (15:06 +0100)]
Reduce BL2 size for FVP

This patch reduces BL2 size by 12kB. Thanks to the shared Mbed TLS heap
between BL1 and BL2, BL2 now requires less memory since it doesn't need
to allocate a heap anymore.

Change-Id: I58a15f8c424273650c9f55112abe88105b6cdbae
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
6 years agoSupport shared Mbed TLS heap for FVP
John Tsichritzis [Mon, 30 Jul 2018 12:41:52 +0000 (13:41 +0100)]
Support shared Mbed TLS heap for FVP

This patch introduces the shared Mbed TLS heap optimisation for Arm
platforms. The objective is the Mbed TLS heap to be shared between BL1
and BL2 so as to not allocate the heap memory twice. To achieve that,
the patch introduces all the necessary helpers for implementing this
optimisation. It also applies it for FVP.

Change-Id: I6d85eaa1361517b7490956b2ac50f5fa0d0bb008
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
6 years agoPrepare Mbed TLS drivers for shared heap
John Tsichritzis [Thu, 7 Jun 2018 15:31:34 +0000 (16:31 +0100)]
Prepare Mbed TLS drivers for shared heap

The Mbed TLS drivers, in order to work, need a heap for internal usage.
This heap, instead of being directly referenced by the drivers, now it
is being accessed indirectly through a pointer. Also, the heap, instead
of being part of the drivers, now it is being received through the
plat_get_mbedtls_heap() function. This function requests a heap from the
current BL image which utilises the Mbed TLS drivers.

Those changes create the opportunity for the Mbed TLS heap to be shared
among different images, thus saving memory. A default heap
implementation is provided but it can be overridden by a platform
specific, optimised implemenetation.

Change-Id: I286a1f10097a9cdcbcd312201eea576c18d157fa
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
6 years agoMerge pull request #1548 from BayLibre/opteed
Soby Mathew [Tue, 4 Sep 2018 04:01:56 +0000 (05:01 +0100)]
Merge pull request #1548 from BayLibre/opteed

opteed: pass power level on suspend

6 years agoMerge pull request #1540 from MISL-EBU-System-SW/marvell-updates-18.09
Soby Mathew [Tue, 4 Sep 2018 02:35:54 +0000 (03:35 +0100)]
Merge pull request #1540 from MISL-EBU-System-SW/marvell-updates-18.09

Marvell updates 18.09

6 years agofix: tools: Fix doimage syntax breaking secure mode build
Konstantin Porotchkin [Thu, 16 Aug 2018 10:57:18 +0000 (13:57 +0300)]
fix: tools: Fix doimage syntax breaking secure mode build

Missing ")" in fprintf causing build break in secure boot mode.

Change-Id: Ice555571683b68bb0d81479e9fc8abc4296809ac
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
6 years agoplat: marvell: Update Marvell base code version to 18.09.1
Konstantin Porotchkin [Thu, 16 Aug 2018 07:25:24 +0000 (10:25 +0300)]
plat: marvell: Update Marvell base code version to 18.09.1

Change-Id: I908844364bf8080612aaa6d750d7d2441ecc2eb8
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
6 years agoplat: svc: ap807: add SVC configuration for AP807
Christine Gharzuzi [Thu, 2 Aug 2018 17:25:11 +0000 (20:25 +0300)]
plat: svc: ap807: add SVC configuration for AP807

- add svc configuration according to values burnt
  to the chip efuse

Change-Id: Icf5d7cc41bc09ac2244d0a126106e681afebb064
Signed-off-by: Christine Gharzuzi <chrisg@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>