Yann Gautier [Mon, 16 Jul 2018 15:55:07 +0000 (17:55 +0200)]
stm32mp1: Add PMIC support
If a PMIC companion chip is present on board, it has to be configured
for regulators supplies.
This check is done with board DT configuration.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Pascal Paillet <p.paillet@st.com>
Yann Gautier [Thu, 5 Jul 2018 14:48:16 +0000 (16:48 +0200)]
stm32mp1: Add console support
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Yann Gautier [Fri, 20 Jul 2018 09:36:05 +0000 (11:36 +0200)]
stm32mp1: save boot information in backup registers
This will be used by BL33 to get boot device and instance.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Mathieu Belou <mathieu.belou@st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Yann Gautier [Fri, 13 Jul 2018 19:33:09 +0000 (21:33 +0200)]
stm32mp1: Add GPIO support
The management of pinctrl nodes of device tree is also added.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Mathieu Belou <mathieu.belou@st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Yann Gautier [Tue, 24 Jul 2018 15:13:36 +0000 (17:13 +0200)]
stm32mp1: Add clock and reset support
The clock driver is under dual license, BSD and GPLv2.
The clock driver uses device tree, so a minimal support for this is added.
The required files for driver and DTS files are in include/dt-bindings/.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Yann Gautier [Mon, 16 Jul 2018 08:54:09 +0000 (10:54 +0200)]
Introduce STMicroelectronics STM32MP1 platform
STM32MP1 is a microprocessor designed by STMicroelectronics,
based on a dual Arm Cortex-A7.
It is an Armv7-A platform, using dedicated code from TF-A.
STM32MP1 uses BL2 compiled with BL2_AT_EL3.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Mathieu Belou <mathieu.belou@st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Pascal Paillet <p.paillet@st.com>
Yann Gautier [Thu, 5 Jul 2018 14:45:46 +0000 (16:45 +0200)]
Add STMicroelectronics to the list of contributors
Signed-off-by: Yann Gautier <yann.gautier@st.com>
danh-arm [Tue, 24 Jul 2018 13:37:23 +0000 (14:37 +0100)]
Merge pull request #1488 from b49020/integration
synquacer: Enable optional OP-TEE support
danh-arm [Tue, 24 Jul 2018 13:36:43 +0000 (14:36 +0100)]
Merge pull request #1485 from jeenu-arm/ras
Double-fault and fatal error handling support
Sumit Garg [Thu, 19 Jul 2018 12:35:50 +0000 (18:05 +0530)]
synquacer: Enable optional OP-TEE support
OP-TEE loading is optional on Developerbox controlled via SCP
firmware. To check if OP-TEE is loaded or not, we use DRAM1 region
info passed by SCP firmware.
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Reviewed-by: Daniel Thompson <daniel.thompson@linaro.org>
danh-arm [Tue, 24 Jul 2018 10:06:24 +0000 (11:06 +0100)]
Merge pull request #1487 from hzhuang1/tbb_bl1
hikey: include TBB in BL1
Haojian Zhuang [Wed, 18 Jul 2018 09:07:00 +0000 (17:07 +0800)]
hikey: include TBB in BL1
BL1 is used in recovery mode on HiKey. The TBB implementation
on HiKey is in BL2. It means that user need to build ATF BL2
with TBB and ATF BL1 with non-TBB. It's inconvenient.
So include TBB in BL1, too.
Signed-off-by: Teddy Reed <teddy@prosauce.org>
Signed-off-by: Victor Chong <victor.chong@linaro.org>
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
danh-arm [Thu, 19 Jul 2018 16:11:32 +0000 (17:11 +0100)]
Merge pull request #1450 from MISL-EBU-System-SW/marvell-support-v6
Marvell support for Armada 8K SoC family
danh-arm [Thu, 19 Jul 2018 14:37:54 +0000 (15:37 +0100)]
Merge pull request #1483 from antonio-nino-diaz-arm/an/rpi3-psci
rpi3: PSCI and Linux boot improvements
danh-arm [Thu, 19 Jul 2018 14:33:19 +0000 (15:33 +0100)]
Merge pull request #1481 from antonio-nino-diaz-arm/an/xlat-refactor
xlat: More refactoring
danh-arm [Thu, 19 Jul 2018 10:49:56 +0000 (11:49 +0100)]
Merge pull request #1449 from theopolis/hikey-tbb
hikey: Add experimental TBB support
danh-arm [Thu, 19 Jul 2018 10:36:58 +0000 (11:36 +0100)]
Merge pull request #1482 from sandrine-bailleux-arm/sb/fix-hcptr
Misc arch.h fixes and cleanup
Jeenu Viswambharan [Thu, 12 Jul 2018 09:00:01 +0000 (10:00 +0100)]
RAS: Update porting guide with RAS platform handlers
Change-Id: I76cb1d387ab51ee48fa91fd7458c7041b454ceee
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
Jeenu Viswambharan [Fri, 6 Jul 2018 15:50:06 +0000 (16:50 +0100)]
RAS: Introduce handler for EL3 EAs
External Aborts while executing in EL3 is fatal in nature. This patch
allows for the platform to define a handler for External Aborts received
while executing in EL3. A default implementation is added which falls
back to platform unhandled exception.
Change-Id: I466f2c8113a33870f2c7d2d8f2bf20437d9fd354
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
Jeenu Viswambharan [Thu, 17 May 2018 10:24:01 +0000 (11:24 +0100)]
RAS: Introduce handler for Double Faults
Double fault is when the PE receives another error whilst one is being
handled. To detect double fault condition, a per-CPU flag is introduced
to track the status of error handling. The flag is checked/modified
while temporarily masking external aborts on the PE.
This patch routes double faults to a separate platform-defined handler.
Change-Id: I70e9b7ba4c817273c55a0af978d9755ff32cc702
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
Jeenu Viswambharan [Thu, 17 May 2018 08:52:36 +0000 (09:52 +0100)]
RAS: Introduce handler for Uncontainable errors
Uncontainable errors are the most severe form of errors, which typically
mean that the system state can't be trusted any more. This further means
that normal error recovery process can't be followed, and an orderly
shutdown of the system is often desirable.
This patch allows for the platform to define a handler for Uncontainable
errors received. Due to the nature of Uncontainable error, the handler
is expected to initiate an orderly shutdown of the system, and therefore
is not expected to return. A default implementation is added which falls
back to platform unhandled exception.
Also fix ras_arch.h header guards.
Change-Id: I072e336a391a0b382e77e627eb9e40729d488b55
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
Konstantin Porotchkin [Thu, 21 Jun 2018 10:40:33 +0000 (13:40 +0300)]
make: support libraries in MAKE_BL macro
Add support for BLx stages to use libraries in MAKE_BL macro.
This change does not affect BL stages that do not have
BL_LIBS variable defined in their makefiles.
However in case that BL wants to use external library
(for instance vendor-specific DDR initialization code supplied
as a library), this patch will allow to build BL image linked
with such library.
Change-Id: Ife29069a72dc4aff833db6ef8b828736d6689b78
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Konstantin Porotchkin [Mon, 7 May 2018 09:52:48 +0000 (12:52 +0300)]
io: Allow image load to address zero
Remove assert on buffer address equal zero.
Marvell uses address 0x0 for loading BL33,
so this check is irrelevant and breaks the
debug builds on Marvell platforms.
Change-Id: Ie56a51138e2e4ddd8986dd7036797dc2d8b10125
Signed-off-by: Haim Boot <hayim@marvell.com>
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/54589
Konstantin Porotchkin [Thu, 7 Jun 2018 15:48:49 +0000 (18:48 +0300)]
plat: marvell: Add board support for A8K platform
Add support for A8K platform boards
Change-Id: Ife025d930d2ab6cabbc13bbe19b2273cc1c938c8
Signed-off-by: Hanna Hawa <hannah@marvell.com>
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Konstantin Porotchkin [Thu, 7 Jun 2018 15:31:14 +0000 (18:31 +0300)]
plat: marvell: Add common ARMADA platform components
Add common Marvell ARMADA platform components.
This patch also includes common components for Marvell
ARMADA 8K platforms.
Change-Id: I42192fdc6525a42e46b3ac2ad63c83db9bcbfeaf
Signed-off-by: Hanna Hawa <hannah@marvell.com>
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Konstantin Porotchkin [Mon, 26 Feb 2018 14:32:35 +0000 (16:32 +0200)]
docs: Add Marvell build and porting documents
Change-Id: I341440701b7e5e3555e604dd9d0a356795e6c4fb
Signed-off-by: Hanna Hawa <hannah@marvell.com>
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Konstantin Porotchkin [Mon, 26 Feb 2018 14:28:40 +0000 (16:28 +0200)]
tools: add support for Marvell doimage
Add Marvell "doimage" utility support.
The "doimage" utility allows to create flash images compatible
with Marvell BootROM image format. Additionally this tool
allows the flash image parsing and verification.
Change-Id: Ie8d7ccd0cc2978684e7eecb695f375395fc749ee
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Konstantin Porotchkin [Mon, 26 Feb 2018 14:06:35 +0000 (16:06 +0200)]
marvell: drivers: Add i2c driver
Add i2c driver for A8K SoC family.
Change-Id: I5932b2fce286d84fc3ad5a74c4c456001faa3196
Signed-off-by: Hanna Hawa <hannah@marvell.com>
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Konstantin Porotchkin [Tue, 24 Apr 2018 16:23:09 +0000 (19:23 +0300)]
mvebu: cp110: add COMPHY driver
Add COMPHY driver for usage in a runtime service.
Change-Id: I6fb42d0a099496d5699ee24684ae2b93ed35770b
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Konstantin Porotchkin [Mon, 26 Feb 2018 14:08:26 +0000 (16:08 +0200)]
marvell: drivers: Add thermal driver
Add thermal driver for A8K SoC family.
The termal unit data is used by Marvell DRAM initialization
code for optimizing the memory controller configuration
Change-Id: Iad92689fa6e4224a89d872e9aa015393abd9cf73
Signed-off-by: Hanna Hawa <hannah@marvell.com>
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Konstantin Porotchkin [Mon, 26 Feb 2018 14:04:25 +0000 (16:04 +0200)]
marvell: drivers: Add L3/system cache management drivers
Add LLC (L3) cache management drivers for Marvell SoCs
AP806, AP807 and AP810
Change-Id: Ic70710f9bc5b6b48395d62212df7011e2fbb5894
Signed-off-by: Hanna Hawa <hannah@marvell.com>
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Konstantin Porotchkin [Thu, 5 Jul 2018 08:28:02 +0000 (11:28 +0300)]
lib: cpu: Add L2 cache aux control register definition to CA72
Add definition of EL1 L2 Auxilary Control register to
Cortex A72 library headers.
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Konstantin Porotchkin [Mon, 26 Feb 2018 14:01:57 +0000 (16:01 +0200)]
marvell: drivers: Add MoChi drivers
Add ModularChip and MCI drivers for A8K SoC family.
ModularChip drivers include support for the internal building
blocks of Marvell ARMADA SoCs - APN806, APN807 and CP110
Change-Id: I9559343788fa2e5eb47e6384a4a7d47408787c02
Signed-off-by: Hanna Hawa <hannah@marvell.com>
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Konstantin Porotchkin [Mon, 26 Feb 2018 13:51:11 +0000 (15:51 +0200)]
marvell: drivers: Add address decoding units drivers
Add address decoding unit drivers for Marvell SoCs.
Address decoding flow and address translation units chart
are located at docs/marvell/misc/mvebu-a8k-addr-map.txt
Change-Id: Id6ce311fa1f4f112df3adfac5d20449f495f71ed
Signed-off-by: Hanna Hawa <hannah@marvell.com>
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Konstantin Porotchkin [Mon, 2 Jul 2018 12:01:32 +0000 (15:01 +0300)]
maintainers: Add Marvell to maintainers list
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Soby Mathew [Wed, 18 Jul 2018 12:35:29 +0000 (13:35 +0100)]
Merge pull request #1471 from Anson-Huang/master
Add i.MX8QX/i.MX8QM power management feature
Sandrine Bailleux [Fri, 13 Jul 2018 08:04:12 +0000 (10:04 +0200)]
Fix HCPTR.TCP11 bit definition
Change-Id: I98f23f6cebcf984b57efc5449b75ff702e1984a0
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Antonio Nino Diaz [Thu, 12 Jul 2018 12:23:59 +0000 (13:23 +0100)]
Fix types of arch.h definitions
Define the values as unsigned int or unsigned long long based on the
actual size of the register. This prevents subtle issues caused by
having a type that is too small. For example:
#define OPTION_ENABLE 0x3
#define OPTION_SHIFT 32
uint64_t mask = OPTION_ENABLE << OPTION_SHIFT;
Because OPTION_ENABLE fits in an int, the value is considered an int.
This means that, after shifting it 32 places to the left, the final
result is 0. The correct way to define the values is:
#define OPTION_ENABLE ULL(0x3)
#define OPTION_SHIFT U(32)
In this case, the compiler is forced to use a 64 bit value from the
start, so shifting it 32 places to the left results in the expected
value.
Change-Id: Ieaf2ffc2d8caa48c622db011f2aef549e713e019
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Antonio Nino Diaz [Wed, 11 Jul 2018 15:45:49 +0000 (16:45 +0100)]
Add missing parentheses to macros in arch.h
Change-Id: Ifea46da46d1bfd01b341acfad75df5bcab48a204
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Soby Mathew [Wed, 18 Jul 2018 09:48:03 +0000 (10:48 +0100)]
Merge pull request #1480 from sandrine-bailleux-arm/topics/sb/debug-macros
Always compile debug macros
Jeenu Viswambharan [Mon, 19 Feb 2018 12:25:53 +0000 (12:25 +0000)]
RAS: Validate stack pointer after error handling
RAS handling flows might involve using setjmp/longjump calls introduced
in earlier patches; therefore, it'd be good to make sure the stack has
been unwound completely after the handling.
This patch inserts ASM assertions on the RAS handling path to validate
stack.
Change-Id: I59d40d3122010c977cdeab3cce3160f3909e7e69
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
Jeenu Viswambharan [Thu, 5 Jul 2018 14:24:45 +0000 (15:24 +0100)]
RAS: Move EA handling to a separate file
A new file ea_delegate.S is introduced, and all EA-related functions are
moved into it. This makes runtime_exceptions.S less crowded and reads
better.
No functional changes.
Change-Id: I64b653b3931984cffd420563f8e8d1ba263f329f
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
Antonio Nino Diaz [Sun, 15 Jul 2018 10:56:33 +0000 (11:56 +0100)]
rpi3: Move NS-DRAM out of the protected region
The Non-secure DRAM region shouldn't be protected in the range specified
in the Linux command line with memmap.
This change also increases the size of the Secure DRAM region.
Change-Id: I306e9e443a84b834c99739f54a534a3ca3be2424
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Antonio Nino Diaz [Sun, 15 Jul 2018 10:54:42 +0000 (11:54 +0100)]
rpi3: Switch addresses of kernel and DTB
In the memory map of the documentation the kernel only had 16MiB of
allocated space. This leaves very little room for growth, so the
addresses of the DTB and the kernel have been interchanged.
The documentation has been updated to reflect this change.
Change-Id: Ib6eab69f047fa88561fb755397ce3a0b356c8860
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Antonio Nino Diaz [Sat, 14 Jul 2018 01:03:38 +0000 (02:03 +0100)]
rpi3: Update documentation
Add information about direct Linux kernel boot for kernels that support
PSCI.
Change-Id: I05f76aa36398edabf411cb25a646437af1862e6e
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Antonio Nino Diaz [Sun, 15 Jul 2018 11:32:32 +0000 (12:32 +0100)]
rpi3: Add support for direct Linux kernel boot
This option allows the Trusted Firmware to pass the correct arguments to
a 32 or 64-bit Linux kernel without the need of an intermediate loader
such as U-Boot.
Change-Id: I2b22e8933fad6a614588ace559f893e97329801f
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Antonio Nino Diaz [Sat, 14 Jul 2018 00:23:41 +0000 (01:23 +0100)]
rpi3: Don't wire mailbox 3 to FIQ line
FIQs shouldn't be used at all as long as the interrupt routing doesn't
support them properly.
Change-Id: Ib1db7b523a62de2035d41197bc791048337cf791
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Antonio Nino Diaz [Sat, 14 Jul 2018 00:22:43 +0000 (01:22 +0100)]
rpi3: Fix warm entrypoint setup for PSCI_CPU_ON
Remove unused variable and set the secure entrypoint correctly.
Change-Id: I7447ea62771092de6be35704077ae28c519d6993
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Antonio Nino Diaz [Fri, 13 Jul 2018 14:26:49 +0000 (15:26 +0100)]
rpi3: Add support for the stack protector
It uses the hardware RNG in a similar way as Juno (it gets 128 bits of
entropy and does xor on them).
It is disabled by default.
Change-Id: I8b3adb61f5a5623716e0e8b6799404c68dd94c60
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Antonio Nino Diaz [Fri, 13 Jul 2018 08:27:16 +0000 (09:27 +0100)]
rpi3: Introduce hardware RNG driver
Note that this is a non-secure RNG. This is only useful for educational
purposes.
Change-Id: If359c8d0f755ef8e416986de7fbca34679a523e1
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Antonio Nino Diaz [Fri, 13 Jul 2018 19:19:21 +0000 (20:19 +0100)]
rpi3: Remove broken support of RESET_TO_BL31
There is no way to boot BL31 at the addresses specified in the platform
memory map unless an extra loader is used at address 0x00000000. It is
better to remove it to prevent confusion. Having it enabled was a bug.
Change-Id: I3229fbc080f5996cff47efce8e799bae94e0d5cb
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Soby Mathew [Mon, 16 Jul 2018 13:22:10 +0000 (14:22 +0100)]
Merge pull request #1478 from antonio-nino-diaz-arm/an/rpi3-improvements
rpi3: A few improvements
Antonio Nino Diaz [Thu, 12 Jul 2018 14:54:10 +0000 (15:54 +0100)]
xlat: Remove references to the Trusted Firmware
This library can be used in other projects. All comments that talk about
the Trusted Firmware should be talking about the library itself.
Change-Id: I3b98d42f7132be72c1f8a4900acfaa78dbd2daa2
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Antonio Nino Diaz [Wed, 11 Jul 2018 12:07:06 +0000 (13:07 +0100)]
SPM: Use generic MMU setup functions
Instead of having a different initialization routine than the rest of
the codebase, use the common implementation.
Change-Id: I27c03b9905f3cf0af8810aad9e43092005387a1a
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Antonio Nino Diaz [Sun, 15 Jul 2018 15:42:01 +0000 (16:42 +0100)]
xlat v2: Make setup_mmu_config public
This allows other parts of the code to reuse it. No functional changes.
Change-Id: Ib052ae235c422d9179958bd3016c3e678779ae9b
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Antonio Nino Diaz [Thu, 12 Jul 2018 12:38:53 +0000 (13:38 +0100)]
rpi3: Detect board revision
Implement VideoCore mailbox interface driver and use it to get the board
revision identifier.
For now it is only used to print the model for debug purposes.
This wiki contains the documentation of the mailbox interface:
https://github.com/raspberrypi/firmware/wiki
Change-Id: I11943b99b52cc1409f4a195ebe58eb44ae5b1d6c
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Antonio Nino Diaz [Sat, 14 Jul 2018 01:15:51 +0000 (02:15 +0100)]
rpi3: Implement PSCI_SYSTEM_OFF
This implementation doesn't actually turn the system off, it simply
reboots it and prevents it from booting while keeping it in a low power
mode.
Change-Id: I7f72c9f43f25ba0341db052bc2be4774c88a7ea3
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Antonio Nino Diaz [Thu, 12 Jul 2018 07:58:38 +0000 (08:58 +0100)]
rpi3: Concatenate BL1 and FIP automatically
Add a new default makefile target to concatenate BL1 and the FIP and
generate armstub8.bin. This way it isn't needed to do it manually.
Documentation updated to reflect the changes.
Change-Id: Id5b5b1b7b9f87767db63fd01180ddfea855a7207
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Dimitris Papastamos [Fri, 13 Jul 2018 14:23:29 +0000 (15:23 +0100)]
Merge pull request #1477 from dp-arm/dp/css-ap-core
CSS: Add support for SCMI AP core config protocol
Antonio Nino Diaz [Thu, 12 Jul 2018 14:44:42 +0000 (15:44 +0100)]
xlat v2: Turn MMU parameters into 64-bit values
Most registers are 64-bit wide, even in AArch32 mode:
- MAIR_ELx is equivalent to MAIR0 and MAIR1.
- TTBR is 64 bit in both AArch64 and AArch32.
The only difference is the TCR register, which is 32 bit in AArch32 and
in EL3 in AArch64. For consistency with the rest of ELs in AArch64, it
makes sense to also have it as a 64-bit value.
Change-Id: I2274d66a28876702e7085df5f8aad0e7ec139da9
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Antonio Nino Diaz [Thu, 12 Jul 2018 14:43:07 +0000 (15:43 +0100)]
xlat v2: Remove IMAGE_EL define
The Exception Level is now detected at runtime. This means that it is not
needed to hardcode the EL used by each image.
This doesn't result in a substantial increase of the image size because
the initialization functions that aren't used are garbage-collected by
the linker.
In AArch32 the current EL has been changed from EL3 to EL1 because the
the AArch32 PL1&0 translation regime behaves more like the AArch64 EL1&0
translation regime than the EL3 one.
Change-Id: I941404299ebe7666ca17619207c923b49a55cb73
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Antonio Nino Diaz [Wed, 11 Jul 2018 08:46:45 +0000 (09:46 +0100)]
xlat v2: Remove unused tlbi helper
xlat_arch_tlbi_va_regime() isn't used, so it has been renamed to
xlat_arch_tlbi_va() and the previous implementation has been removed.
Change-Id: Ic118bed3fb68234748d86b2e9e95b25650289276
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Antonio Nino Diaz [Thu, 5 Jul 2018 07:11:48 +0000 (08:11 +0100)]
xlat v2: Remove architectural headers
They only contained one function that is easily integrated in the private
library header and the existing architectural C files.
This also helps making the library more portable, as the Makefile of the
library now doesn't use the variable INCLUDES, which is specific to this
codebase and doesn't respect the namespace of the library.
Change-Id: I22228e6a97e9b4f346f5cd8947609263e8df71d8
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Sandrine Bailleux [Thu, 21 Jun 2018 09:41:43 +0000 (11:41 +0200)]
Tegra: Fix up INFO() message
With commit
cf24229e6ef4 ("Run compiler on debug macros for type
checking"), the compiler will now always evaluate INFO() macro
calls, no matter the LOG_LEVEL value. Therefore, any variable
referenced in the macro has to be be defined.
Address this issue by removing the local variable and using the
expression it was assigned directly in the INFO() call.
Change-Id: Iedc23b3538c1e162372e85390881e50718e50bf3
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Sandrine Bailleux [Wed, 20 Jun 2018 16:18:56 +0000 (18:18 +0200)]
Fix verbose messages in SDEI code
Fix mismatches between the format specifier and the corresponding
variable type.
Change-Id: Ib9004bd9baa9ba24a50000bea4f2418e1bf7e743
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Sandrine Bailleux [Wed, 20 Jun 2018 12:50:48 +0000 (14:50 +0200)]
Run compiler on debug macros for type checking
Even if the log output is too low for a message to be printed out on
the console by the debug macros, it should still be evaluated by the
compiler to get some type checking and validation of the format
specifiers. To do so, introduce the no_tf_log() macro that encloses
the call to tf_log() in an always-false condition.
This avoids the problem of discovering build issues only when we build
the firmware with the right LOG_LEVEL value.
Change-Id: Ic0fd252ab691d0187fd925756a4837aca1cbfd7b
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Dimitris Papastamos [Thu, 12 Jul 2018 15:53:08 +0000 (16:53 +0100)]
Merge pull request #1432 from Yann-lms/mmc_framework
[RFC] Add MMC framework
Dimitris Papastamos [Thu, 12 Jul 2018 10:53:37 +0000 (11:53 +0100)]
Merge pull request #1476 from grandpaul/paulliu-rpi3-modify-size
rpi3: enlarge SEC_DRAM0_SIZE for optee_test to pass
Dimitris Papastamos [Thu, 12 Jul 2018 10:52:53 +0000 (11:52 +0100)]
Merge pull request #1464 from antonio-nino-diaz-arm/an/rpi3-ints
rpi3: Implement simple interrupt routing
Dimitris Papastamos [Thu, 12 Jul 2018 09:11:28 +0000 (10:11 +0100)]
Merge pull request #1475 from sandrine-bailleux-arm/topics/sb/misra-fvp-opteed
Fix some violations to MISRA rules 8.3, 8.4, 8.5, 8.8
Dimitris Papastamos [Mon, 18 Jun 2018 12:01:06 +0000 (13:01 +0100)]
CSS: Use SCMI AP core protocol to set the warm boot entrypoint
Change-Id: Iaebbeac1a1d6fbd531e5694b95ed068b7a193e62
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
Dimitris Papastamos [Tue, 3 Apr 2018 13:58:17 +0000 (14:58 +0100)]
Add support for SCMI AP core configuration protocol v1.0
Change-Id: If07000b6b19011e960336a305a784dd643301b97
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
Anson Huang [Thu, 12 Jul 2018 06:43:06 +0000 (14:43 +0800)]
imx: imx8qm: add domain suspend/resume support
Add domain suspend/resume support, Linux kernel
can "echo mem > /sys/power/state" to put system
into suspend mode, all CPUs and cluster will be
powered off and can be waked up if irq pending
in GIC, tested on i.MX8QM MEK board.
Since the power state has been implemented, switch
to use standard power state for CCI operations
instead of private cpu use count in i.MX8QM.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Anson Huang [Thu, 12 Jul 2018 06:30:52 +0000 (14:30 +0800)]
imx: imx8qm: add domain off support
Add domain off support for Linux kernel's cpu
hot-plug feature, when there are cpu off request
from Linux kernel, TF-A will send command to
system controller to do CPU power gate accordingly,
tested on i.MX8QM MEK board.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Anson Huang [Thu, 12 Jul 2018 06:27:36 +0000 (14:27 +0800)]
imx: imx8qm: add system reset support
Add system reset support for i.MX8QM,
when Linux kernel issues "reboot" command,
TF-A will send command to inform system
controller to reset whole board according
to board design, tested on i.MX8QM MEK board.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Anson Huang [Thu, 12 Jul 2018 06:26:07 +0000 (14:26 +0800)]
imx: imx8qm: add system off support
Add system power off support for i.MX8QM,
when Linux kernel issues "poweroff" command,
TF-A will send command to inform system
controller to power off whole board according
to board design, tested on i.MX8QM MEK board.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Anson Huang [Thu, 12 Jul 2018 06:17:19 +0000 (14:17 +0800)]
imx: imx8qx: add domain suspend/resume support
Add domain suspend/resume support, Linux kernel
can "echo mem > /sys/power/state" to put system
into suspend mode, all CPUs and cluster will be
powered off and can be waked up if irq pending
in GIC, tested on i.MX8QX MEK board.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Ying-Chun Liu (PaulLiu) [Wed, 11 Jul 2018 15:32:59 +0000 (23:32 +0800)]
rpi3: enlarge SEC_DRAM0_SIZE for optee_test to pass
Running optee_test failed because SEC_DRAM0_SIZE is too small. Previous
is 2 MB. We enlarge it to 11 MB for passing the test. Also we reduce
the NS_DRAM0_SIZE from 13MB to 4MB so that the whole section is still
fit in 16MB.
This commit also modified the document to reflect the changes we've
made in code.
Tested-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org>
Anson Huang [Thu, 12 Jul 2018 03:07:10 +0000 (11:07 +0800)]
imx: imx8qx: add domain off support
Add domain off support for Linux kernel's cpu
hot-plug feature, when there are cpu off request
from Linux kernel, TF-A will send command to
system controller to do CPU power gate accordingly.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Anson Huang [Thu, 12 Jul 2018 03:04:15 +0000 (11:04 +0800)]
imx: imx8qx: add system reset support
Add system reset support for i.MX8QX,
when Linux kernel issues "reboot" command,
TF-A will send command to inform system
controller to reset whole board according
to board design, tested on i.MX8QX MEK board.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Anson Huang [Thu, 12 Jul 2018 02:52:55 +0000 (10:52 +0800)]
imx: imx8qx: add system off support
Add system power off support for i.MX8QX,
when Linux kernel issues "poweroff" command,
TF-A will send command to inform system
controller to power off whole board according
to board design, tested on i.MX8QX MEK board.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Antonio Nino Diaz [Wed, 11 Jul 2018 20:00:32 +0000 (21:00 +0100)]
rpi3: Implement simple interrupt routing
Implement minimal interrupt routing functions. All interrupts are
treated as non-secure interrupts to be handled by the non-secure world.
Add note to the documentation about disabling FIQs qhen using OP-TEE
with Linux.
Change-Id: I937096542d973925e43ae946c5d0b306d0d95a94
Tested-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Sandrine Bailleux [Wed, 11 Jul 2018 11:59:18 +0000 (13:59 +0200)]
ARM platforms: Make arm_lock static
The ARM_INSTANTIATE_LOCK macro defines a lock meant to be further
manipulated using the arm_lock_init/get/release() macros. It has 2
variants, depending on the BL image it is compiled for. One version
defines the lock variable with internal linkage whereas the other one,
with external linkage.
Code that uses these macros is not compliant with MISRA rule 8.4 because
when using the external linkage version, there is no visible declaration
for the lock variable.
This patch defines the arm_lock variable with internal linkage in both
cases. This fits well the way these macros are used in the code today,
where the lock is not used outside of the translation unit it is
defined in.
Change-Id: I213a74a2a6088a4f1e9a61a319ca7579c2001320
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Sandrine Bailleux [Wed, 11 Jul 2018 12:37:54 +0000 (14:37 +0200)]
ARM platforms: Remove some duplicate declarations
The plat_arm_mmap variable is already declared in plat_arm.h, which is
included from plat/arm/common/arm_common.c.
Similarly, plat_arm.h declares the 'plat_arm_psci_pm_ops' variable, which
does not need to be declared again in plat/arm/common/arm_pm.c.
The duplication was not compliant with MISRA rule 8.5.
Change-Id: Icc42547cc025023226b1078a7ec4f06d093364b7
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Sandrine Bailleux [Wed, 11 Jul 2018 10:44:22 +0000 (12:44 +0200)]
Fix some violations to MISRA rule 8.3
Wherever we use 'struct foo' and 'foo_t' interchangeably in a
function's declaration and definition, use 'struct foo' consistently
for both, as per the TF-A coding guidelines [1].
[1] https://github.com/ARM-software/arm-trusted-firmware/wiki/ARM-Trusted-Firmware-Coding-Guidelines#avoid-anonymous-typedefs-of-structsenums-in-header-files
Change-Id: I7998eb24a26746e87e9b6425529926406745b721
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Dimitris Papastamos [Wed, 11 Jul 2018 13:22:22 +0000 (14:22 +0100)]
Merge pull request #1474 from dp-arm/dp/cpus
Add initial CPU support for Cortex-Deimos and Cortex-Helios
Joel Hutton [Wed, 10 Jan 2018 16:06:07 +0000 (16:06 +0000)]
Add initial CPU support for Cortex-Helios
Change-Id: Ic0486131c493632eadf329f80b0b5904aed5e4ef
Signed-off-by: Joel Hutton <joel.hutton@arm.com>
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
Joel Hutton [Fri, 4 May 2018 14:09:47 +0000 (15:09 +0100)]
Add initial CPU support for Cortex-Deimos
Change-Id: I2c4b06423fcd96af9351b88a5e2818059f981f1b
Signed-off-by: Joel Hutton <Joel.Hutton@Arm.com>
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
Dimitris Papastamos [Wed, 11 Jul 2018 12:15:52 +0000 (13:15 +0100)]
Merge pull request #1473 from robertovargas-arm/misra
Misra
Dimitris Papastamos [Wed, 11 Jul 2018 10:13:36 +0000 (11:13 +0100)]
Merge pull request #1460 from robertovargas-arm/clang
Make TF compatible with Clang assembler and linker
Roberto Vargas [Mon, 23 Apr 2018 07:38:12 +0000 (08:38 +0100)]
Update documentation about how to use clang toolchain
Change-Id: Ie65eb779b048940cf32ed5744ff40610b3c5499d
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
Roberto Vargas [Thu, 10 May 2018 12:38:19 +0000 (13:38 +0100)]
Use clang as preprocessor when clang toolchain is selected
Change-Id: I562c5de91e12fe384245df41225dfb9122a13a85
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
Roberto Vargas [Mon, 16 Apr 2018 10:29:45 +0000 (11:29 +0100)]
Use clang assembler when clang compiler is used
Change-Id: Ib90b767e46360ef07c1f22526e3f3eb5fe366d5d
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
Roberto Vargas [Fri, 4 May 2018 09:54:33 +0000 (10:54 +0100)]
Remove integrity check in declare_cpu_ops_base
This check was added to ensure the correct behaviour of fill_constants
macro. This macro has been verified and it is known his correct
behaviour. The check generates an error when the clang assembler is
used, so it is better to remove the check.
Change-Id: I3447ff9e9e5ee5cf0502f65e53c3d105d9396b8b
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
Roberto Vargas [Tue, 1 May 2018 08:54:54 +0000 (09:54 +0100)]
Remove .struct directive
This directive is not implemented by clang assembler. The traditional
way to implement structs in assembly is using two macros for every field,
one for the offset, and another one for the size. For every field, the
offset can be calculated using the size and offset of the previous field.
Change-Id: Iacc6781e8f302fb925898737b8e85ab4e88a51cc
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
Roberto Vargas [Mon, 30 Apr 2018 16:58:58 +0000 (17:58 +0100)]
Remove string concatenation in assembler files
Clang assembler doesn't support concatenation of adjacent strings.
Change-Id: I092a1e30c137d431c6adcc13519fc2d595f92f14
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
Roberto Vargas [Tue, 17 Apr 2018 10:31:43 +0000 (11:31 +0100)]
Add end_vector_entry assembler macro
Check_vector_size checks if the size of the vector fits
in the size reserved for it. This check creates problems in
the Clang assembler. A new macro, end_vector_entry, is added
and check_vector_size is deprecated.
This new macro fills the current exception vector until the next
exception vector. If the size of the current vector is bigger
than 32 instructions then it gives an error.
Change-Id: Ie8545cf1003a1e31656a1018dd6b4c28a4eaf671
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
Roberto Vargas [Tue, 17 Apr 2018 10:31:43 +0000 (11:31 +0100)]
Remove .func and .endfunc assembler directives
These directives are only used when stabs debugging information
is used, but we use ELF which uses DWARF debugging information.
Clang assembler doesn't support these directives, and removing
them makes the code more compatible with clang.
Change-Id: I2803f22ebd24c0fe248e04ef1b17de9cec5f89c4
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
Roberto Vargas [Fri, 13 Apr 2018 13:26:47 +0000 (14:26 +0100)]
Allow overriding the linker
This patch allows the user to override the value of the LD Makefile
variable. This feature can be used to force the use of the new Clang
linker.
Change-Id: I97ffeb18e48fa75346702a479d7dc1e8abcb3621
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
Roberto Vargas [Thu, 10 May 2018 10:01:16 +0000 (11:01 +0100)]
Add .extab and .exidx sections
These sections are required by clang when the code is compiled for
aarch32. These sections are related to the unwind of the stack in
exceptions, but in the way that clang defines and uses them, the
garbage collector cannot get rid of them.
Change-Id: I085efc0cf77eae961d522472f72c4b5bad2237ab
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>