Tom Rini [Tue, 10 Dec 2013 14:33:13 +0000 (09:33 -0500)]
Merge branch 'master' of git://git.denx.de/u-boot-mmc
Tom Rini [Tue, 10 Dec 2013 14:29:45 +0000 (09:29 -0500)]
Merge branch 'master' of git://git.denx.de/u-boot-i2c
Kuo-Jung Su [Mon, 25 Nov 2013 02:51:41 +0000 (10:51 +0800)]
mmc: add Faraday FTSDC021 SDHCI controller support
Faraday FTSDC021 is a controller which is compliant with
SDHCI v3.0, SDIO v2.0 and MMC v4.3.
However this driver is only verified with SD memory cards.
Signed-off-by: Kuo-Jung Su <dantesu@faraday-tech.com>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
CC: Andy Fleming <afleming@gmail.com>
Priyanka Jain [Thu, 28 Nov 2013 04:42:16 +0000 (10:12 +0530)]
powerpc: mmc: Add corenet devices support in esdhc spl
Existing eSDHC SPL framework assumes booting from sd-image
with boot_format header which contains final u-boot Image
offset and size. No such header is present in case of
corenet devices like T1040 as corenet deivces use PBI-RCW
based intialization.
So, for corenet deives, SPL bootloader use values provided
at compilation time. These values can be defined in board
specific config file.
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
Alexey Brodkin [Wed, 27 Nov 2013 13:00:52 +0000 (17:00 +0400)]
mmc/dwmmc: modify FIFO threshold only if value explicitly set
If platform provides "host->fifoth_val" it will be used for
initialization of DWMCI_FIFOTH register. Otherwise default value will be
used.
This implementation allows:
* escape unclear and recursive calculations that are currently in use
* use whatever custom value for DWMCI_FIFOTH initialization if any
particular SoC requires it
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Mischa Jonker <mjonker@synopsys.com>
Cc: Alim Akhtar <alim.akhtar@samsung.com>
Cc: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Amar <amarendra.xt@samsung.com>
Cc: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: Andy Fleming <afleming@freescale.com>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
Jaehoon Chung [Fri, 29 Nov 2013 11:08:57 +0000 (20:08 +0900)]
mmc: dw_mmc: remove the exynos specific code in dw-mmc.c
dw-mmc.c is the general driver file.
So, remove the exynos specific code at dw-mmc.c.
Instead, exynos specific cod can be move into exynos-dw_mmc.c.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Acked-by: Alexey Brodkin <abrodkin@synopsys.com>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
Acked-by: Minkyu Kang <mk7.kang@samsung.com>
Tom Rini [Fri, 6 Dec 2013 12:19:09 +0000 (07:19 -0500)]
Merge branch 'master' of git://git.denx.de/u-boot-blackfin
Masahiro Yamada [Fri, 29 Nov 2013 06:34:16 +0000 (15:34 +0900)]
blackfin: Do not generate unused header bootrom-asm-offsets.h
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Axel Lin [Mon, 2 Dec 2013 04:57:44 +0000 (12:57 +0800)]
spi: bfin_spi6xx: Remove unnecessary test for bus and pins[bus]
For invalid bus number, current code returns NULL in the default case of
switch-case statements. In additional, pins[bus] is always not NULL because
it is the address of specific row of the two-dimensional array.
Thus this patch removes these unnecessary test.
Signed-off-by: Axel Lin <axel.lin@ingics.com>
Acked-by: Scott Jiang <scott.jiang.linux@gmail.com>
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Axel Lin [Mon, 2 Dec 2013 04:57:33 +0000 (12:57 +0800)]
spi: bfin_spi: Remove unnecessary test for bus and pins[bus]
For invalid bus number, current code returns NULL in the default case of
switch-case statements. In additional, pins[bus] is always not NULL because
it is the address of specific row of the two-dimensional array.
Thus this patch removes these unnecessary test.
Signed-off-by: Axel Lin <axel.lin@ingics.com>
Acked-by: Scott Jiang <scott.jiang.linux@gmail.com>
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Sonic Zhang [Mon, 18 Nov 2013 10:59:18 +0000 (18:59 +0800)]
blackfin: soft-i2c: No need to define blackfin specific soft i2c operations
Use default GPIO operations.
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Acked-by: Heiko Schocher <hs@denx.de>
Sonic Zhang [Mon, 18 Nov 2013 06:50:19 +0000 (14:50 +0800)]
blackfin: Add missing macro CONFIG_BFIN_SERIAL
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Sonic Zhang [Mon, 18 Nov 2013 06:12:39 +0000 (14:12 +0800)]
blackfin: If none ADI_GPIOX macro is defined, use ADI_GPIO1 as default
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Sonic Zhang [Mon, 18 Nov 2013 06:01:38 +0000 (14:01 +0800)]
blackfin: Use ADI_GPIO2 driver other than the default ADI_GPIO1
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Naveen Krishna Ch [Fri, 6 Dec 2013 06:42:38 +0000 (12:12 +0530)]
i2c: samsung: register i2c busses for Exynso5420 and Exynos5250
This patch adds the U_BOOT_I2C_ADAP_COMPLETE defines for channels
on Exynos5420 and Exynos5250 and also adds support for init function
for hsi2c channels
Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
Nikita Kiryanov [Thu, 28 Nov 2013 16:04:42 +0000 (18:04 +0200)]
arm: omap: i2c: don't zero cnt in i2c_write
Writing zero into I2Ci.I2C_CNT register causes random I2C failures in OMAP3
based devices. This seems to be related to the following advisory which
apears in multiple erratas for OMAP3 SoCs (OMAP35xx, DM37xx), as well as
OMAP4430 TRM:
Advisory:
I2C Module Does Not Allow 0-Byte Data Requests
Details:
When configured as the master, the I2C module does not allow 0-byte data
transfers. Note: Programming I2Ci.I2C_CNT[15:0]: DCOUNT = 0 will cause
undefined behavior.
Workaround(s):
No workaround. Do not use 0-byte data requests.
The writes in question are unnecessary from a functional point of view.
Most of them are done after I/O has finished, and the only one that preceds
I/O (in i2c_probe()) is also unnecessary because a stop bit is sent before
actual data transmission takes place.
Therefore, remove all writes that zero the cnt register.
Cc: Heiko Schocher <hs@denx.de>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Tom Rini <trini@ti.com>
Cc: Lubomir Popov <lpopov@mm-sol.com>
Cc: Enric Balletbo Serra <eballetbo@gmail.com>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-by: Lubomir Popov <lpopov@mm-sol.com>
Kuo-Jung Su [Mon, 2 Dec 2013 08:02:59 +0000 (16:02 +0800)]
cmd_eeprom: bug fix for i2c read/write
The local pointer of address (i.e., addr) only gets
referenced under SPI mode, and it won't be appropriate
to pass only 1-byte addr[1] to i2c_read/i2c_write while
CONFIG_SYS_I2C_EEPROM_ADDR_LEN > 1.
1. In U-boot's I2C model, the address would be re-assembled
to a byte string in MSB order inside I2C controller drivers.
2. The 'CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW' option which could
be found at soft_i2c.c is always turned on in cmd_eeprom.c,
the addr[0] always contains the device address with overflowed
MSB address bits.
Signed-off-by: Kuo-Jung Su <dantesu@faraday-tech.com>
Cc: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
cc: Peter Tyser <ptyser@xes-inc.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Mischa Jonker <mjonker@synopsys.com>
Kuo-Jung Su [Mon, 2 Dec 2013 08:02:58 +0000 (16:02 +0800)]
i2c: fti2c010: serial out r/w address in MSB order
For a eeprom with a 2-bytes address (e.g., Ateml AT24C1024B),
the r/w address should be serial out in MSB order.
Signed-off-by: Kuo-Jung Su <dantesu@faraday-tech.com>
Cc: Heiko Schocher <hs@denx.de>
Kuo-Jung Su [Mon, 2 Dec 2013 08:02:57 +0000 (16:02 +0800)]
i2c: fti2c010: migrate to new i2c model
Replace the legacy i2c model with the new one.
Signed-off-by: Kuo-Jung Su <dantesu@faraday-tech.com>
Cc: Heiko Schocher <hs@denx.de>
Kuo-Jung Su [Mon, 2 Dec 2013 08:02:56 +0000 (16:02 +0800)]
i2c: fti2c010: cosmetic: coding style cleanup
Coding style cleanup
Signed-off-by: Kuo-Jung Su <dantesu@faraday-tech.com>
Cc: Heiko Schocher <hs@denx.de>
Piotr Wilczek [Wed, 20 Nov 2013 09:43:50 +0000 (10:43 +0100)]
driver:i2c:s3c24x0: fix clock init for hsi2c
Fix clock value initialisation for Exynos other than Exynos5 for hsi2c.
Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Heiko Schocher <hs@denx.de>
Piotr Wilczek [Wed, 20 Nov 2013 09:43:49 +0000 (10:43 +0100)]
driver:i2c:s3c24x0: adapt driver to new i2c
This patch adapts the s3c24x0 driver to the new i2c framework.
Config file is modified for all the boards that use the driver.
Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
CC: Minkyu Kang <mk7.kang@samsung.com>
CC: Heiko Schocher <hs@denx.de>
CC: Inderpal Singh <inderpal.singh@linaro.org>
CC: David Müller <d.mueller@elsoft.ch>
CC: Chander Kashyap <k.chander@samsung.com>
CC: Lukasz Majewski <l.majewski@samsung.com>
Tested-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
Reviewed-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
York Sun [Tue, 3 Dec 2013 21:16:59 +0000 (13:16 -0800)]
powerpc/mpc8349: Use generic mpc85xx DDR driver
MPC8349 has been using mpc85xx DDR driver through a symbolic link to
mpc85xx_ddr_gen2.c. After consolidating the drivers to a single set
under driver/ddr/fsl/, the link is replaced by referring driver
directly. We now can simply enable the macro and use the driver.
Other mpc83xx SoCs still use their own driver.
Signed-off-by: York Sun <yorksun@freescale.com>
Shengzhou Liu [Wed, 4 Dec 2013 06:21:05 +0000 (14:21 +0800)]
powerpc/t2080qds: undef CONFIG_FSL_DDR_INTERACTIVE
Usually CONFIG_FSL_DDR_INTERACTIVE feature is used for debug.
we would not enable this by default to save the limited space of u-boot.
This avoid following compiling error:
section .bootpg loaded at [
00000000effff000,
00000000effff577] overlap ssection
.data loaded at [
00000000efff31b8,
00000000f00010c7]
u-boot: section .bootpg lma 0xeffff000 adjusted to 0xf00010c8
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
Zang Roy-R61911 [Thu, 28 Nov 2013 05:23:37 +0000 (13:23 +0800)]
T4240: Address T4240/T4160 Rev2.0 DDR clock change
MEM_PLL_RAT on T4240/T4160 Rev2.0 uses a value which is half of Rev1.0.
It's 12 in Rev1.0, for Rev2.0 it uses 6.
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
Priyanka Jain [Thu, 28 Nov 2013 04:38:12 +0000 (10:08 +0530)]
powerpc: spiflash:Add corenet devices support in eSPI SPL
Existing eSPI SPL framework assumes booting from spi-image
with boot_format header which contains final u-boot Image
offset and size. No such header is present in case of
corenet devices like T1040 as corenet deivces use PBI-RCW
based intialization.
So, for corenet deives, SPL bootloader use values provided
at compilation time. These values can be defined in board
specific config file.
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
Po Liu [Tue, 26 Nov 2013 06:34:07 +0000 (14:34 +0800)]
powerpc/c29xpcie: Getting DDR SPD image from 16-bit sub-address EEPROM
Currently, there is only one EEPROM on c29xpcie board which is AT24C1024.
We program the SPD data at beginning of the AT24C1024.But the AT24C1024
has a 16-bit sub-address mode. This patch is tomake it work when getting
SPD in a 16-bit sub-address EEPROM.
Signed-off-by: Po Liu <Po.Liu@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
Zhao Qiang [Tue, 26 Nov 2013 05:59:15 +0000 (13:59 +0800)]
powerpc/p1010rdb:modify the mtest start_address
In new board P1010RDB-PB, the interrupt vector table is at
the start of memory. So if the start_address needs to be set
a proper value.
Signed-off-by: Zhao Qiang <B45475@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
Dave Liu [Thu, 28 Nov 2013 06:58:08 +0000 (14:58 +0800)]
powerpc/corenet: CPC1 speculation disable
In PBL RAMBOOT(SPI/SD/NAND boot) mode, CPC1 used as SRAM, should disable
CPC1 speculation and keep it till relocation. Otherwise, speculation
transactions will go to DDR controller, it will cause problem.
Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
Tom Rini [Mon, 2 Dec 2013 13:48:02 +0000 (08:48 -0500)]
Merge branch 'serial' of git://git.denx.de/u-boot-microblaze
Tom Rini [Mon, 2 Dec 2013 13:44:28 +0000 (08:44 -0500)]
Merge branch 'master' of git://git.denx.de/u-boot-mips
Masahiro Yamada [Thu, 21 Nov 2013 07:10:20 +0000 (16:10 +0900)]
Blackfin: remove executable permission of AWK script
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Tom Rini [Mon, 2 Dec 2013 13:38:28 +0000 (08:38 -0500)]
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
Soren Brinkmann [Tue, 29 Oct 2013 20:11:54 +0000 (13:11 -0700)]
serial: zynq: Remove unused #defines
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Series-to: trini, uboot
Paul Burton [Tue, 26 Nov 2013 17:45:28 +0000 (17:45 +0000)]
malta: set CONFIG_SYS_BOOTM_LEN to 64MB
Allow a larger kernel binary to be decompressed - the default 8MB can
become limiting on a Malta.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Paul Burton [Tue, 26 Nov 2013 17:45:27 +0000 (17:45 +0000)]
malta: enable PIIX4 SERIRQ
Whilst U-boot does not require this itself, Linux currently relies upon
it having been muxed and enabled by the bootloader. Thus in order to
preserve compatibility with current kernels before a fix is merged in
Linux we will enable the SERIRQ interrupt and mux it to its pin.
Without doing this current kernels will never receive serial port
interrupts and the end result is typically that userland appears to
hang.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Paul Burton [Tue, 26 Nov 2013 17:45:26 +0000 (17:45 +0000)]
malta: correct UART baudrate
CONFIG_SYS_NS16550_CLK specifies the rate of the clock 16x the baud
rate. The SMSC FDC37M81x datasheet states that a divider of 1 results in
a UART at 115200 baud, thus the x16 clock rate is 115200 * 16.
Previously the divider was left at 0 which led to a rate of 38400 baud
regardless of CONFIG_BAUDRATE or the baudrate environment variable.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Paul Burton [Tue, 26 Nov 2013 17:45:25 +0000 (17:45 +0000)]
mips: don't hardcode Malta env baudrate
The baudrate passed to Linux in the environment was hardcoded at 38400.
Instead pass the correct baudrate from global data, allowing Linux to
correctly inherit the baudrate used by U-boot when console setup is not
explicitly specified.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Tom Rini [Mon, 25 Nov 2013 21:49:32 +0000 (16:49 -0500)]
Prepare v2014.01-rc1
Signed-off-by: Tom Rini <trini@ti.com>
Shengzhou Liu [Fri, 22 Nov 2013 09:39:12 +0000 (17:39 +0800)]
t2080qds/ramboot: enable PBL tool for t2080qds
Add the default RCW(SerDes 0x66_0x16) and PBI configure file for
T2080QDS board, so we can use PBL tool to generate the ramboot
image to support boot from NAND/SPI/SD.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Shengzhou Liu [Fri, 22 Nov 2013 09:39:11 +0000 (17:39 +0800)]
powerpc/t2080qds: add support for t2080qds board
The T2080QDS is a high-performance computing evaluation, development and
test platform supporting the T2080 QorIQ Power Architecture processor.
T2080QDS feature overview
Processor:
- T2080 SoC integrating four 64-bit dual-threads e6500 cores up to 1.8GHz
Memory:
- Single memory controller capable of supporting DDR3 and DDR3-LV devices
- Two DDR3 DIMMs up to 4GB, Dual rank @ 2133MT/s and ECC support
Ethernet interfaces:
- Two 1Gbps RGMII on-board ports
- Four 10Gbps XFI on-board cages
- 1Gbps/2.5Gbps SGMII Riser card
- 10Gbps XAUI Riser card
Accelerator:
- DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC
SerDes:
- 16 lanes up to 10.3125GHz
- Supports Aurora debug, PEX, SATA, SGMII, sRIO, HiGig, XFI and XAUI
IFC:
- 128MB NOR Flash, 512MB NAND Flash, PromJet debug port and FPGA
eSPI:
- Three SPI flash (16MB N25Q128A + 16MB EN25S64 + 512KB SST25WF040)
USB:
- Two USB2.0 ports with internal PHY (one Type-A + one micro Type-AB)
PCIE:
- Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV)
SATA:
- Two SATA 2.0 ports on-board
SRIO:
- Two Serial RapidIO 2.0 ports up to 5 GHz
eSDHC:
- Supports SD/SDHC/SDXC/eMMC Card
I2C:
- Four I2C controllers.
UART:
- Dual 4-pins UART serial ports
System Logic:
- QIXIS-II FPGA system controll
Debug Features:
- Support Legacy, COP/JTAG, Aurora, Event and EVT
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
[York Sun: removed Makefile blank line at EOF,
fix conflicts with moving DDR driver]
Acked-by: York Sun <yorksun@freescale.com>
Shengzhou Liu [Fri, 22 Nov 2013 09:39:10 +0000 (17:39 +0800)]
powerpc/mpc85xx: Add T2080/T2081 SoC support
Add support for Freescale T2080/T2081 SoC.
T2080 includes the following functions and features:
- Four dual-threads 64-bit Power architecture e6500 cores, up to 1.8GHz
- 2MB L2 cache and 512KB CoreNet platform cache (CPC)
- Hierarchical interconnect fabric
- One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
- Data Path Acceleration Architecture (DPAA) incorporating acceleration
- 16 SerDes lanes up to 10.3125 GHz
- 8 mEMACs for network interfaces (four 1Gbps MACs and four 10Gbps/1Gbps MACs)
- High-speed peripheral interfaces
- Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV)
- Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz
- Additional peripheral interfaces
- Two serial ATA (SATA 2.0) controllers
- Two high-speed USB 2.0 controllers with integrated PHY
- Enhanced secure digital host controller (SD/SDHC/SDXC/eMMC)
- Enhanced serial peripheral interface (eSPI)
- Four I2C controllers
- Four 2-pin UARTs or two 4-pin UARTs
- Integrated Flash Controller supporting NAND and NOR flash
- Three eight-channel DMA engines
- Support for hardware virtualization and partitioning enforcement
- QorIQ Platform's Trust Architecture 2.0
Differences between T2080 and T2081:
Feature T2080 T2081
1G Ethernet numbers: 8 6
10G Ethernet numbers: 4 2
SerDes lanes: 16 8
Serial RapidIO,RMan: 2 no
SATA Controller: 2 no
Aurora: yes no
SoC Package: 896-pins 780-pins
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
Shengzhou Liu [Fri, 22 Nov 2013 09:39:09 +0000 (17:39 +0800)]
net/fman: Add support for 10GEC3 and 10GEC4
There are more than two 10GEC in single FMAN in some SoCs(e.g. T2080).
This patch adds support for 10GEC3 and 10GEC4.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
York Sun [Tue, 22 Oct 2013 19:39:02 +0000 (12:39 -0700)]
Driver/IFC: Move Freescale IFC driver to a common driver
Freescale IFC controller has been used for mpc8xxx. It will be used
for ARM-based SoC as well. This patch moves the driver to driver/misc
and fix the header file includes.
Signed-off-by: York Sun <yorksun@freescale.com>
York Sun [Mon, 28 Oct 2013 23:36:02 +0000 (16:36 -0700)]
Driver/DDR: Update DDR driver to allow non-zero base address
The DRAM base has been zero for Power SoCs. It could be non-zero
for ARM SoCs. Use a macro instead of hard-coding to zero.
Signed-off-by: York Sun <yorksun@freescale.com>
York Sun [Mon, 3 Jun 2013 19:39:06 +0000 (12:39 -0700)]
powerpc/mpc8xxx: Extend DDR registers' fields
Some DDR registers' fields have expanded to accommodate larger values.
These changes are backward compatible. Some fields are removed for newer
DDR controllers. Writing to those fields are safely ignored.
TIMING_CFG_2 register is fixed. Additive latency is added to RD_TO_PRE
automatically. It was a misunderstanding in commit
c360ceac.
Signed-off-by: York Sun <yorksun@freescale.com>
York Sun [Mon, 30 Sep 2013 21:20:51 +0000 (14:20 -0700)]
Driver/DDR: Add Freescale DDR driver for ARM
Make PowerPC specific code conditional so ARM SoCs can reuse
this driver. Add DDR3 driver for ARM.
Signed-off-by: York Sun <yorksun@freescale.com>
York Sun [Mon, 18 Nov 2013 18:29:32 +0000 (10:29 -0800)]
Driver/DDR: combine ccsr_ddr for 83xx, 85xx and 86xx
Fix ccsr_ddr structure to avoid using typedef. Combine DDR2 and DDR3
structure for 83xx, 85xx and 86xx.
Signed-off-by: York Sun <yorksun@freescale.com>
York Sun [Mon, 30 Sep 2013 16:22:09 +0000 (09:22 -0700)]
Driver/DDR: Moving Freescale DDR driver to a common driver
Freescale DDR driver has been used for mpc83xx, mpc85xx, mpc86xx SoCs.
The similar DDR controllers will be used for ARM-based SoCs.
Signed-off-by: York Sun <yorksun@freescale.com>
Zhao Qiang [Thu, 26 Sep 2013 01:10:32 +0000 (09:10 +0800)]
p1010rdb: enable mtdparts for NAND
The default partition table matches the .dts files for these boards in
Linux. This allows these partitions to be used by name with U-Boot's
"nand" command.
Signed-off-by: Zhao Qiang <B45475@freescale.com>
Tang Yuantian [Thu, 17 Oct 2013 02:47:33 +0000 (10:47 +0800)]
mpc85xx: Fix the offset of register address error
The offset of register address within GPIO module is just
CONFIG_SYS_MPC85xx_GPIO_ADDR. So, fix it. The following platforms
are confirmed: MPC8572, P1023, P1020, P1022, P2020, P4080,
P5020, P5040, T4240, B4860.
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Priyanka Jain [Fri, 25 Oct 2013 09:56:27 +0000 (15:26 +0530)]
powerpc/t1040qds: Correct Maintainer name in boards.cfg
Update T1040QDS naem to Poonam Aggrwal.
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Tom Rini [Mon, 25 Nov 2013 15:42:53 +0000 (10:42 -0500)]
Merge branch 'sandbox1' of git.denx.de/u-boot-x86
Tom Rini [Mon, 25 Nov 2013 15:42:19 +0000 (10:42 -0500)]
Merge branch 'master' of git://git.denx.de/u-boot-net
Tom Rini [Mon, 25 Nov 2013 15:42:13 +0000 (10:42 -0500)]
Merge branch 'master' of git://git.denx.de/u-boot-nand-flash
Tom Rini [Mon, 25 Nov 2013 15:42:05 +0000 (10:42 -0500)]
Merge branch 'buildpatman' of git.denx.de/u-boot-x86
Tom Rini [Mon, 18 Nov 2013 13:31:56 +0000 (08:31 -0500)]
sparc: Correct arch/sparc/cpu/leon3/start.S from SPDX conversion
The SPDX tag conversion ate part of this file, put things back to the
way they should be.
Signed-off-by: Tom Rini <trini@ti.com>
Wolfgang Denk [Tue, 19 Nov 2013 07:01:44 +0000 (08:01 +0100)]
blackfin: don't use 'bool' when it causes problems
The use of 'bool' data types in globally used header files cases build
errors like this:
In file included from arch/blackfin/include/asm/blackfin.h:13:0,
from include/common.h:92,
from cmd_test.c:17:
arch/blackfin/include/asm/blackfin_local.h:54:1: error: unknown type name 'bool'
Use plain 'int' instead to avoid such kind of trouble.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Masahiro Yamada [Thu, 21 Nov 2013 10:06:58 +0000 (19:06 +0900)]
MAKEALL: add -b (--board) option
Some board have multiple configurations.
For example, the board "m54455evb" has many configurations:
M54455EVB, M54455EVB_a66, M54455EVB_i66, M54455EVB_intel, ...
When we modify board-related files, we need to test
all configurations based on such a board.
In such a case, the new option -b is useful.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Masahiro Yamada [Wed, 20 Nov 2013 09:14:23 +0000 (18:14 +0900)]
bios_emulator: delete an unnecessary include path
-I$(TOPDIR)/include is defined in the top config.mk.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Masahiro Yamada [Wed, 20 Nov 2013 09:11:57 +0000 (18:11 +0900)]
nand_spl: trivial refactoring of makefiles
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Masahiro Yamada [Wed, 20 Nov 2013 03:45:56 +0000 (12:45 +0900)]
Makefile: descend into subdirectories only when CONFIG_API is defined
All objects under api/ and examples/api/ directories are selected
by CONFIG_API.
So we can move CONFIG_API switch to the top Makefile.
In order to use CONFIG_API, the definition of SUBDIR_EXAMPLES-y
must be moved after "sinlude $(obj)include/autoconf.mk".
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Masahiro Yamada [Mon, 18 Nov 2013 07:24:58 +0000 (16:24 +0900)]
common: Delete unnecessary rules.
The directory tools/ is always built before common/.
So when envcrc tool is necessary in common/Makefile,
it already exists.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Masahiro Yamada [Mon, 18 Nov 2013 02:18:57 +0000 (11:18 +0900)]
drivers: delete unnecessary HOSTCFLAGS
HOSTCFLAGS is meaningless because no host programs
are compiled there.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Masahiro Yamada [Mon, 18 Nov 2013 02:17:30 +0000 (11:17 +0900)]
Makefile: move some libraries to lib/Makefile
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Masahiro Yamada [Mon, 18 Nov 2013 02:08:35 +0000 (11:08 +0900)]
Makefile: descend into subdirectories only when CONFIG_API is defined
All objects under api/ and examples/api/ directories are selected
by CONFIG_API.
So we can move CONFIG_API switch to the top Makefile.
In order to use CONFIG_API, the definition of SUBDIR_EXAMPLES-y
must be moved after "sinlude $(obj)include/autoconf.mk".
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Masahiro Yamada [Mon, 18 Nov 2013 02:06:00 +0000 (11:06 +0900)]
examples: delete unnecessary CPPFLAGS
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Masahiro Yamada [Mon, 18 Nov 2013 01:39:39 +0000 (10:39 +0900)]
board: tqm5200: delete its own object make rule
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Masahiro Yamada [Mon, 18 Nov 2013 01:34:36 +0000 (10:34 +0900)]
spieval: Remove remainders of dead board
Commit
69434e4c deleted spieval board support
but it missed to clean up include/configs/spieval.h file.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Masahiro Yamada [Mon, 18 Nov 2013 01:25:41 +0000 (10:25 +0900)]
post: remove unnecessary include path settings
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Masahiro Yamada [Mon, 18 Nov 2013 00:44:54 +0000 (09:44 +0900)]
board: h2200: Delete an unnecessary make rule
We have a generic rule to generate .o file from *.S
in $(TOPDIR)/config.mk.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Masahiro Yamada [Thu, 14 Nov 2013 02:00:30 +0000 (11:00 +0900)]
tools: updater: Remove remainders of dead board
tools/updater needs board/MAI/AmigaOneG3SE board
for compiling.
But AmigaOneG3SE board was already deleted
by Commit
953b7e6.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Masahiro Yamada [Thu, 14 Nov 2013 01:58:56 +0000 (10:58 +0900)]
tools: imls: Remove a broken and unused tool.
It looks like tools/imls/Makefile is invoked from nowhere.
And also it is broken.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Igor Grinberg [Thu, 7 Nov 2013 23:03:52 +0000 (01:03 +0200)]
gpio_led: add support for inverted polarity
Some GPIO connected LEDs have inverted polarity.
Introduce new config option: CONFIG_GPIO_LED_INVERTED_TABLE for the
specifying the inverted GPIO LEDs list and add support for this in the
gpio_led driver.
Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
Tested-by: Ilya Ledvich <ilya@compulab.co.il>
Igor Grinberg [Thu, 7 Nov 2013 23:03:51 +0000 (01:03 +0200)]
gpio_led: check gpio_request() return value
Add a check for the gpio_request() function return value and do not try
to configure the GPIO if the gpio_request() call fails.
Also, print an error message indicating the gpio_request() has failed.
Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
Tested-by: Ilya Ledvich <ilya@compulab.co.il>
Igor Grinberg [Thu, 7 Nov 2013 23:03:50 +0000 (01:03 +0200)]
README: document the CONFIG_GPIO_LED symbol
The CONFIG_GPIO_LED symbol does not have any documentation in the README
file. Document the CONFIG_GPIO_LED symbol.
Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
Tom Rini [Thu, 7 Nov 2013 12:39:48 +0000 (07:39 -0500)]
hash.c: Correct non-hash subcommand crc32 addr-save support
In the case of not having CONFIG_CMD_HASH but having CONFIG_CMD_CRC32
enabled (and not CONFIG_CRC32_VERIFY), we end up in this part of the
code path on hash_command(). However, we will only have exactly 3 args
here, and 3 > 3 is false, and we will not try and store the hash at the
address given as arg #3. The next problem however is that we've been
moving argv around so the third value is now in argv[0] not argv[3].
Confirmed on AM335x Beaglebone White.
Signed-off-by: Tom Rini <trini@ti.com>
Thierry Reding [Fri, 20 Sep 2013 14:03:43 +0000 (16:03 +0200)]
net: rtl8169: Add support for RTL8168d/8111d
This chip is compatible with the existing driver, except that it uses
BAR2 instead of BAR1 for the I/O memory region. Using this patch I can
use the PCIe ethernet interface on the CompuLab Trimslice to boot from
the network.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Patch: 276477
Thierry Reding [Fri, 20 Sep 2013 14:03:42 +0000 (16:03 +0200)]
net: rtl8169: Improve cache maintenance
Instead of directly calling the low-level invalidate_dcache_range() and
flush_cache() functions, provide thin wrappers that take into account
alignment requirements.
While at it, fix a case where the cache was flushed but should have been
invalidated, two cases where the buffer data was flushed instead of the
descriptor and a missing cache invalidation before reading the packet
data that the NIC just wrote to memory.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Patch: 276474
Srikanth Thokala [Fri, 8 Nov 2013 17:25:48 +0000 (22:55 +0530)]
net: zynq_gem: Add d-cache support
Added d-cache support for zynq_gem.c,
Observed a difference of +0.8 MiB/s when downloading
a file of size of 3007944Bytes.
With d-cache OFF:
----------------
Filename 'uImage'.
Load address: 0x800
Loading: #################################################################
#################################################################
#################################################################
##########
1.3 MiB/s
done
Bytes transferred =
3007944 (2de5c8 hex)
With d-cache ON:
---------------
Filename 'uImage'.
Load address: 0x800
Loading: #################################################################
#################################################################
#################################################################
##########
2.1 MiB/s
done
Bytes transferred =
3007944 (2de5c8 hex)
Changes on zynq_gem for d-cache support:
- Tx and Rx buffers are cache-aligned
- Updated logic for invalidating Rx buffers and flushing Tx buffers.
- Tx and Rx BD's are allocated from non-cacheable region.
(When BDs are cached, we don't see a consistent link)
- Use TX BD status intead of txsr status checks.
Signed-off-by: Srikanth Thokala <sthokal@xilinx.com>
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
David Dueck [Tue, 5 Nov 2013 16:23:03 +0000 (17:23 +0100)]
phy: Use general phy code for smsc lan8720a
Signed-off-by: David Dueck <davidcdueck@googlemail.com>
David Dueck [Tue, 5 Nov 2013 16:23:02 +0000 (17:23 +0100)]
phy: Use supported field during autonegotiation
The current code incorrectly detects gigabit capabilities for some
100Mbit/s phys. (lan8720a)
Signed-off-by: David Dueck <davidcdueck@googlemail.com>
Andrew Ruder [Wed, 23 Oct 2013 00:09:02 +0000 (19:09 -0500)]
net: dm9000: random mac address support
When an unprogrammed EEPROM is attached to a dm9000, the dm9000 will
come up with a invalid MAC address of ff:ff:ff:ff:ff:ff. Add code that
gets enabled if CONFIG_RANDOM_MACADDR is enabled that generates a random
(and valid) locally administered MAC address that allows the system to
network boot until a real MAC address can be configured.
Signed-off-by: Andrew Ruder <andrew.ruder@elecsyscorp.com>
Rojhalat Ibrahim [Mon, 7 Oct 2013 16:30:39 +0000 (18:30 +0200)]
drivers/net/e1000: Introduce CONFIG_E1000_NO_NVM
The e1000 driver expects to always have some kind of non-volatile memory
attached directly to the ethernet controller chip. This means that I would
have to add an additional separate flash chip to my custom board just to
store essentially the MAC address. Since I don't want to do that, this patch
introduces a new config option CONFIG_E1000_NO_NVM. If defined it disables
all accesses to the NVM. I have tested the patch with a 82574 controller.
Signed-off-by: Rojhalat Ibrahim <imr@rtschenk.de>
Andrew Ruder [Wed, 23 Oct 2013 00:10:28 +0000 (19:10 -0500)]
net: tftpsrv: Get correct client MAC address
NetServerEther was not being cleared in the tftp server code, so the
destination MAC address would be whatever the last destination MAC
address was.
Scenario:
U-Boot:
dhcp
tftpsrv
Host:
Send device WRQ
Device:
Responds with ACK to dhcp server mac address with
host ip address
By clearing NetServerEther, we force a lookup of the host MAC address
to go with the associated host IP.
Signed-off-by: Andrew Ruder <andrew.ruder@elecsyscorp.com>
Fabio Estevam [Sat, 2 Nov 2013 18:40:42 +0000 (16:40 -0200)]
net: phy: atheros: Fix masks for AR8035 and AR8021
The masks were ignoring the last 4 bits which didn't allow detection differences
between the ar8031 and ar8035.
Signed-off-by: Jon Nettleton <jon.nettleton@gmail.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Patch: 288018
Chunhe Lan [Fri, 1 Nov 2013 09:17:44 +0000 (17:17 +0800)]
net/phy: Fix the phy id mask of AR8031
The both AR8031 and AR8035 belong to Atheros 803x serial PHY.
So the phy id mask of AR8031 is the same to the phy id mask
of AR8035. The right mask value is 0x4fffff.
This patch has been tested on the P1010 and P1023.
Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Patch: 287748
Claudiu Manoil [Mon, 30 Sep 2013 09:44:47 +0000 (12:44 +0300)]
net: tsec: Fix mac addr setup portability, cleanup
Fix the 32-bit memory access that is not "endianess safe",
i.e. not giving the desired byte layout for LE cpus:
tempval = *((uint *) (tmpbuf + 4)), where 'char tmpbuf[]'.
Free the stack from rendundant local vars:
tmpbuf[] and i.
Use a portable type (u32) for the 32bit tsec register value
holder: tempval.
Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
Claudiu Manoil [Mon, 30 Sep 2013 09:44:46 +0000 (12:44 +0300)]
net: tsec: Use portable regs type (uint->u32)
Use cross arch portable u32 instead of uint for the
tsec registers. Remove the typedefs for the register
struct definitions in the process. Fix long lines.
Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
Claudiu Manoil [Fri, 4 Oct 2013 16:13:53 +0000 (19:13 +0300)]
net: tsec: Use portable types and accessors for BDs
Currently, the buffer descriptor (BD) fields cannot be
correctly accessed by a little endian processor. This
patch fixes the issue by making the access of BDs to be
portable among different cpu architectures.
Use portable data types for the Rx/Tx buffer descriptor
fields. Use portable I/O accessors to insure that the
big endian BDs are correctly accessed by little endian
cpus too, and to insure proper sync with the H/W.
Removed the redundant RTXBD "volatile" type, as proper
synchronization around BD data accesses is provided by
the I/O accessors now.
The "sparse" tool was also used to verify the correctness
of these changes.
Cc: Scott Wood <scottwood@freescale.com>
Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
Claudiu Manoil [Mon, 30 Sep 2013 09:44:44 +0000 (12:44 +0300)]
net: tsec: Fix CamelCase issues around BD code
Fix bufPtr and the rxIdx/ txIdx occurrences to
solve the related checkpatch warnings for the
coming patches.
Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
Claudiu Manoil [Mon, 30 Sep 2013 09:44:43 +0000 (12:44 +0300)]
net: fsl_mdio: Fix warnings for __iomem pointers
Add the __iomem address space marker for the tsec pointers
to struct tsec_mii_mng memory mapped register regions.
This solves the sparse warnings for mixig normal pointers with
__iomem pointers for tsec. E.g.:
fsl_mdio.c:34:19: warning: incorrect type in argument 1 (different
address spaces)
fsl_mdio.c:34:19: expected unsigned int volatile [noderef]
<asn:2>*addr
fsl_mdio.c:34:19: got unsigned int *<noident>
[...]
tsec.c:91:35: warning: incorrect type in argument 1 (different address
spaces)
tsec.c:91:35: expected struct tsec_mii_mng *phyregs
tsec.c:91:35: got struct tsec_mii_mng [noderef] <asn:2>*phyregs_sgmii
[...]
tsec.c:680:19: warning: incorrect type in assignment (different address
spaces)
tsec.c:680:19: expected struct tsec_mii_mng *regs
tsec.c:680:19: got struct tsec_mii_mng [noderef] <asn:2>*<noident>
[...]
Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
Claudiu Manoil [Mon, 30 Sep 2013 09:44:42 +0000 (12:44 +0300)]
net: tsec: Cleanup tsec regs init and fix __iomem warns
Remove tsec_t typedef. Define macros as getters of
tsec and mdio register memory regions, for consistent
initialization of various 'regs' fields and also to
manage overly long initialization lines.
Use the __iomem address space marker to address sparse
warnings in tsec.c where IO accessors are used, like:
tsec.c:394:19: warning: incorrect type in argument 1 (different
address spaces)
tsec.c:394:19: expected unsigned int volatile [noderef]
<asn:2>*addr
tsec.c:394:19: got unsigned int *<noident>
[...]
Add the __iomem address space marker for the tsec pointers
to struct tsec_mii_mng memory mapped register regions.
This solves the sparse warnings for mixig normal pointers
with __iomem pointers for tsec.
Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
Claudiu Manoil [Mon, 30 Sep 2013 09:44:41 +0000 (12:44 +0300)]
net: tsec: Fix priv pointer in tsec_mcast_addr()
Access to privlist[1] (hardcoded referece to the 2nd tsec's
priv area) is neither correct nor does it make sense in the
current context. Each tsec dev has access to its own priv
instance only, and hence to its own set of group address
registers (GADDR) to filter multicast addresses.
This fix leads to removal of the unused (faulty) privlist[]
and related global static vars. Note that mcast() can be
called only after eth_device allocation and init, and hence
after priv area allocation, so dev->priv is correctly
initialized upon mcast() call.
Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
Patch: 278990
Claudiu Manoil [Mon, 30 Sep 2013 09:44:40 +0000 (12:44 +0300)]
net: tsec: Fix and cleanup tsec_mcast_addr()
There are several implementation issues for tsec_mcast_addr()
addressed by this patch:
* unmanaged, not portable r/w access to registers; fixed with
setbits_be32()/ clrbits_be32()
* use of volatile pointers
* unnecessary forced cast to u8 for the ether_crc() result
* removed redundant parens
* corrected some comment slips
Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
Patch: 279000
Claudiu Manoil [Mon, 30 Sep 2013 09:44:39 +0000 (12:44 +0300)]
net: Fix mcast function pointer prototype
This fixes the following compiler warnings when activating
CONFIG_MCAST_TFTP:
tsec.c: In function 'tsec_mcast_addr':
tsec.c:130:2: warning: passing argument 2 of 'ether_crc' makes pointer
from integer without a cast [enabled by default]
In file included from /work/u-boot-net/include/common.h:874:0,
from tsec.c:15:
/work/u-boot-net/include/net.h:189:5: note: expected 'const unsigned
char *' but argument is of type 'u8'
tsec.c: In function 'tsec_initialize':
tsec.c:646:13: warning: assignment from incompatible pointer type
[enabled by default]
eth.c: In function 'eth_mcast_join':
eth.c:358:2: warning: passing argument 2 of 'eth_current->mcast' makes
integer from pointer without a cast [enabled by default]
eth.c:358:2: note: expected 'u32' but argument is of type 'u8 *'
In the eth_mcast_join() implementation, eth_current->mcast()
takes a u8 pointer to the multicast mac address and not a ip
address value as implied by its prototype.
Fix parameter type mismatch for tsec_macst_addr() (tsec.c):
ether_crc() takes a u8 pointer not a u8 value.
mcast() is given a u8 pointer to the multicats mac address.
Update parameter type for the rest of mcast() instances.
Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
Patch: 278989
Alexey Brodkin [Wed, 25 Sep 2013 15:27:48 +0000 (19:27 +0400)]
net: designware: Fix alignment of buffer descriptors
It's important that buffer descriptors are aligned in accordance to GMAC
data bus width (32/64/128-bit). It's safe to align to 128-bit (16-bytes)
for every bus width type.
If buffer descriptor is improperly aligned GMAC discards lower bits of
provided address and as a result reads from improper location that
doesn't match expected fields.
Commit
ef76025a99247cdb8f927a2c9f15400678dfb599 "net: Multiple
updates/enhancements to designware.c" introduced another structure
member "link_printed" right before buffer descriptors while "padding"
member was left untouched. This together with alignment of structure
itself to 16-byte boundary forces buffer descriptoprs always to be
4-byte aligned that causes driver complete disfunction if GMAC bus width
is 64 or 128-bit.
Proposed change makes sure all buffer descriptors are 16-byte (128-bit)
aligned.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Patch: 277902
Alexey Brodkin [Wed, 25 Sep 2013 13:33:10 +0000 (17:33 +0400)]
net: designware: Respect "bus mode" register contents on SW reset
"bus mode" register contains lots of fields and some of them don't
expect to be written with 0 (zero). So since we're only interested in
resetting MAC (which is done with setting the least significant bit of
this register with "0") I believe it's better to modify only 1 bit of
the register.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Acked-by: Vipin Kumar <vipin.kumar@st.com>
Patch: 277864
Nobuhiro Iwamatsu [Tue, 24 Sep 2013 06:38:33 +0000 (15:38 +0900)]
net: sh-eth: Add support R8A7791
R8A7791 has the same sh-ether IP core as other SH/rmobile.
This patch adds support of R8A7791.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
CC: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
CC: Joe Hershberger <joe.hershberger@gmail.com>
Heiko Schocher [Sun, 22 Sep 2013 07:55:49 +0000 (09:55 +0200)]
net, phy: fix AR8031 phy_mask
AR8035 driver will be never applied because of wrong mask for
AR8031 driver. Fix this.
Signed-off-by: Heiko Schocher <hs@denx.de>
Reported-by: Pavel Nakonechny <pavel.nakonechny@skitlab.ru>
Cc: Andy Fleming <afleming@freescale.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Patch: 276944