project/bcm63xx/atf.git
7 years agofirmware-design: Fix typo in ToC header flags specification
dp-arm [Thu, 16 Mar 2017 09:31:35 +0000 (09:31 +0000)]
firmware-design: Fix typo in ToC header flags specification

Fixes ARM-software/tf-issues#463

Change-Id: I73e0c5fbd87004953df8b1fa19319ad562ecc867
Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
7 years agoMerge pull request #861 from soby-mathew/sm/aarch32_fixes
davidcunado-arm [Sat, 18 Mar 2017 12:16:27 +0000 (12:16 +0000)]
Merge pull request #861 from soby-mathew/sm/aarch32_fixes

Misc AArch32 fixes

7 years agoMerge pull request #858 from soby-mathew/sm/gic_driver_data_fix
davidcunado-arm [Fri, 17 Mar 2017 13:31:05 +0000 (13:31 +0000)]
Merge pull request #858 from soby-mathew/sm/gic_driver_data_fix

Flush the GIC driver data after init

7 years agoMerge pull request #860 from jeenu-arm/hw-asstd-coh
davidcunado-arm [Fri, 17 Mar 2017 12:34:37 +0000 (12:34 +0000)]
Merge pull request #860 from jeenu-arm/hw-asstd-coh

Patches for platforms with hardware-assisted coherency

7 years agoMerge pull request #856 from antonio-nino-diaz-arm/an/dynamic-xlat
davidcunado-arm [Thu, 16 Mar 2017 12:42:32 +0000 (12:42 +0000)]
Merge pull request #856 from antonio-nino-diaz-arm/an/dynamic-xlat

Introduce version 2 of the translation tables library

7 years agoMerge pull request #864 from vwadekar/enable-errata-tegra210
davidcunado-arm [Fri, 10 Mar 2017 13:21:09 +0000 (14:21 +0100)]
Merge pull request #864 from vwadekar/enable-errata-tegra210

Tegra210: enable errata for Cortex-A57 and Cortex-A53 CPUs

7 years agoMerge pull request #862 from vwadekar/spd-trusty-tlkd-changes
davidcunado-arm [Thu, 9 Mar 2017 09:39:00 +0000 (10:39 +0100)]
Merge pull request #862 from vwadekar/spd-trusty-tlkd-changes

SPD changes for Trusty and TLKD

7 years agoARM platforms: Enable xlat tables lib v2
Antonio Nino Diaz [Thu, 23 Feb 2017 17:22:58 +0000 (17:22 +0000)]
ARM platforms: Enable xlat tables lib v2

Modify ARM common makefile to use version 2 of the translation tables
library and include the new header in C files.

Simplify header dependencies related to this library to simplify the
change.

The following table contains information about the size increase in
bytes for BL1 after applying this patch. The code has been compiled for
different configurations of FVP in AArch64 mode with compiler GCC 4.9.3
20150413. The sizes have been calculated with the output of `nm` by
adding the size of all regions and comparing the total size before and
after the change. They are sumarized in the table below:

                               text   bss   data  total
        Release                +660   -20    +88   +728
        Debug                  +740   -20   +242   +962
        Debug (LOG_LEVEL=50)  +1120   -20   +317  +1417

Change-Id: I539e307f158ab71e3a8b771640001fc1bf431b29
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
7 years agoApply workaround for errata 813419 of Cortex-A57
Antonio Nino Diaz [Fri, 24 Feb 2017 11:39:22 +0000 (11:39 +0000)]
Apply workaround for errata 813419 of Cortex-A57

TLBI instructions for EL3 won't have the desired effect under specific
circumstances in Cortex-A57 r0p0. The workaround is to execute DSB and
TLBI twice each time.

Even though this errata is only needed in r0p0, the current errata
framework is not prepared to apply run-time workarounds. The current one
is always applied if compiled in, regardless of the CPU or its revision.

This errata has been enabled for Juno.

The `DSB` instruction used when initializing the translation tables has
been changed to `DSB ISH` as an optimization and to be consistent with
the barriers used for the workaround.

Change-Id: Ifc1d70b79cb5e0d87e90d88d376a59385667d338
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
7 years agoAdd dynamic region support to xlat tables lib v2
Antonio Nino Diaz [Mon, 27 Feb 2017 17:23:54 +0000 (17:23 +0000)]
Add dynamic region support to xlat tables lib v2

Added APIs to add and remove regions to the translation tables
dynamically while the MMU is enabled. Only static regions are allowed
to overlap other static ones (for backwards compatibility).

A new private attribute (MT_DYNAMIC / MT_STATIC) has been added to
flag each region as such.

The dynamic mapping functionality can be enabled or disabled when
compiling by setting the build option PLAT_XLAT_TABLES_DYNAMIC to 1
or 0. This can be done per-image.

TLB maintenance code during dynamic table mapping and unmapping has
also been added.

Fixes ARM-software/tf-issues#310

Change-Id: I19e8992005c4292297a382824394490c5387aa3b
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
7 years agoImprove debug output of the translation tables
Antonio Nino Diaz [Mon, 13 Feb 2017 11:35:49 +0000 (11:35 +0000)]
Improve debug output of the translation tables

The printed output has been improved in two ways:

- Whenever multiple invalid descriptors are found, only the first one
  is printed, and a line is added to inform about how many descriptors
  have been omitted.

- At the beginning of each line there is an indication of the table
  level the entry belongs to. Example of the new output:
  `[LV3] VA:0x1000 PA:0x1000 size:0x1000 MEM-RO-S-EXEC`

Change-Id: Ib6f1cd8dbd449452f09258f4108241eb11f8d445
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
7 years agoSimplify translation tables headers dependencies
Antonio Nino Diaz [Mon, 20 Feb 2017 14:22:22 +0000 (14:22 +0000)]
Simplify translation tables headers dependencies

The files affected by this patch don't really depend on `xlat_tables.h`.
By changing the included file it becomes easier to switch between the
two versions of the translation tables library.

Change-Id: Idae9171c490e0865cb55883b19eaf942457c4ccc
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
7 years agoAdd version 2 of xlat tables library
Antonio Nino Diaz [Wed, 8 Mar 2017 14:40:23 +0000 (14:40 +0000)]
Add version 2 of xlat tables library

The folder lib/xlat_tables_v2 has been created to store a new version
of the translation tables library for further modifications in patches
to follow. At the moment it only contains a basic implementation that
supports static regions.

This library allows different translation tables to be modified by
using different 'contexts'. For now, the implementation defaults to
the translation tables used by the current image, but it is possible
to modify other tables than the ones in use.

Added a new API to print debug information for the current state of
the translation tables, rather than printing the information while
the tables are being created. This allows subsequent debug printing
of the xlat tables after they have been changed, which will be useful
when dynamic regions are implemented in a patch to follow.

The common definitions stored in `xlat_tables.h` header have been moved
to a new file common to both versions, `xlat_tables_defs.h`.

All headers related to the translation tables library have been moved to
a the subfolder `xlat_tables`.

Change-Id: Ia55962c33e0b781831d43a548e505206dffc5ea9
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
7 years agoTegra210: enable errata for Cortex-A57 and Cortex-A53 CPUs
Varun Wadekar [Mon, 6 Mar 2017 17:15:15 +0000 (09:15 -0800)]
Tegra210: enable errata for Cortex-A57 and Cortex-A53 CPUs

This patch enables the following erratas for the Tegra210 SoC:

* Cortex-A57
=============
- A57_DISABLE_NON_TEMPORAL_HINT
- ERRATA_A57_826974
- ERRATA_A57_826977
- ERRATA_A57_828024
- ERRATA_A57_829520
- ERRATA_A57_833471

* Cortex-A53
=============
- A53_DISABLE_NON_TEMPORAL_HINT
- ERRATA_A53_826319
- ERRATA_A53_836870

Tegra210 uses Cortex-A57 revision: r1p1 and Cortex-A53 revision: r0p2.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
7 years agoMerge pull request #852 from dp-arm/dp/fiptool-embed-image
davidcunado-arm [Tue, 7 Mar 2017 13:44:44 +0000 (14:44 +0100)]
Merge pull request #852 from dp-arm/dp/fiptool-embed-image

fiptool: Embed a pointer to an image within the image descriptor

7 years agospd: trusty: support for AARCH64 mode
Varun Wadekar [Thu, 23 Feb 2017 18:34:06 +0000 (10:34 -0800)]
spd: trusty: support for AARCH64 mode

This patch removes support for running Trusty in the AARCH32 mode as
all platforms use it in only AARCH64 mode.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
7 years agospd: trusty: save context starting from the stack end
Varun Wadekar [Fri, 17 Feb 2017 02:14:37 +0000 (18:14 -0800)]
spd: trusty: save context starting from the stack end

This patch uses the stack end to start saving the CPU context
during world switch. The previous logic, used the stack start
to save the context, thus overwriting the other members of the
context.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
7 years agospd: trusty: add SET_ROT_PARAMS handling
Varun Wadekar [Thu, 29 Sep 2016 23:08:16 +0000 (16:08 -0700)]
spd: trusty: add SET_ROT_PARAMS handling

If Trusty is not running on the device, then Verified Boot is
not supported and the NS layer will fail gracefully later during
boot. This patch just returns success for the case when Trusty is
not running on the device and the bootloader issues SET_ROT_PARAMS
call during boot, so that we can at least boot non-Android images.

Change-Id: I40fc249983df80fb8cc5be5e4ce94c99d5b5f17d
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
7 years agotlkd: execute standard SMC calls on the boot CPU
Varun Wadekar [Wed, 8 Jun 2016 04:21:59 +0000 (21:21 -0700)]
tlkd: execute standard SMC calls on the boot CPU

This patch checks if standard SMC calls, meant for TLK, are issued
only on the boot CPU. TLK is UP Trusted OS stack and so we need this
check to avoid the NS world calling into TLK from any other CPU.

The previous check tied TLK to CPU0, but the boot CPU can be other
than CPU0 in some scenarios.

Change-Id: I75eaafa32471ce19e9920433c2f97b6b5fc02d86
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
7 years agospd: trusty: pass boot params to the Trusted OS
Wayne Lin [Tue, 24 May 2016 22:28:42 +0000 (15:28 -0700)]
spd: trusty: pass boot params to the Trusted OS

This patch passes the boot parameters, provided by the previous
bootloader, to the Trusted OS via X0, X1 and X2.

Original change by: Wayne Lin <wlin@nvidia.com>

Change-Id: I2039612a8a8226158babfd505ce8c31c4212319c
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
7 years agospd: trusty: only process one function ID at a time
Anthony Zhou [Wed, 20 Apr 2016 02:16:48 +0000 (10:16 +0800)]
spd: trusty: only process one function ID at a time

In multi-guest trusty environment, all guest's SMCs will be
forwarded to Trusty. This change only allows 1 guest's SMC
to be forwarded at a time and returns 'busy' status to all
other requests.

Change-Id: I2144467d11e3680e28ec816adeec2766bca114d4
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
7 years agospd: trusty: pass VMID via X7
Anthony Zhou [Fri, 30 Oct 2015 22:03:41 +0000 (06:03 +0800)]
spd: trusty: pass VMID via X7

According to the ARM DEN0028A spec, hypervisor ID(VMID) should be stored
in x7 (or w7). This patch gets this value from the context and passes it
to Trusty. In order to do so, introduce new macros to pass five to eight
parameters to the Trusted OS.

Change-Id: I101cf45d0712e1e880466b2274f9a48af755c9fa
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
7 years agoMerge pull request #863 from vwadekar/tegra-changes-from-downstream-v4
davidcunado-arm [Sat, 4 Mar 2017 00:56:46 +0000 (00:56 +0000)]
Merge pull request #863 from vwadekar/tegra-changes-from-downstream-v4

Tegra changes from downstream v4

7 years agoMerge pull request #854 from rockchip-linux/pm_plat
davidcunado-arm [Fri, 3 Mar 2017 23:29:01 +0000 (23:29 +0000)]
Merge pull request #854 from rockchip-linux/pm_plat

rockchip: plat_pm.c: Change callbacks implement for our SOCs.

7 years agoTegra: enable SEPARATE_CODE_AND_RODATA build flag
Varun Wadekar [Tue, 28 Feb 2017 16:23:59 +0000 (08:23 -0800)]
Tegra: enable SEPARATE_CODE_AND_RODATA build flag

This patch enables the SEPARATE_CODE_AND_RODATA build flag for all
Tegra platforms, to allow setting proper MMU attributes for the RO
data and the code.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
7 years agorockchip: Change the callback implement of power domain for rk3368
tony.xie [Fri, 3 Mar 2017 08:22:12 +0000 (16:22 +0800)]
rockchip: Change the callback implement of power domain for rk3368

Change-Id: I6d39b4cac9b34b1f841e9bbddaf9c49785ba0c5e
Signed-off-by: tony.xie <tony.xie@rock-chips.com>
7 years agoTegra210: assert if afflvl0/1 have incorrect state-ids
Harvey Hsieh [Wed, 28 Dec 2016 13:53:18 +0000 (21:53 +0800)]
Tegra210: assert if afflvl0/1 have incorrect state-ids

The linux kernel v3.10 does not use System Suspend function ID, whereas
v4.4 uses it. This means affinity levels 0/1 will have different state id
values during System Suspend entry. This patch updates the assert criteria
to check both the state id values.

Change-Id: I07fcaf99501cc9622e40d0a2c1eb4a4a160be10a
Signed-off-by: Harvey Hsieh <hhsieh@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
7 years agoTegra: SiP: 64-bit address for Video Memory base
Harvey Hsieh [Tue, 11 Oct 2016 10:59:52 +0000 (18:59 +0800)]
Tegra: SiP: 64-bit address for Video Memory base

This patch allows the NS world to pass 64-bit base address for
the Video Memory carveout region.

Change-Id: I7e47cc1f5425bd39c6763755b801517013e1e0cd
Signed-off-by: Harvey Hsieh <hhsieh@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
7 years agoTegra: increase ADDR_SPACE_SIZE to 35 bits
Steven Kao [Thu, 24 Nov 2016 11:24:37 +0000 (19:24 +0800)]
Tegra: increase ADDR_SPACE_SIZE to 35 bits

This patch increases the ADDR_SPACE_SIZE macro (virtual address)
to 35 bits, to support max memory of 32G, for all Tegra platforms.

Change-Id: I8e6861601d3a667d7428988c7596b0adebfa0548
Signed-off-by: Steven kao <skao@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
7 years agoTegra: init the console only if the platform supports it
Damon Duan [Mon, 7 Nov 2016 11:37:50 +0000 (19:37 +0800)]
Tegra: init the console only if the platform supports it

Some platforms might want to keep the uart console disabled
during boot. This patch checks if the platform supports a
console, before calling console_init().

Change-Id: Icc9c59cb979d91fd0a72e4732403b3284bdd2dfc
Signed-off-by: Damon Duan <danield@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
7 years agoTegra210: new TZDRAM base address
Varun Wadekar [Thu, 1 Sep 2016 21:59:32 +0000 (14:59 -0700)]
Tegra210: new TZDRAM base address

This patch modifies the TZDRAM base address to the new aperture
allocated by the bootloader.

Change-Id: Id158d15b1ec9aa681136d258e90fbba930aebf92
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
7 years agoTegra210: set core power state during cluster power down
Varun Wadekar [Thu, 1 Sep 2016 21:56:17 +0000 (14:56 -0700)]
Tegra210: set core power state during cluster power down

This patch sets the core power state during cluster power down,
so that the 'get_target_pwr_state' handler can calculate the
proper states for all the affinity levels.

Change-Id: If4adb001011208916427ee1623c6c923bed99985
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
7 years agoTegra: calculate proper power state for affinity levels
Varun Wadekar [Thu, 1 Sep 2016 21:51:59 +0000 (14:51 -0700)]
Tegra: calculate proper power state for affinity levels

This patch fixes the 'tegra_soc_get_target_pwr_state' handler used to
calculate the proper state for each of the affinity levels.

Change-Id: Id16bd15b96f0fc633ffeac2d7a390592fbd0454b
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
7 years agoTegra: fix logic to calculate GICD_ISPENDR register address
Varun Wadekar [Tue, 23 Aug 2016 21:01:19 +0000 (14:01 -0700)]
Tegra: fix logic to calculate GICD_ISPENDR register address

This patch uses GICD_BASE to calculate the GICD_ISPENDR regsiter address
in the platform's 'plat_crash_print_regs' routine.

Reported by: Seth Eatinger <seatinger@nvidia.com>

Change-Id: Ic7be29abc781f475ad25b59582ae60a0a2497377
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
7 years agoTegra: uninit and re-init console across System Suspend
Varun Wadekar [Tue, 2 Aug 2016 05:16:21 +0000 (22:16 -0700)]
Tegra: uninit and re-init console across System Suspend

This patch removes the console_init() from runtime_setup() as we already
initialize it earlier and disables/enables it across "System Suspend".

Change-Id: I992d3ca56ff4797faf83e8d7fa52c0ef3e1c3367
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
7 years agoTegra: support for silicon/simulation platforms
Varun Wadekar [Wed, 20 Jul 2016 17:28:51 +0000 (10:28 -0700)]
Tegra: support for silicon/simulation platforms

This patch adds support to identify the underlying platform
on which we are running. The currently supported platforms
are actual silicon and simulation platforms.

Change-Id: Iadf96e79ec663b3dbd1a18e9bb95ffcdb82fc8af
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
7 years agoMerge pull request #859 from Summer-ARM/sq/update-doc
danh-arm [Thu, 2 Mar 2017 17:03:12 +0000 (17:03 +0000)]
Merge pull request #859 from Summer-ARM/sq/update-doc

Update LOAD_IMAGE_V2 user guide documentation

7 years agoAArch32: Enable override of plat_set_my_stack/plat_get_my_stack
Soby Mathew [Tue, 14 Feb 2017 10:21:55 +0000 (10:21 +0000)]
AArch32: Enable override of plat_set_my_stack/plat_get_my_stack

This patch makes the default MP definitions of plat_get_my_stack()
and plat_set_my_stack() as weak so that they can be overridden by
the AArch32 Secure Payload if it requires.

Change-Id: I3b6ddff5750443a776505e3023ff2934227592b6
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
7 years agoAArch32: Fix conditional inclusion of bakery_locks
Soby Mathew [Tue, 28 Feb 2017 22:58:29 +0000 (22:58 +0000)]
AArch32: Fix conditional inclusion of bakery_locks

Due to incorrect conditional compilation checks, bakery locks were
excluded from the CCN driver and the power controller driver for FVP
when BL32 was built as the EL3 Runtime Software in AArch32 mode.
This patch corrects the same.

Change-Id: Ib1f163d9167a5c38e4d622232c4835cad9c235aa
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
7 years agoAArch32: Fix normal memory bakery compilation
Soby Mathew [Tue, 14 Feb 2017 10:16:18 +0000 (10:16 +0000)]
AArch32: Fix normal memory bakery compilation

This patch fixes a compilation issue with bakery locks when
PSCI library is compiled with USE_COHERENT_MEM = 0 build option.

Change-Id: Ic7f6cf9f2bb37f8a946eafbee9cbc3bf0dc7e900
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
7 years agoMerge pull request #853 from vwadekar/tegra-changes-from-downstream-v3
davidcunado-arm [Thu, 2 Mar 2017 15:27:33 +0000 (15:27 +0000)]
Merge pull request #853 from vwadekar/tegra-changes-from-downstream-v3

Tegra changes from downstream v3

7 years agoPSCI: Optimize call paths if all participants are cache-coherent
Jeenu Viswambharan [Thu, 5 Jan 2017 11:01:02 +0000 (11:01 +0000)]
PSCI: Optimize call paths if all participants are cache-coherent

The current PSCI implementation can apply certain optimizations upon the
assumption that all PSCI participants are cache-coherent.

  - Skip performing cache maintenance during power-up.

  - Skip performing cache maintenance during power-down:

    At present, on the power-down path, CPU driver disables caches and
    MMU, and performs cache maintenance in preparation for powering down
    the CPU. This means that PSCI must perform additional cache
    maintenance on the extant stack for correct functioning.

    If all participating CPUs are cache-coherent, CPU driver would
    neither disable MMU nor perform cache maintenance. The CPU being
    powered down, therefore, remain cache-coherent throughout all PSCI
    call paths. This in turn means that PSCI cache maintenance
    operations are not required during power down.

  - Choose spin locks instead of bakery locks:

    The current PSCI implementation must synchronize both cache-coherent
    and non-cache-coherent participants. Mutual exclusion primitives are
    not guaranteed to function on non-coherent memory. For this reason,
    the current PSCI implementation had to resort to bakery locks.

    If all participants are cache-coherent, the implementation can
    enable MMU and data caches early, and substitute bakery locks for
    spin locks. Spin locks make use of architectural mutual exclusion
    primitives, and are lighter and faster.

The optimizations are applied when HW_ASSISTED_COHERENCY build option is
enabled, as it's expected that all PSCI participants are cache-coherent
in those systems.

Change-Id: Iac51c3ed318ea7e2120f6b6a46fd2db2eae46ede
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
7 years agoPSCI: Introduce cache and barrier wrappers
Jeenu Viswambharan [Fri, 6 Jan 2017 14:58:11 +0000 (14:58 +0000)]
PSCI: Introduce cache and barrier wrappers

The PSCI implementation performs cache maintenance operations on its
data structures to ensure their visibility to both cache-coherent and
non-cache-coherent participants. These cache maintenance operations
can be skipped if all PSCI participants are cache-coherent. When
HW_ASSISTED_COHERENCY build option is enabled, we assume PSCI
participants are cache-coherent.

For usage abstraction, this patch introduces wrappers for PSCI cache
maintenance and barrier operations used for state coordination: they are
effectively NOPs when HW_ASSISTED_COHERENCY is enabled, but are
applied otherwise.

Also refactor local state usage and associated cache operations to make
it clearer.

Change-Id: I77f17a90cba41085b7188c1345fe5731c99fad87
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
7 years agoDisallow using coherent memory with hardware-assisted coherency
Jeenu Viswambharan [Fri, 6 Jan 2017 16:14:42 +0000 (16:14 +0000)]
Disallow using coherent memory with hardware-assisted coherency

ARM Trusted Firmware keeps certain data structures in a memory region
with non-cacheable attributes (termed as "coherent memory") to keep data
coherent with observers that are cache-coherent, and those not. These
data structures pertain to power management and mutual exclusion. Using
coherent memory also costs at least an additional page to map memory
with special memory attributes.

On systems with hardware-assisted coherency, all CPUs that participate
in power management and mutual exclusion are cache-coherent, obviating
the need for special memory attributes for such data structures.
Instead, they can be placed in normal memory, along with rest of data.

On systems with hardware-assisted coherency, where build option
HW_ASSISTED_COHERENCY will be set, also having USE_COHERENT_MEMORY
enabled only wastes a page of memory without any
benefit. Therefore, with HW_ASSISTED_COHERENCY set to 1, require that
USE_COHERENT_MEMORY is explicitly set to 0.

Change-Id: I5101657ae6b1a46278069f23e2d88ee5cbd98efa
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
7 years agoEnable data caches early with hardware-assisted coherency
Jeenu Viswambharan [Thu, 5 Jan 2017 10:37:21 +0000 (10:37 +0000)]
Enable data caches early with hardware-assisted coherency

At present, warm-booted CPUs keep their caches disabled when enabling
MMU, and remains so until they enter coherency later.

On systems with hardware-assisted coherency, for which
HW_ASSISTED_COHERENCY build flag would be enabled, warm-booted CPUs can
have both caches and MMU enabled at once.

Change-Id: Icb0adb026e01aecf34beadf49c88faa9dd368327
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
7 years agobuild: Define build option for hardware-assisted coherency
Jeenu Viswambharan [Wed, 4 Jan 2017 13:51:42 +0000 (13:51 +0000)]
build: Define build option for hardware-assisted coherency

The boolean build option HW_ASSISTED_COHERENCY is introduced to enable
various optimizations in ARM Trusted Software, when built for such
systems. It's set to 0 by default.

Change-Id: I638390da6e1718fe024dcf5b402e07084f1eb014
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
7 years agoUpdate LOAD_IMAGE_V2 user guide documentation
Summer Qin [Wed, 22 Feb 2017 14:04:15 +0000 (14:04 +0000)]
Update LOAD_IMAGE_V2 user guide documentation

Now the TRUSTED_BOARD_BOOT is supported for AArch64 when LOAD_IMAGE_V2
is enabled. This patch updates the user-guide.md documentation for the
same.

Change-Id: I97de07435c81258c2a5f41a30a69736863a10bd1
Signed-off-by: Summer Qin <summer.qin@arm.com>
7 years agoFlush the GIC driver data after init
Soby Mathew [Tue, 14 Feb 2017 10:11:52 +0000 (10:11 +0000)]
Flush the GIC driver data after init

The GIC driver data is initialized by the primary CPU with caches
enabled. When the secondary CPU boots up, it initializes the
GICC/GICR interface with the caches disabled and there is a chance that
the driver data is not yet written back to the memory. This patch fixes
this problem by flushing the driver data after they have been
initialized.

Change-Id: Ie9477029683846209593ff005d2bac559bb8f5e6
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
7 years agorockchip: plat_pm.c: Change callbacks implement for our SOCs.
tony.xie [Wed, 1 Mar 2017 03:05:17 +0000 (11:05 +0800)]
rockchip: plat_pm.c: Change callbacks implement for our SOCs.

Remove struct rockchip_pm_ops_cb and instead of using weak functions
implement; in this way we want the codes look clear and simple;

Change-Id: Ib9e8a5e932fdfc2b3e6a1ec502c40dfe720ac400
Signed-off-by: tony.xie <tony.xie@rock-chips.com>
7 years agoTegra: per-soc `get_target_pwr_state` handler
Varun Wadekar [Tue, 7 Jun 2016 19:00:06 +0000 (12:00 -0700)]
Tegra: per-soc `get_target_pwr_state` handler

This patch implements a per-soc handler to calculate the target
power state for the cluster/system. A weak implementation of the
handler is provided for platforms to use by default.

For SoCs with multiple CPU clusters, this handler would provide
the individual cluster/system state, allowing the PSCI service to
flush caches during cluster/system power down.

Change-Id: I568cdb42204f9841a8430bd9105bd694f71cf91d
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
7 years agoTegra: relocate BL32 image to TZDRAM memory
Varun Wadekar [Mon, 23 May 2016 22:56:14 +0000 (15:56 -0700)]
Tegra: relocate BL32 image to TZDRAM memory

This patch adds support to relocate the BL32 image from the NS
memory to TZDRAM during cold boot. The NS memory buffer is
cleared out after the process completes.

Change-Id: I1a033ffe73b8c309449f874d5187708d0a8846d2
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
7 years agostdlib: add memcpy16() to string.h
Varun Wadekar [Mon, 21 Mar 2016 17:22:12 +0000 (10:22 -0700)]
stdlib: add memcpy16() to string.h

This patch exports memcpy16() for platforms, as an option to
memcpy().

Change-Id: I5d4e1cfb4608ec3674224b1447fdd740de549b1f
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
7 years agoTegra: get BL31 arguments from previous bootloader
Varun Wadekar [Mon, 23 May 2016 18:41:07 +0000 (11:41 -0700)]
Tegra: get BL31 arguments from previous bootloader

This patch implements handlers which platforms can override to
get the BL31 arguments passed by the previous bootloader.

Change-Id: I6b9628a984644ce1b5de5aa6d7cd890e57241d89
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
7 years agoTegra: return BL32 entry point info if it is valid
Varun Wadekar [Mon, 6 Jun 2016 17:46:28 +0000 (10:46 -0700)]
Tegra: return BL32 entry point info if it is valid

This patch returns pointer to the BL32 entrypoint info only if
it is valid.

Change-Id: I71ce3c4626681753c94f3a7bbaa50c26c74874cb
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
7 years agoTegra: configure TZDRAM fence during early setup
Varun Wadekar [Sun, 5 Jun 2016 05:08:50 +0000 (22:08 -0700)]
Tegra: configure TZDRAM fence during early setup

This patch configures the TZDRAM fence during early platform
setup to allow the memory controller to enable DRAM encryption
before the TZDRAM actually gets used.

Change-Id: I0169ef9dda75699527b4e30c9e617a9036ba1d76
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
7 years agoTegra: restore TZRAM settings on "System Resume"
Varun Wadekar [Thu, 2 Jun 2016 02:34:37 +0000 (19:34 -0700)]
Tegra: restore TZRAM settings on "System Resume"

This patch restores the TZRAM fence and the access permissions
on exiting the "System Suspend" state.

Change-Id: Ie313fca5a861c73f80df9639b01115780fb6e217
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
7 years agoTegra: enable ECC/Parity protection for Cortex-A57 CPUs
Varun Wadekar [Thu, 12 May 2016 20:43:33 +0000 (13:43 -0700)]
Tegra: enable ECC/Parity protection for Cortex-A57 CPUs

This patch enables L2 ECC and Parity Protection for ARM Cortex-A57 CPUs
for Tegra SoCs.

Change-Id: I038fcd529991d0201a4951ce2730ab71b1c980f9
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
7 years agoTegra: GIC: differentiate between FIQs targeted towards EL3/S-EL1
Varun Wadekar [Fri, 20 May 2016 23:21:22 +0000 (16:21 -0700)]
Tegra: GIC: differentiate between FIQs targeted towards EL3/S-EL1

This patch modifies the secure IRQ registration process to allow platforms
to specify the target CPUs as well as the owner of the IRQ. IRQs "owned"
by the EL3 would return INTR_TYPE_EL3 whereas those owned by the Trusted
OS would return INTR_TYPE_S_EL1 as a result.

Change-Id: I528f7c8220d0ae0c0f354e78d69e188abb666ef6
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
7 years agoTegra: implement FIQ interrupt handler
Varun Wadekar [Tue, 29 Dec 2015 00:36:42 +0000 (16:36 -0800)]
Tegra: implement FIQ interrupt handler

This patch adds a handler for FIQ interrupts triggered when
the CPU is in the NS world. The handler stores the NS world's
context along with ELR_EL3/SPSR_EL3.

The NS world driver issues an SMC initially to register it's
handler. The monitor firmware stores this handler address and
jumps to it when the FIQ interrupt fires. Upon entry into the
NS world the driver then issues another SMC to get the CPU
context when the FIQ fired. This allows the NS world driver to
determine the CPU state and call stack when the interrupt
fired. Generally, systems register watchdog interrupts as FIQs
which are then used to get the CPU state during hangs/crashes.

Change-Id: I733af61a08d1318c75acedbe9569a758744edd0c
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
7 years agoTegra: GIC: enable FIQ interrupt handling
Varun Wadekar [Mon, 28 Dec 2015 22:55:41 +0000 (14:55 -0800)]
Tegra: GIC: enable FIQ interrupt handling

Tegra chips support multiple FIQ interrupt sources. These interrupts
are enabled in the GICD/GICC interfaces by the tegra_gic driver. A
new FIQ handler would be added in a subsequent change which can be
registered by the platform code.

This patch adds the GIC programming as part of the tegra_gic_setup()
which now takes an array of all the FIQ interrupts to be enabled for
the platform. The Tegra132 and Tegra210 platforms right now do not
register for any FIQ interrupts themselves, but will definitely use
this support in the future.

Change-Id: I0ea164be901cd6681167028fea0567399f18d4b8
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
7 years agocpus: denver: remove barrier from denver_enable_dco()
Varun Wadekar [Fri, 6 May 2016 23:35:30 +0000 (16:35 -0700)]
cpus: denver: remove barrier from denver_enable_dco()

This patch removes unnecessary `isb` from the enable DCO sequence as
there is no need to synchronize this operation.

Change-Id: I0191e684bbc7fdba635c3afbc4e4ecd793b6f06f
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
7 years agoTegra: implement common handler `plat_get_target_pwr_state()`
Varun Wadekar [Thu, 5 May 2016 21:13:30 +0000 (14:13 -0700)]
Tegra: implement common handler `plat_get_target_pwr_state()`

This patch adds a platform handler to calculate the proper target power
level at the specified affinity level.

Tegra platforms assign a local state value in order of decreasing depth
of the power state i.e. for two power states X & Y, if X < Y then X
represents a shallower power state than Y. As a result, the coordinated
target local power state for a power domain will be the maximum of the
requested local power state values.

Change-Id: I67360684b7f5b783fcfdd605b96da5375fa05417
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
7 years agoTegra: include platform_def.h to access UART macros
Varun Wadekar [Tue, 26 Apr 2016 18:38:38 +0000 (11:38 -0700)]
Tegra: include platform_def.h to access UART macros

This patch includes platform_def.h required to access UART macros -
"TEGRA_BOOT_UART_CLK_IN_HZ" and "TEGRA_CONSOLE_BAUDRATE" from
tegra_helpers.S.

Change-Id: Ieb63968a48dc299d03e81ddeb1ccc871cf3397a1
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
7 years agoTegra: allow SiP smc calls from Secure World
Wayne Lin [Thu, 31 Mar 2016 20:49:09 +0000 (13:49 -0700)]
Tegra: allow SiP smc calls from Secure World

This patch removes the restriction of allowing SiP calls only from the
non-secure world. The secure world can issue SiP calls as a result of
this patch now.

Change-Id: Idd64e893ae8e114bba0196872d3ec544cac150bf
Signed-off-by: Wayne Lin <wlin@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
7 years agoTegra: handler for per-soc early setup
Varun Wadekar [Mon, 28 Mar 2016 22:56:47 +0000 (15:56 -0700)]
Tegra: handler for per-soc early setup

This patch adds a weak handler for early platform setup which
can be overriden by the soc-specific handlers to perform any
early setup tasks.

Change-Id: I1a7a98d59b2332a3030c6dca5a9b7be977177326
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
7 years agoTegra: relocate code to BL31_BASE during cold boot
Varun Wadekar [Thu, 24 Mar 2016 22:34:24 +0000 (15:34 -0700)]
Tegra: relocate code to BL31_BASE during cold boot

This patch adds support to relocate BL3-1 code to BL31_BASE in case
we cold boot to a different address. This is particularly useful to
maintain compatibility with legacy BL2 code.

This patch also checks to see if the image base address matches either
the TZDRAM or TZSRAM base.

Change-Id: I72c96d7f89076701a6ac2537d4c06565c54dab9c
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
7 years agoMerge pull request #851 from jeenu-arm/assert-fix
danh-arm [Tue, 28 Feb 2017 12:07:55 +0000 (12:07 +0000)]
Merge pull request #851 from jeenu-arm/assert-fix

Remove redundant assert

7 years agoMerge pull request #848 from douglas-raillard-arm/dr/improve_errata_doc
danh-arm [Tue, 28 Feb 2017 12:07:32 +0000 (12:07 +0000)]
Merge pull request #848 from douglas-raillard-arm/dr/improve_errata_doc

Clarify errata ERRATA_A53_836870 documentation

7 years agoMerge pull request #847 from douglas-raillard-arm/dr/fix_abort_smc
danh-arm [Tue, 28 Feb 2017 12:06:54 +0000 (12:06 +0000)]
Merge pull request #847 from douglas-raillard-arm/dr/fix_abort_smc

Fix TSPD implementation of STD SMC ABORT

7 years agoMerge pull request #837 from douglas-raillard-arm/dr/fix_tools_cflags
danh-arm [Tue, 28 Feb 2017 11:58:12 +0000 (11:58 +0000)]
Merge pull request #837 from douglas-raillard-arm/dr/fix_tools_cflags

build: Use separate CFLAGS for tools

7 years agoTegra: Disable A57/A53 cache non-temporal hints
Varun Wadekar [Mon, 21 Mar 2016 18:18:40 +0000 (11:18 -0700)]
Tegra: Disable A57/A53 cache non-temporal hints

This change disables the cache non-temporal hints for A57 and
A53 CPUs on Tegra.

Change-Id: I279d95aec5afbc3ca3cc4b34aa16de3f2c83a4fc
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
7 years agoMerge pull request #835 from rockchip-linux/rk3399-atf-cleanup-20170210
davidcunado-arm [Mon, 27 Feb 2017 15:25:45 +0000 (15:25 +0000)]
Merge pull request #835 from rockchip-linux/rk3399-atf-cleanup-20170210

RK3399 ARM TF clean up 20170210

7 years agofiptool: Embed a pointer to an image within the image descriptor
dp-arm [Tue, 14 Feb 2017 15:22:13 +0000 (15:22 +0000)]
fiptool: Embed a pointer to an image within the image descriptor

Currently, fiptool uses two linked lists.  One to chain together all
the images and one for all the image descriptors.  Initially this was
done because not all images had a corresponding image descriptor.
This was the case for unknown images which existed in the FIP but
there was no descriptor in the builtin table for them.  When support
for the --blob option came in, we started building descriptors for the
unknown images on the fly.  As a result every image now has a
corresponding image descriptor and therefore it is no longer necessary
to keep track of them separately.

To simplify the design, maintain only a single linked list of image
descriptors.  An image descriptor contains a pointer to the
corresponding image.  If the pointer is NULL, then the descriptor is
skipped in all the operations.  This approach simplifies the traversal
code and avoids redundant lookups.

The linked list of image descriptors is populated based on the
`toc_entries` array.  This means that the order of the images in the
FIP file remains the same across add/remove or create/update
operations.  This is true for all standard images (those specified in
`toc_entries`) but not for those specified via the --blob option.

Change-Id: Ic29a263c86c8f1efdad322b430368c7623782e2d
Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
7 years agoMerge pull request #849 from vwadekar/tegra-changes-from-downstream-v2
davidcunado-arm [Mon, 27 Feb 2017 14:41:24 +0000 (14:41 +0000)]
Merge pull request #849 from vwadekar/tegra-changes-from-downstream-v2

Tegra changes from downstream v2

7 years agorockchip: rk3399: enable secure accessing for SRAM
Xing Zheng [Tue, 14 Feb 2017 10:03:20 +0000 (18:03 +0800)]
rockchip: rk3399: enable secure accessing for SRAM

Sorry to miss the security configuration for SRAM, if we don't support
it, somebody may modify the comment of SRAM in the non-secure space.
Let's fix this issue.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
7 years agorockchip: rk3399: Use tFC value instead of tRFC value
Derek Basehore [Fri, 10 Feb 2017 06:08:48 +0000 (22:08 -0800)]
rockchip: rk3399: Use tFC value instead of tRFC value

This fixes code that set a tFC value in a register using the tRFC
value instead.

Signed-off-by: Derek Basehore <dbasehore@chromium.org>
7 years agorockchip: rk3399: Fix CAS latency setting
Derek Basehore [Fri, 10 Feb 2017 06:02:42 +0000 (22:02 -0800)]
rockchip: rk3399: Fix CAS latency setting

The F1 CAS latency setting was not bit shifted, which resulted in
setting the DRAM additive latency value instead.

Signed-off-by: Derek Basehore <dbasehore@chromium.org>
7 years agorockchip: rk3399: disable training modules after DDR DFS
Xing Zheng [Thu, 9 Feb 2017 06:51:38 +0000 (14:51 +0800)]
rockchip: rk3399: disable training modules after DDR DFS

On resume, we use the DFS hardware to switch frequency index,
followed by a full training sequence on that index. Leaving
the DFS training modules enabled causes issues with the full
training done at resume. We also only needs these enabled
during a call to ddr_set_rate during runtime, so there's no
issue disabling them at the end of ddr_set_rate.

Signed-off-by: Derek Basehore <dbasehore@chromium.org>
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
7 years agorockchip: rk3399: Move DQS drive strength setting to M0
Derek Basehore [Thu, 2 Feb 2017 02:09:13 +0000 (18:09 -0800)]
rockchip: rk3399: Move DQS drive strength setting to M0

This moves the setting of the DQS drive strength to the M0 to minimize
the impact on DDR transactions. We need to have the DQS drive strength
changed for data training, which is triggered by the M0, but it also
needs to be changed back when data training is finished.

Signed-off-by: Derek Basehore <dbasehore@chromium.org>
7 years agorockchip: rk3399: Remove dram dfs optimization
Derek Basehore [Wed, 1 Feb 2017 00:37:01 +0000 (16:37 -0800)]
rockchip: rk3399: Remove dram dfs optimization

This removes an optimization to not recalculate parameters if the
frequency index being switched to hold the next frequency. This is
because some registers do not have a copy per frequency index, so this
optimization might be causing problems.

Signed-off-by: Derek Basehore <dbasehore@chromium.org>
7 years agorockchip: rk3399: Save and restore RX_CAL_DQS values
Derek Basehore [Tue, 31 Jan 2017 08:20:19 +0000 (00:20 -0800)]
rockchip: rk3399: Save and restore RX_CAL_DQS values

We were getting far off values on resume for the RX_CAL_DQS values.
This saves and restores the values for suspend/resume until the root
of the problem is figured out

Signed-off-by: Derek Basehore <dbasehore@chromium.org>
7 years agorockchip: Add MIN() and MAX() macros back to M0 code
Julius Werner [Tue, 31 Jan 2017 02:26:07 +0000 (18:26 -0800)]
rockchip: Add MIN() and MAX() macros back to M0 code

These macros were accidentally deleted in a previous cleanup. This
slipped through because the code using them is currently unused, but
that may change in the future.

Signed-off-by: Julius Werner <jwerner@chromium.org>
7 years agorockchip: Clean up M0 Makefile, clarify float-abi
Julius Werner [Tue, 31 Jan 2017 00:13:21 +0000 (16:13 -0800)]
rockchip: Clean up M0 Makefile, clarify float-abi

This patch shuffles the M0 Makefile flags around a bit trying to make
their purpose clearer and remove duplication. Since all three build
steps (compiling, assembling, linking) actually call GCC, remove the
misleading aliases $(AS) and $(LD) to avoid confusion that those tools
might be called directly. Split flags into a common group that has
meaning for all three steps and separate variables specific to each
step. Remove -nostartfiles which is a strict subset of -nostdlib.

Also add explicit parameters for -mfloat-abi=soft, -fomit-frame-pointer
and -fno-common. If omitted these settings depend on the toolchain's
built-in default and cause various problems if they resolve to
unexpected values.

Signed-off-by: Julius Werner <jwerner@chromium.org>
7 years agorockchip: rk3399: Clean up and seprate secure parts from SoC codes
Xing Zheng [Fri, 24 Feb 2017 06:56:41 +0000 (14:56 +0800)]
rockchip: rk3399: Clean up and seprate secure parts from SoC codes

The goal is that make clear the secure and SoC codes. Now cleaning them
will help secure code extensions for RK3399 in the future.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
7 years agorockchip: rk3399: sperate the BL31 parameters for sharing
Xing Zheng [Thu, 22 Dec 2016 10:34:14 +0000 (18:34 +0800)]
rockchip: rk3399: sperate the BL31 parameters for sharing

Maybe the coreboot will reference the BL31 parameters (e.g the TZRAM_BASE
and TZRAM_SIZE for DDR secure regions), we can split them and don't have
to hardcode the range in two places.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
7 years agorockchip: rk3399: configure the DDR secure region for BL31 image
Xing Zheng [Fri, 24 Feb 2017 06:47:51 +0000 (14:47 +0800)]
rockchip: rk3399: configure the DDR secure region for BL31 image

Move the BL31 loaded base address 0x10000 to 0x1000, and configure
the the memory range 0~1MB is secure, the goal is that make sure
the BL31 image will be not modified.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
7 years agorockchip: Clean up header and referenced files
Xing Zheng [Fri, 24 Feb 2017 08:26:11 +0000 (16:26 +0800)]
rockchip: Clean up header and referenced files

So far, there are more and more features are supported on the RK3399,
meanwhile, these features are increasingly being defined and intertwined.
It's time to clean up and make them clearer.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
7 years agorockchip: rk3399: Don't wait for vblank in M0 for ddrfreq
Derek Basehore [Mon, 9 Jan 2017 23:38:57 +0000 (15:38 -0800)]
rockchip: rk3399: Don't wait for vblank in M0 for ddrfreq

This removes waiting for vblank on the M0 during ddrfreq transitions.
That will now be done in the kernel to allow scheduling to be done on
the CPU core that changes the ddr frequency. Waiting for vblank in
the M0 would have the CPU core that waits on the M0 spin looping for
up to 16ms (1 frame for the display).

Signed-off-by: Derek Basehore <dbasehore@chromium.org>
7 years agorockchip: rk3399: restore PMU_CRU_GATEDIS_CON0 value after ddr dvfs
Lin Huang [Fri, 30 Dec 2016 03:50:01 +0000 (11:50 +0800)]
rockchip: rk3399: restore PMU_CRU_GATEDIS_CON0 value after ddr dvfs

we will set PMU_CRU_GATEDIS_CON0 when idle port, it will enable
all clock, for save power consumption, we need to restore old value
when finish it.

Signed-off-by: Lin Huang <hl@rock-chips.com>
7 years agorockchip: rk3399: fix PMU_CRU_GATEDIS_CON0 setting error
Lin Huang [Fri, 30 Dec 2016 05:53:25 +0000 (13:53 +0800)]
rockchip: rk3399: fix PMU_CRU_GATEDIS_CON0 setting error

As rk3399 TRM1.1 document show, when set PMU_CRU_GATEDIS_CON0/1
register, it need set the write_mask bit (bit16 ~ bit31), but as
we test, it not need it. So need to correct the setting way, otherwise
it will set wrong value to this register.

Signed-off-by: Lin Huang <hl@rock-chips.com>
7 years agoFIXUP: rockchip: rk3399: fix the incorrect bit during m0_init
Xing Zheng [Tue, 20 Dec 2016 12:44:41 +0000 (20:44 +0800)]
FIXUP: rockchip: rk3399: fix the incorrect bit during m0_init

We found that the DUT will be hanged if we don't set the bit_1 of the
PMUCRU_GATEDIS_CON0. But, from the TRM, there is weird that the bit_1
is set the clk_center1_gating_dis, not clk_pmum0_gating_dis. Is the
TRM incorrect? We need to check it with the IC team and re-clean the
commit message and explain it tomorrow.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
7 years agorockchip: rk3399: improve the m0 enable flow
Lin Huang [Mon, 12 Dec 2016 07:18:08 +0000 (15:18 +0800)]
rockchip: rk3399: improve the m0 enable flow

This patch do following things:
1. Request hresetn_cm0s_pmu_req first then request
   poresetn_cm0s_pmu_req during M0 enable.
2. Do not diable M0 clock for ddr dvfs.
3. Correct the clk_pmum0_gating_dis bit, it is BIT0 not BIT1
4. do not set/clear hclk_noc_pmu_en in M0 code, it does not relate
   to the M0 clock.

Signed-off-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Derek Basehore <dbasehore@chromium.org>
7 years agorockchip: rk3399: check vop status when we wait dma finish flag
Lin Huang [Thu, 1 Dec 2016 08:55:05 +0000 (16:55 +0800)]
rockchip: rk3399: check vop status when we wait dma finish flag

When vop is disabled and we read the vop register the system will
hang, so check vop status when we wait for the DMA finish flag to
avoid this sitiuation. This is done by checking for standby, DMA stop
mode, and disabled window states. Any one of these will prevent the
DMA finish flag from triggering.

Signed-off-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Derek Basehore <dbasehore@chromium.org>
7 years agorockchip: rk3399: add stopwatch functions to m0
Lin Huang [Wed, 30 Nov 2016 08:57:08 +0000 (16:57 +0800)]
rockchip: rk3399: add stopwatch functions to m0

There is system timer in m0, we can use it to implement a set of
stopwatch functions for measuring timeouts.

Signed-off-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Derek Basehore <dbasehore@chromium.org>
7 years agorockchip: rk3399: dram: set all ddr frequency pll_postdiv values to 0
Lin Huang [Thu, 15 Dec 2016 07:08:47 +0000 (15:08 +0800)]
rockchip: rk3399: dram: set all ddr frequency pll_postdiv values to 0

The phy pll needs to get 2X frequency to the DDR, so set the
pll_postdiv to 0.

Signed-off-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Derek Basehore <dbasehore@chromium.org>
7 years agorockchip: rk3399: enable CA training when do ddr dfs
Lin Huang [Fri, 16 Dec 2016 05:59:07 +0000 (13:59 +0800)]
rockchip: rk3399: enable CA training when do ddr dfs

For ddr dfs stable, We need to enable ddr CA training
when do ddr dfs.

Signed-off-by: Lin Huang <hl@rock-chips.com>
7 years agorockchip: rk3399: fix hang in ddr set rate
Derek Basehore [Fri, 24 Feb 2017 06:33:03 +0000 (14:33 +0800)]
rockchip: rk3399: fix hang in ddr set rate

This fixes a hang with setting the DRAM rate based on a race condition
with the M0 which sets the DRAM rate. The AP can also starve the M0,
so this also delays the AP reads to the DONE parameter for the M0.

Signed-off-by: Derek Basehore <dbasehore@chromium.org>
7 years agorockchip: rk3399: Enable per CS training at 666MHz
Derek Basehore [Thu, 10 Nov 2016 02:28:19 +0000 (18:28 -0800)]
rockchip: rk3399: Enable per CS training at 666MHz

This enables per CS training at 666MHz and above for ddrfreq per
vendor recommendation. Since the threshold was used for latency was
the same value, this also adds a new value for that.

Signed-off-by: Derek Basehore <dbasehore@chromium.org>
7 years agorockchip: rk3399: add support for ddrfreq suspend/resume
Derek Basehore [Fri, 24 Feb 2017 06:31:36 +0000 (14:31 +0800)]
rockchip: rk3399: add support for ddrfreq suspend/resume

This patch sets the frequency configuration of the next DRAM DFS index
to the configuration of the current index. This does not perform a
frequency transition. It just configures registers so the training on
resume for both indices will be correct.

Signed-off-by: Derek Basehore <dbasehore@chromium.org>
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
7 years agork3399: dram: use PMU M0 to do ddr frequency scaling
Xing Zheng [Wed, 26 Oct 2016 13:25:26 +0000 (21:25 +0800)]
rk3399: dram: use PMU M0 to do ddr frequency scaling

We used dcf do ddr frequency scaling, but we just include a dcf
binary, it hard to maintain later, we have M0 compile flow in ATF,
and M0 can also work for ddr frequency scaling, so let's use it.

Signed-off-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>