Dimitris Papastamos [Mon, 19 Jun 2017 14:54:58 +0000 (15:54 +0100)]
juno: Fix AArch32 build
Commit
6de8b24f52cf2bd74adefbaa86dd2a0676c3eaa2 broke Juno AArch32
build.
Change-Id: Ied70d9becb86e53ccb46a2e3245e2a551d1bf701
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
Dimitris Papastamos [Tue, 13 Jun 2017 11:33:39 +0000 (12:33 +0100)]
aarch32: Fix L2CTRL definition for Cortex A57 and A72
Fixes ARM-software/tf-issues#495
Change-Id: I6a0aea78f670cc199873218a18af1d9cc2a6fafd
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
Dimitris Papastamos [Mon, 5 Jun 2017 13:55:41 +0000 (14:55 +0100)]
aarch32: Implement errata workarounds for Cortex A57
This brings the implementation on par with the software
errata workarounds for AArch64.
Change-Id: I98a85fd92e32ae4259f4ec5b3e93cffc87090064
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
Dimitris Papastamos [Mon, 5 Jun 2017 12:37:25 +0000 (13:37 +0100)]
aarch32: Implement errata workarounds for Cortex A53
This brings the implementation on par with the software
errata workarounds for AArch64.
Change-Id: Id103602e35b1c0ad3705a5b2b7cdb34dd8a8c5e2
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
Dimitris Papastamos [Mon, 5 Jun 2017 12:36:34 +0000 (13:36 +0100)]
aarch32: Implement cpu_rev_var_hs()
Helper function to assist with errata workaround application.
Change-Id: Idba42ca238442cc826f43444dbfa754e433a5e5e
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
Dimitris Papastamos [Wed, 7 Jun 2017 11:22:01 +0000 (12:22 +0100)]
sp_min: Flush console at end of main()
Flush the console so the errata report is printed correctly
before exit to normal world.
Change-Id: Idd6b5199b5fb8bda9d16a7b5c6426cdda7c73167
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
Dimitris Papastamos [Wed, 7 Jun 2017 12:45:41 +0000 (13:45 +0100)]
sp_min: Implement `sp_min_plat_runtime_setup()`
On ARM platforms before exiting from SP_MIN ensure that
the default console is switched to the runtime serial port.
Change-Id: I0ca0d42cc47e345d56179eac16aa3d6712767c9b
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
davidcunado-arm [Tue, 20 Jun 2017 11:20:08 +0000 (12:20 +0100)]
Merge pull request #966 from davidcunado-arm/dc/build_with_gcc6.2
Resolve build errors flagged by GCC 6.2
David Cunado [Thu, 1 Jun 2017 11:48:39 +0000 (12:48 +0100)]
Resolve build errors flagged by GCC 6.2
With GCC 6.2 compiler, more C undefined behaviour is being flagged as
warnings, which result in build errors in ARM TF build.
This patch addresses issue caused by enums with values that exceed
maximum value for an int. For these cases the enum is converted to
a set of defines.
Change-Id: I5114164be10d86d5beef3ea1ed9be5863855144d
Signed-off-by: David Cunado <david.cunado@arm.com>
davidcunado-arm [Tue, 20 Jun 2017 09:21:38 +0000 (10:21 +0100)]
Merge pull request #991 from davidcunado-arm/dc/update_hikey
hikey960: migrate to use A53 specific defines
David Cunado [Mon, 19 Jun 2017 10:48:22 +0000 (11:48 +0100)]
hikey960: migrate to use A53 specific defines
The patch
fb7d32e5881ef2445e8fe2305005f5590d4a7cfa migrated the CPU
libraries to have unique defines, prefixing them with the CPU name.
This patch migrates the hikey960 platform port to use the A53 specific
defines.
Change-Id: Id76f544b0b236bbd4974ab5ffa1203f073c20021
Signed-off-by: David Cunado <david.cunado@arm.com>
davidcunado-arm [Fri, 16 Jun 2017 11:06:24 +0000 (12:06 +0100)]
Merge pull request #953 from vwadekar/tegra-misra-fixes-v1
Tegra misra fixes v1
davidcunado-arm [Fri, 16 Jun 2017 08:17:45 +0000 (09:17 +0100)]
Merge pull request #984 from masahir0y/uniphier
uniphier memory-overrun bug fix
davidcunado-arm [Fri, 16 Jun 2017 08:17:28 +0000 (09:17 +0100)]
Merge pull request #986 from jagadeeshujja/jagujj/fix-get-power-state
CSS:Fix scpi "get_power_state" when ARM_PLAT_MT is set
davidcunado-arm [Thu, 15 Jun 2017 22:57:04 +0000 (23:57 +0100)]
Merge pull request #980 from dp-arm/dp/make-fix
tools: Use exported quiet flag from top-level Makefile
davidcunado-arm [Thu, 15 Jun 2017 22:50:30 +0000 (23:50 +0100)]
Merge pull request #981 from soby-mathew/sm/cov_scmi
Fix coverity error in CSS SCMI driver
davidcunado-arm [Thu, 15 Jun 2017 22:26:01 +0000 (23:26 +0100)]
Merge pull request #985 from hzhuang1/remove_mailbox
hikey960: remove mailbox driver
jagadeesh ujja [Thu, 11 May 2017 11:02:18 +0000 (16:32 +0530)]
CSS:Fix scpi "get_power_state" when ARM_PLAT_MT is set
The ARM_PLAT_MT bit enables the support for MT bit in
MPIDR format. This means that the level 0 affinity
represents the thread and CPU / Cluster levels are
at affinity level 1 and 2 respectively.
This was not catered for in the scpi 'css_scp_get_power_state, API.
Since the SCPI driver can only cater for single threaded CPUs,
this patch fixes the problem by catering for this shift by
effectively ignoring the Thread (level 0) affinity level.
Change-Id: If44f55c9fb2773c8d3f8a9bbcf5420a6f7409dfe
Signed-off-by: jagadeesh ujja <jagadeesh.ujja@arm.com>
Haojian Zhuang [Thu, 15 Jun 2017 02:30:37 +0000 (10:30 +0800)]
hikey960: remove mailbox driver
Since this mailbox driver is abandoned, remove it.
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Masahiro Yamada [Thu, 15 Jun 2017 00:32:12 +0000 (09:32 +0900)]
uniphier: fix memory over-run bug
Check the array index before the write. This issue was found by a
static analysis tool.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Anthony Zhou [Mon, 6 Mar 2017 08:06:45 +0000 (16:06 +0800)]
Tegra186: mce: fix MISRA defects
Main fixes:
* Added explicit casts (e.g. 0U) to integers in order for them to be
compatible with whatever operation they're used in [Rule 10.1]
* Force operands of an operator to the same type category [Rule 10.4]
* Added curly braces ({}) around if/while statements in order to
make them compound [Rule 15.6]
* Added parentheses [Rule 12.1]
* Voided non C-library functions whose return types are not used [Rule 17.7]
Change-Id: I91404edec2e2194b1ce2672d2a3fc6a1f5bf41f1
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Anthony Zhou [Thu, 27 Apr 2017 14:00:54 +0000 (22:00 +0800)]
Tegra: delay_timer: fix MISRA defects
Main fixes:
* Include header file for function declarations [Rule 8.4]
* Move global object into function [Rule 8.9]
Change-Id: I1bc9f3f0ebd4ffc0b8444ac856cd97b0cb56bda4
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
Varun Wadekar [Fri, 26 May 2017 01:06:59 +0000 (18:06 -0700)]
Tegra: gic: fix MISRA defects
Main fixes:
* Use int32_t replace int, use uint32_t replace unsign int [Rule 4.6]
* Added explicit casts (e.g. 0U) to integers in order for them to be
compatible with whatever operation they're used in [Rule 10.1]
* Force operands of an operator to the same type category [Rule 10.4]
* Fixed assert/if statements conditions to be essentially boolean [Rule 14.4]
* Added curly braces ({}) around if statements in order to
make them compound [Rule 15.6]
* Convert macros form headers to unsigned ints
Change-Id: I8051cc16499cece2039c9751bd347645f40f0901
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Anthony Zhou [Fri, 24 Feb 2017 06:44:21 +0000 (14:44 +0800)]
Tegra: fiq_glue: fix MISRA defects
Main fixes:
* Added explicit casts (e.g. 0U) to integers in order for them to be
compatible with whatever operation they're used in [Rule 10.1]
* Convert object type to match the type of function parameters
[Rule 10.3]
* Added curly braces ({}) around if statements in order to
make them compound [Rule 15.6]
* Expressions resulting from the expansion of macro parameters
shall be enclosed in parentheses[Rule 20.7]
Change-Id: I5cf83caafcc1650b545ca731bf3eb8f0bfeb362b
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
Anthony Zhou [Mon, 13 Mar 2017 08:47:58 +0000 (16:47 +0800)]
Tegra: pmc: fix defects flagged during MISRA analysis
Main fixes:
* Fixed if/while statement conditional to be essentially boolean [Rule 14.4]
* Added curly braces ({}) around if/for/while statements in order to
make them compound [Rule 15.6]
* Added explicit casts (e.g. 0U) to integers in order for them to be
compatible with whatever operation they're used in [Rule 10.1]
Change-Id: Ic72b248aeede6cf18bf85051188ea7b8fd8ae829
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
Varun Wadekar [Wed, 26 Apr 2017 15:31:50 +0000 (08:31 -0700)]
Tegra: memctrl: check GPU reset state from common place
This patch moves the GPU reset state check, during VideoMem resize, to the
common SiP handler, to reduce code duplication.
Change-Id: I3818c5f104b809da83dc2a61d6a8149606f81c13
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Varun Wadekar [Tue, 18 Apr 2017 16:55:54 +0000 (09:55 -0700)]
Tegra: memctrl_v2: fix software logic to check "flush complete"
This patch fixes the logic to check if the command written to the
MC_CLIENT_HOTRESET_CTRLx registers, was accepted by the hardware module.
Change-Id: If94fff9424555cb4688042eda17b4b20f4eb399a
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Varun Wadekar [Mon, 24 Apr 2017 21:17:12 +0000 (14:17 -0700)]
Tegra: add explicit casts for integer macros
This patch adds explicit casts (U(x)) to integers in the tegra_def.h
headers, to make them compatible with whatever operation they're used
in [MISRA-C Rule 10.1]
Change-Id: Ic5fc611aad986a2c6e6e6f625e0753ab9b69eb02
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Varun Wadekar [Fri, 26 May 2017 01:04:48 +0000 (18:04 -0700)]
include: add U()/ULL() macros for constants
This patch uses the U() and ULL() macros for constants, to fix some
of the signed-ness defects flagged by the MISRA scanner.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Varun Wadekar [Thu, 18 May 2017 17:32:51 +0000 (10:32 -0700)]
Add U() macro to share constants between C and other sources
This patch adds the U(_x) macros to utils_def.h to allow constants to
be shared between C and other sources.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Varun Wadekar [Mon, 5 Jun 2017 21:54:46 +0000 (14:54 -0700)]
Unique names for defines in the CPU libraries
This patch makes all the defines in the CPU libraries unique,
by prefixing them with the CPU name.
NOTE: PLATFORMS USING THESE MACROS WILL HAVE TO UPDATE THEIR CODE
TO START USING THE UPDATED NAMES
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Varun Wadekar [Wed, 7 Jun 2017 16:57:42 +0000 (09:57 -0700)]
Tegra: enable 'signed-comparison' compilation warning/errors
This patch enables the 'sign-compare' flag, to enable warning/errors
for comparisons between signed/unsigned variables. The warning has
been enabled for all the Tegra platforms, to start with.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
davidcunado-arm [Wed, 14 Jun 2017 13:59:36 +0000 (14:59 +0100)]
Merge pull request #979 from soby-mathew/sm/aarch32_macro_fix
Fix stdlib defines for AArch32
davidcunado-arm [Tue, 13 Jun 2017 21:18:17 +0000 (22:18 +0100)]
Merge pull request #974 from masahir0y/uniphier
UniPhier Initial Support
davidcunado-arm [Tue, 13 Jun 2017 08:21:09 +0000 (09:21 +0100)]
Merge pull request #982 from hzhuang1/fix_hikey960
Fix hikey960
Haojian Zhuang [Mon, 12 Jun 2017 14:20:38 +0000 (22:20 +0800)]
hikey960: fix the calculation in boardid
Since the type of ADC value is always unsigned int, don't
need to check the value with negative value.
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Haojian Zhuang [Mon, 12 Jun 2017 14:18:15 +0000 (22:18 +0800)]
ufs: fix the and operator
Should use AND (&), not &&.
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Masahiro Yamada [Mon, 15 May 2017 04:00:00 +0000 (13:00 +0900)]
uniphier: add TSP support
Add TSP to test BL32 without relying on external projects.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada [Sat, 3 Sep 2016 02:37:40 +0000 (11:37 +0900)]
uniphier: support Socionext UniPhier platform
Initial commit for Socionext UniPhier SoC support. BL1, Bl2, and
BL31 are supported. Refer to docs/plat/socionext-uniphier.md for
more detais.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
dp-arm [Tue, 2 May 2017 10:14:29 +0000 (11:14 +0100)]
tools: Use exported quiet flag from top-level Makefile
When V is set from the command line, the value is passed to the tools'
Makefiles as well.
Change-Id: I91a1f66de5c1ae6f36b6c9f0a9bd550d4a30f092
Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
Soby Mathew [Fri, 9 Jun 2017 14:04:43 +0000 (15:04 +0100)]
Fix coverity error in CSS SCMI driver
Change-Id: Ia7d731f429e452e4bc9f9a553d7105b6394c621c
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
Soby Mathew [Tue, 6 Jun 2017 09:01:03 +0000 (10:01 +0100)]
Fix stdlib defines for AArch32
Some of the macro defines in the header files of `include/lib/stdlib/machine/`
folder are not correct for AArch32. This patch fixes the same.
Change-Id: I8bfaf638a7986fd902648d2074537bd26c313cb3
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
davidcunado-arm [Fri, 9 Jun 2017 12:49:39 +0000 (13:49 +0100)]
Merge pull request #972 from achingupta/ag/freebsd-dt-change
Device tree changes to boot FreeBSD on FVPs
davidcunado-arm [Fri, 9 Jun 2017 12:49:25 +0000 (13:49 +0100)]
Merge pull request #971 from Xilinx/tegra
tegra: Fix build errors
davidcunado-arm [Fri, 9 Jun 2017 11:03:52 +0000 (12:03 +0100)]
Merge pull request #973 from danh-arm/dh/add-maintainers
Docs: Clarify copyright requirements
davidcunado-arm [Fri, 9 Jun 2017 11:03:35 +0000 (12:03 +0100)]
Merge pull request #968 from antonio-nino-diaz-arm/an/snprintf-alt
mbedtls: Don't use tf_snprintf if option not defined
davidcunado-arm [Thu, 8 Jun 2017 16:34:44 +0000 (17:34 +0100)]
Merge pull request #967 from rockchip-linux/rockchip-cleanup-
20170606
RK3399: Shrink M0 SRAM code to fit in PMUSRAM
Soren Brinkmann [Wed, 7 Jun 2017 16:51:26 +0000 (09:51 -0700)]
tegra: Fix build errors
The 'impl' variable is guarded by the symbol DEBUG, but used in an INFO
level print statement. INFO is defined based on LOG_LEVEL. Hence, builds
would fail when
- DEBUG=0 && LOG_LEVEL>=LOG_LEVEL_INFO with a variable used but not defined
- DEBUG=1 && LOG_LEVEL<LOG_LEVEL_INFO with a variable defined but not used
Fixing this by guarding impl with the same condition that guards INFO.
Fixes ARM-software/tf-issues#490
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Dan Handley [Tue, 6 Jun 2017 16:26:37 +0000 (17:26 +0100)]
Docs: Clarify copyright requirements
Clarify copyright requirements in contributing.md.
Also clarify maintainership structure by adding a new maintainers.md. This
imports individual maintainer details from the GitHub wiki.
Fixes ARM-software/tf-issues#488
Change-Id: I7135d3f77ea45533f667de7e1dcdf65697486a91
Signed-off-by: Dan Handley <dan.handley@arm.com>
danh-arm [Thu, 8 Jun 2017 10:46:34 +0000 (11:46 +0100)]
Merge pull request #970 from vingu-linaro/enable-pmf-rt-instr-hikey
Enable pmf rt instr hikey
danh-arm [Thu, 8 Jun 2017 08:50:03 +0000 (09:50 +0100)]
Merge pull request #959 from hzhuang1/hikey960_v1
Hikey960 v1
Lin Huang [Fri, 12 May 2017 02:26:32 +0000 (10:26 +0800)]
rockchip: check wakeup cpu when resume
unlike rk3399 and rk3368, there are some rockchip 64bit SOC
do not have CPUPD, and pmu_cpuson_entrypoint() is common
function for rockchip platform, so we need to check wakeup
cpu when resume.
Change-Id: I6313e8a9d7c16b03e033414f0cb281646c2159ff
Signed-off-by: Lin Huang <hl@rock-chips.com>
Lin Huang [Tue, 16 May 2017 08:40:46 +0000 (16:40 +0800)]
rockchip/rk3399: enable PMU_PERILP_PD_EN bit when suspend
with PMU_PERILP_PD_EN bit enable, the soc will shutdown
cm0, crypto, dcf, imem(normal SRAM), dmac, bootrom, efuse_con,
spi, i2c, uart, saradc, tsadc when suspend, we have M0 code
need to run when suspend in normal SRAM, so we need to take
care of that.
Change-Id: I8c066637e5b81d4b1d53197450b9d592cbe00793
Signed-off-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Derek Basehore <dbasehore@chromium.org>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Derek Basehore [Tue, 16 May 2017 04:18:28 +0000 (21:18 -0700)]
rockchip/rk3399: Move DRAM restore to PMUSRAM
This moves the DRAM restore code to PMUSRAM. This is so that the
voltage domain that contains the SRAM that it was stored in before may
be turned off during system suspend.
Change-Id: Id761181a30caadd12f1ce061d1034f3159a76d28
Signed-off-by: Derek Basehore <dbasehore@chromium.org>
Derek Basehore [Sat, 13 May 2017 04:29:13 +0000 (21:29 -0700)]
rockchip/rk3399: convert to for-loops to save code space
This converts two functions to use for-loops. This saves a bit of
space to help moving DRAM resume code to PMUSRAM.
Change-Id: Ie6ca490cf50c2ec83335cf1845b337c3e8a47496
Signed-off-by: Derek Basehore <dbasehore@chromium.org>
Derek Basehore [Thu, 11 May 2017 06:22:02 +0000 (23:22 -0700)]
rockchip/rk3399: Remove unneeded if statement
The removed if statement would make the same check that the for loop
it is in does to break out of the for loop, so it doesn't make any
sense to keep it there.
Change-Id: I819c29f9182e6de1fc47e418aed15ad38e8f9fa9
Signed-off-by: Derek Basehore <dbasehore@chromium.org>
Derek Basehore [Thu, 11 May 2017 04:59:31 +0000 (21:59 -0700)]
rockchip/rk3399: Remove unneeded register sets
This removes the mmio_... function calls to set the multicast bit for
the PHY registers when overriding the write leveling values. These are
not needed since multicast is set by default when calling the
function, and it's also better not to leave the side effect of
disabling multicast when exiting the function.
Change-Id: I83e089a2a2d55268b3832f36724c3b2c4be81082
Signed-off-by: Derek Basehore <dbasehore@chromium.org>
Derek Basehore [Sun, 7 May 2017 06:22:23 +0000 (23:22 -0700)]
rockchip/rk3399: remove unneeded DDR restore function
This removes the phy_dll_bypass_set function as it is unneeded. The
values that function sets are saved during suspend, so the proper
values will be restored on resume.
Change-Id: I17542206c56e639ce8cb6375233145167441d4e2
Signed-off-by: Derek Basehore <dbasehore@chromium.org>
Derek Basehore [Sat, 6 May 2017 00:53:33 +0000 (17:53 -0700)]
rockchip/rk3399: Save space for DRAM suspend data
This removes the space allocation for the unused PHY register space.
For instance in PHY registers 0-127, only 0-90 are used, so don't save
the 91-127 registers. This saves about 1.6KB of space.
Change-Id: I0c9f6d9bed8f0c1f3b8b805dfb10cf0c06208919
Signed-off-by: Derek Basehore <dbasehore@chromium.org>
Lin Huang [Thu, 4 May 2017 08:02:45 +0000 (16:02 +0800)]
rockchip: add pmusram section
the function pmu_cpuon_entrypoint() need to run in the pmusram,
we just copy bin file to pmusram before, now we add pmusram section
and link pmu_cpuon_entrypoint() to pmusram directly
Change-Id: Iae31e4c01c480c8e6f565a8f588332b478efdb16
Signed-off-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Lin Huang [Wed, 22 Feb 2017 10:24:55 +0000 (18:24 +0800)]
rockchip/rk3399: fix DRAM gate training issue
The differential signal of DQS need keep low level
before gate training. It need enable RPULL and disable
PHY side ODT to ensure it when do gate training.
But it can not access the PHY registers to do it when
perform DFS.So the workaroud as below: It is ensure that
the PHY's read gate is landing somewhere in the incoming
DQS's pulses before it starts searching for pre-amble window.
It need get the rddqs_delay_ps to calculate the start point
of gate training for DFS.
Change-Id: I79eabcf4ec9a9c8f4539f68a51f22afba49c72fe
Signed-off-by: Lin Huang <hl@rock-chips.com>
Haojian Zhuang [Thu, 1 Jun 2017 08:46:41 +0000 (16:46 +0800)]
hikey960: add document
Add document on HiKey960 platform and how to build.
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Haojian Zhuang [Thu, 1 Jun 2017 07:20:46 +0000 (15:20 +0800)]
hikey960: support BL31
Support BL31 on HiKey960 platform. Implement PSCI.
Signed-off-by: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Haojian Zhuang [Thu, 1 Jun 2017 06:03:22 +0000 (14:03 +0800)]
hikey960: support BL2
BL2 loads MCU firmware & BL31 on hikey960 platform. The MCU firmware
is used to implement low power feature.
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Haojian Zhuang [Thu, 1 Jun 2017 04:15:14 +0000 (12:15 +0800)]
hikey960: support BL1 on hikey960 platform
Support BL1 on HiKey960 platform. When recovery mode is detected,
BL1 loads NS BL1U that flushs images into UFS. When normal boot
mode is detected, BL1 loads BL2.
Fix for https://github.com/ARM-software/tf-issues/issues/486
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Vincent Guittot [Wed, 7 Jun 2017 08:12:05 +0000 (10:12 +0200)]
hikey: enable PMF and instrumentations
enable PMF service call and instrumetion for hikey platform
Signed-off-by: Vincent Guittot <vincent.guittot@linaro.org>
Haojian Zhuang [Fri, 2 Jun 2017 00:51:17 +0000 (08:51 +0800)]
stdlib: support AARCH32 in endian head file
Add the support of AARCH32 in endian head file. The code is also
imported from FreeBSD 11.0. It's based on commit in below.
commit
4e3a5b429989b4ff621682ff1462f801237bd551
Author: mmel <mmel@FreeBSD.org>
Date: Tue Nov 10 12:02:41 2015 +0000
ARM: Remove trailing whitespace from sys/arm/include
No functional changes.
Approved by: kib (mentor)
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Haojian Zhuang [Thu, 1 Jun 2017 13:55:53 +0000 (21:55 +0800)]
stdlib: import endian head file from freebsd
Import endian head files from FreeBSD 11.0. The link of FreeBSD source code
is https://github.com/freebsd/freebsd
Import machine/endian.h from sys/arm64/include/endian.h in FreeBSD.
commit
d09ff72cef8e35dbf62f7363dcbf07b453f06243
Author: andrew <andrew@FreeBSD.org>
Date: Mon Mar 23 11:54:56 2015 +0000
Add the start of the arm64 machine headers. This is the subset needed to
start getting userland libraries building.
Reviewed by: imp
Sponsored by: The FreeBSD Foundation
Import sys/endian.h from sys/sys/endian.h in FreeBSD.
commit
3c3fa2f5b0c7640373fcbcc3f667bf7794e8e609
Author: phk <phk@FreeBSD.org>
Date: Thu May 20 06:16:13 2010 +0000
Fix some way-past-brucification complaints from FlexeLint.
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
danh-arm [Tue, 6 Jun 2017 12:39:58 +0000 (13:39 +0100)]
Merge pull request #969 from Summer-ARM/sq/update-doc
Update the path for firmware_image_package.h in firmware-design.md
Antonio Nino Diaz [Tue, 6 Jun 2017 09:54:39 +0000 (10:54 +0100)]
mbedtls: Don't use tf_snprintf if option not defined
If `MBEDTLS_PLATFORM_SNPRINTF_ALT` isn't used, the function
`mbedtls_platform_set_snprintf()` isn't defined.
In case a platform uses a different mbed TLS configuration file than
the one provided by the Trusted Firmware, and it doesn't define the
mentioned build option, this will result in a build error.
This patch modifies the initialization code so that
`mbedtls_platform_set_snprintf()` is only used if
`MBEDTLS_PLATFORM_SNPRINTF_ALT` is defined, allowing platforms to use
it or not depending on their needs.
Change-Id: I1d5c86d57e9b2871ba463030bf89210ebec5178e
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
danh-arm [Mon, 5 Jun 2017 13:45:10 +0000 (14:45 +0100)]
Merge pull request #964 from soby-mathew/sm/rsapss_sup
Add support for RSASSAPSS algorithm
danh-arm [Mon, 5 Jun 2017 13:42:59 +0000 (14:42 +0100)]
Merge pull request #963 from soby-mathew/sm/scmi_dev
Add SCMI power domain and system power protocol support
danh-arm [Mon, 5 Jun 2017 13:41:31 +0000 (14:41 +0100)]
Merge pull request #961 from jeenu-arm/gic-600
Introduce ARM GIC-600 driver
danh-arm [Mon, 5 Jun 2017 13:41:20 +0000 (14:41 +0100)]
Merge pull request #960 from jeenu-arm/cpu-libs
Add support for Cortex-A75 and Cortex-A55 CPUs
danh-arm [Mon, 5 Jun 2017 13:09:41 +0000 (14:09 +0100)]
Merge pull request #962 from antonio-nino-diaz-arm/an/fwu-checks
FWU: Check for overlaps when loading images, introduce `FWU_SMC_IMAGE_RESET`
Soby Mathew [Mon, 14 Nov 2016 12:44:32 +0000 (12:44 +0000)]
Add SCMI support for Juno platform
This patch adds the memory map region for the SCMI payload memory
and maps the Juno core indices to SCMI power domains via the
`plat_css_core_pos_to_scmi_dmn_id_map` array.
Change-Id: I0d2bb2a719ff5b6a9d8e22e91e1625ab14453665
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
Soby Mathew [Mon, 14 Nov 2016 12:25:45 +0000 (12:25 +0000)]
CSS: Add SCMI driver for SCP
This patch adds the SCMI driver for communicating with SCP. The power
domain management and system power management protocol of the SCMI
specification[1] is implemented in the driver. The SCP power management
abstraction layer for SCMI for CSS power management is also added.
A new buid option `CSS_USE_SCMI_DRIVER` is introduced to select SCMI
driver over SCPI.
[1] ARM System Control and Management Interface v1.0 (SCMI)
Document number: ARM DEN 0056A
Change-Id: I67265615a17e679a2afe810b9b0043711ba09dbb
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
Soby Mathew [Mon, 22 May 2017 15:12:33 +0000 (16:12 +0100)]
cert_create: Use RSASSA-PSS signature scheme for certificates
This patch modifies the `cert_create` tool to use RSASSA-PSS scheme for
signing the certificates. This is compliant with RSA PKCS_2_1 standard as
mandated by TBBR.
Note that the certificates generated by using cert_create tool after this
patch can be authenticated during TBB only if the corresponding mbedtls
driver in ARM Trusted Firmware has the corresponding support.
Change-Id: If224f41c76b3c4765ae2af5259e67f73602818a4
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
Soby Mathew [Wed, 31 May 2017 09:35:27 +0000 (10:35 +0100)]
Add support for RSASSAPSS algorithm in mbedtls crypto driver
This patch adds support for RSASSA-PSS Signature Algorithm for
X509 certificates in mbedtls crypto driver. Now the driver supports
RSA PKCS2_1 standard as mandated by TBBR.
NOTE: With this patch, the PKCS1_5 standard compliant RSA signature
is deprecated.
Change-Id: I9cf6d073370b710cc36a7b374a55ec96c0496461
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
Soby Mathew [Mon, 5 Jun 2017 11:18:04 +0000 (12:18 +0100)]
Increase heapsize for mbedtls library
The mbedTLS library requires larger heap memory for verification of RSASSA-PSS
signature in certificates during Trusted Board Boot. This patch increases the
heap memory for the same.
Change-Id: I3c3123d7142b7b7b01463516ec436734895da159
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
Summer Qin [Mon, 10 Apr 2017 16:14:38 +0000 (17:14 +0100)]
Update the path for firmware_image_package.h in firmware-design.md
Change-Id: Ic0a9b3c6d212e7171b37f944e11f079282dcce87
Signed-off-by: Summer Qin <summer.qin@arm.com>
Achin Gupta [Mon, 26 Sep 2016 09:22:56 +0000 (10:22 +0100)]
Device tree changes to boot FreeBSD on FVPs
FreeBSD does not understand #interrupt-map in a device tree. This prevents the
GIC from being set up correctly. This patch removes the #interrupt-map in the
device trees for the Base and Foundation FVPs. This enables correct boot of
FreeBSD on these platforms.
These changes have been tested with FreeBSD and an Ubuntu cloud image
(ubuntu-16.04-server-cloudimg-arm64-uefi1.img) to ensure compatibility with
Linux.
Change-Id: I1347acdcf994ec4b1dd843ba32af9951aa54db73
Signed-off-by: Achin Gupta <achin.gupta@arm.com>
Antonio Nino Diaz [Fri, 12 May 2017 15:51:59 +0000 (16:51 +0100)]
FWU: Introduce FWU_SMC_IMAGE_RESET
This SMC is as a means for the image loading state machine to go from
COPYING, COPIED or AUTHENTICATED states to RESET state. Previously, this
was only done when the authentication of an image failed or when the
execution of the image finished.
Documentation updated.
Change-Id: Ida6d4c65017f83ae5e27465ec36f54499c6534d9
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Antonio Nino Diaz [Thu, 1 Jun 2017 12:40:17 +0000 (13:40 +0100)]
FWU: Check for overlaps when loading images
Added checks to FWU_SMC_IMAGE_COPY to prevent loading data into a
memory region where another image data is already loaded.
Without this check, if two images are configured to be loaded in
overlapping memory regions, one of them can be loaded and
authenticated and the copy function is still able to load data from
the second image on top of the first one. Since the first image is
still in authenticated state, it can be executed, which could lead to
the execution of unauthenticated arbitrary code of the second image.
Firmware update documentation updated.
Change-Id: Ib6871e569794c8e610a5ea59fe162ff5dcec526c
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Antonio Nino Diaz [Fri, 12 May 2017 15:14:51 +0000 (16:14 +0100)]
Remove `DISABLE_PEDANTIC` build option
It doesn't make sense to use the `-pedantic` flag when building the
Trusted Firmware as we use GNU extensions and so our code is not
fully ISO C compliant. This flag only makes sense if the code intends to
be ISO C compliant.
Change-Id: I6273564112759ff57f03b273f5349733a5f38aef
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Jeenu Viswambharan [Tue, 6 Dec 2016 16:15:22 +0000 (16:15 +0000)]
Introduce ARM GIC-600 driver
ARM GIC-600 IP complies with ARM GICv3 architecture, but among others,
implements a power control register in the Redistributor frame. This
register must be programmed to mark the frame as powered on, before
accessing other registers in the frame. Rest of initialization sequence
remains the same.
The driver provides APIs for Redistributor power management, and
overrides those in the generic GICv3 driver. The driver data is shared
between generic GICv3 driver and that of GIC-600.
For FVP platform, the GIC-600 driver is chosen when FVP_USE_GIC_DRIVER
is set to FVP_GIC600. Also update user guide.
Change-Id: I321b2360728d69f6d4b0a747b2cfcc3fe5a20d67
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
David Wang [Wed, 9 Nov 2016 16:29:02 +0000 (16:29 +0000)]
Add support for Cortex-A75 and Cortex-A55 CPUs
Both Cortex-A75 and Cortex-A55 CPUs use the ARM DynamIQ Shared Unit
(DSU). The power-down and power-up sequences are therefore mostly
managed in hardware, and required software operations are considerably
simpler.
Change-Id: I68b30e6e1ebe7c041d5e67f39c59f08575fc7ecc
Co-authored-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
danh-arm [Thu, 1 Jun 2017 10:04:48 +0000 (11:04 +0100)]
Merge pull request #957 from hzhuang1/finish_hikey_psci
Finish hikey psci
danh-arm [Wed, 31 May 2017 15:40:56 +0000 (16:40 +0100)]
Merge pull request #958 from antonio-nino-diaz-arm/an/mbedtls-heap-size
mbedtls: Define optimized mbed TLS heap size
Antonio Nino Diaz [Fri, 19 May 2017 15:57:54 +0000 (16:57 +0100)]
mbedtls: Define optimized mbed TLS heap size
mbed TLS provides the debug API `mbedtls_memory_buffer_alloc_status()`
to analyse the RAM usage of the library.
When RSA is selected as algorithm, the maximum heap usage in FVP and
Juno has been determined empirically to be approximately 5.5 KiB.
However, The default heap size used when RSA is selected is 8 KiB.
This patch reduces the buffer from 8 KiB to 6 KiB so that the BSS
sections of both BL1 and BL2 are 2 KiB smaller when the firmware is
compiled with TBB support.
Change-Id: I43878a4e7af50c97be9c8d027c728c8483f24fbf
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
danh-arm [Wed, 31 May 2017 13:25:36 +0000 (14:25 +0100)]
Merge pull request #955 from hzhuang1/ufs
Add ufs stack and designware phy
danh-arm [Wed, 31 May 2017 13:23:41 +0000 (14:23 +0100)]
Merge pull request #956 from hzhuang1/fix_var_in_ddr
hikey: fix uninitialized variable in ddr code
Leo Yan [Sat, 27 May 2017 05:17:45 +0000 (13:17 +0800)]
hikey: pm: finish PSCI hook functions
This patch is to enable CPU suspend/resume and system level's
suspend/resume; also enable system power off state.
Signed-off-by: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Leo Yan [Sat, 27 May 2017 05:15:40 +0000 (13:15 +0800)]
hikey: bl31: enable CCI port for cluster 0
The cluster 0 doesn't rely on PSCI to enable it; so enable CCI port
for cluster 0 in BL31 platform setup flow.
Signed-off-by: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Leo Yan [Sat, 27 May 2017 05:12:40 +0000 (13:12 +0800)]
hikey: fix for CPU topology
Fix for CPU topology so present the CPU core numbers for two clusters;
Base on this fixing, the PSCI can maintain correct power states.
Signed-off-by: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Haojian Zhuang [Wed, 31 May 2017 04:42:10 +0000 (12:42 +0800)]
hikey: fix uninitialized variable in ddr code
Fix uninitliazed variable in ddr driver code.
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Haojian Zhuang [Wed, 31 May 2017 17:00:46 +0000 (11:00 -0600)]
drivers: add designware ufs driver
Initialized the designware UFS PHY.
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Haojian Zhuang [Wed, 31 May 2017 03:00:15 +0000 (11:00 +0800)]
drivers: add ufs stack
If UFS device is initialized, we could just make it out of
hibernation by UFS_FLAGS_SKIPINIT. And vendor's dirver is always
focus on PHY setting. We could use UFS driver directly if it
exits from hibernation.
There're eight LUNs in UFS device. The UFS driver only provides
the read/write API with LUN. User could define his own read/write
since user may want to access different LUNs.
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
davidcunado-arm [Tue, 30 May 2017 09:56:47 +0000 (10:56 +0100)]
Merge pull request #949 from antonio-nino-diaz-arm/an/printf-memory
Reduce code size when building with Trusted Board Boot enabled
davidcunado-arm [Thu, 25 May 2017 10:26:22 +0000 (11:26 +0100)]
Merge pull request #950 from danh-arm/hz/hikey
HiKey v3