danh-arm [Mon, 4 Aug 2014 09:34:18 +0000 (10:34 +0100)]
Merge pull request #179 from jcastillo-arm/jc/tf-issues/219
Call platform_is_primary_cpu() only from reset handler
danh-arm [Mon, 4 Aug 2014 09:31:54 +0000 (10:31 +0100)]
Merge pull request #178 from soby-mathew/sm/optmize_el3_context
Optimize EL3 register state stored in cpu_context structure
danh-arm [Fri, 1 Aug 2014 11:17:51 +0000 (12:17 +0100)]
Merge pull request #175 from vikramkanigiri/vk/spd-init-by-stack-unwinding
Vk/spd init by stack unwinding
Vikram Kanigiri [Tue, 15 Jul 2014 15:49:22 +0000 (16:49 +0100)]
Support asynchronous method for BL3-2 initialization
This patch adds support for BL3-2 initialization by asynchronous
method where BL3-1 transfers control to BL3-2 using world switch.
After BL3-2 initialization, it transfers control to BL3-3 via SPD
service handler. The SPD service handler initializes the CPU context
to BL3-3 entrypoint depending on the return function indentifier from
TSP initialization.
Fixes ARM-software/TF-issues#184
Change-Id: I7b135c2ceeb356d3bb5b6a287932e96ac67c7a34
Vikram Kanigiri [Tue, 15 Jul 2014 15:46:43 +0000 (16:46 +0100)]
Rework the TSPD setup code
There is no mechanism which allows the TSPD to specify what SPSR to
use when entering BL3-2 instead of BL3-3. This patch divides the
responsibility between tspd_setup() and tspd_init() for initializing
the TSPD and TSP to support the alternate BL3-2 initialization flow
where BL3-1 handsover control to BL3-2 instead of BL3-3.
SPSR generated by TSPD for TSP is preserved due the new division of
labour which fixes #174.
This patch also moves the cpu_context initialization code from
tspd_setup() to tspd_init() immediately before entering the TSP.
Instead tspd_setup() updates the BL3-2 entrypoint info structure
with the state required for initializing the TSP later.
Fixes ARM-software/TF-issues#174
Change-Id: Ida0a8a48d466c71d5b07b8c7f2af169b73f96940
Juan Castillo [Wed, 16 Jul 2014 14:53:43 +0000 (15:53 +0100)]
Call platform_is_primary_cpu() only from reset handler
The purpose of platform_is_primary_cpu() is to determine after reset
(BL1 or BL3-1 with reset handler) if the current CPU must follow the
cold boot path (primary CPU), or wait in a safe state (secondary CPU)
until the primary CPU has finished the system initialization.
This patch removes redundant calls to platform_is_primary_cpu() in
subsequent bootloader entrypoints since the reset handler already
guarantees that code is executed exclusively on the primary CPU.
Additionally, this patch removes the weak definition of
platform_is_primary_cpu(), so the implementation of this function
becomes mandatory. Removing the weak symbol avoids other
bootloaders accidentally picking up an invalid definition in case the
porting layer makes the real function available only to BL1.
The define PRIMARY_CPU is no longer mandatory in the platform porting
because platform_is_primary_cpu() hides the implementation details
(for instance, there may be platforms that report the primary CPU in
a system register). The primary CPU definition in FVP has been moved
to fvp_def.h.
The porting guide has been updated accordingly.
Fixes ARM-software/tf-issues#219
Change-Id: If675a1de8e8d25122b7fef147cb238d939f90b5e
Soby Mathew [Fri, 4 Jul 2014 15:02:26 +0000 (16:02 +0100)]
Optimize EL3 register state stored in cpu_context structure
This patch further optimizes the EL3 register state stored in
cpu_context. The 2 registers which are removed from cpu_context are:
* cntfrq_el0 is the system timer register which is writable
only in EL3 and it can be programmed during cold/warm boot. Hence
it need not be saved to cpu_context.
* cptr_el3 controls access to Trace, Floating-point, and Advanced
SIMD functionality and it is programmed every time during cold
and warm boot. The current BL3-1 implementation does not need to
modify the access controls during normal execution and hence
they are expected to remain static.
Fixes ARM-software/tf-issues#197
Change-Id: I599ceee3b73a7dcfd37069fd41b60e3d397a7b18
danh-arm [Mon, 28 Jul 2014 13:33:44 +0000 (14:33 +0100)]
Merge pull request #177 from jcastillo-arm/jc/tf-issues/096
Rework incorrect use of assert() and panic() in codebase
danh-arm [Mon, 28 Jul 2014 13:28:40 +0000 (14:28 +0100)]
Merge pull request #172 from soby-mathew/sm/asm_assert
Introduce asm assert and optimize crash reporting
danh-arm [Mon, 28 Jul 2014 13:27:25 +0000 (14:27 +0100)]
Merge pull request #170 from achingupta/ag/tf-issues#226
Simplify management of SCTLR_EL3 and SCTLR_EL1
danh-arm [Mon, 28 Jul 2014 13:24:52 +0000 (14:24 +0100)]
Merge pull request #169 from achingupta/ag/tf-issues#198
Ag/tf issues#198
Juan Castillo [Thu, 5 Jun 2014 08:45:36 +0000 (09:45 +0100)]
Rework incorrect use of assert() and panic() in codebase
Assert a valid security state using the macro sec_state_is_valid().
Replace assert() with panic() in those cases that might arise
because of runtime errors and not programming errors.
Replace panic() with assert() in those cases that might arise
because of programming errors.
Fixes ARM-software/tf-issues#96
Change-Id: I51e9ef0439fd5ff5e0edfef49050b69804bf14d5
Soby Mathew [Wed, 16 Jul 2014 08:23:52 +0000 (09:23 +0100)]
Add CPUECTLR_EL1 and Snoop Control register to crash reporting
This patch adds the CPUECTLR_EL1 register and the CCI Snoop Control
register to the list of registers being reported when an unhandled
exception occurs.
Change-Id: I2d997f2d6ef3d7fa1fad5efe3364dc9058f9f22c
Soby Mathew [Wed, 25 Jun 2014 09:07:40 +0000 (10:07 +0100)]
Rework the crash reporting in BL3-1 to use less stack
This patch reworks the crash reporting mechanism to further
optimise the stack and code size. The reporting makes use
of assembly console functions to avoid calling C Runtime
to report the CPU state. The crash buffer requirement is
reduced to 64 bytes with this implementation. The crash
buffer is now part of per-cpu data which makes retrieving
the crash buffer trivial.
Also now panic() will use crash reporting if
invoked from BL3-1.
Fixes ARM-software/tf-issues#199
Change-Id: I79d27a4524583d723483165dc40801f45e627da5
Soby Mathew [Mon, 14 Jul 2014 15:58:03 +0000 (16:58 +0100)]
Implement an assert() callable from assembly code
The patch implements a macro ASM_ASSERT() which can
be invoked from assembly code. When assertion happens,
file name and line number of the check is written
to the crash console.
Fixes ARM-software/tf-issues#95
Change-Id: I6f905a068e1c0fa4f746d723f18df60daaa00a86
Soby Mathew [Mon, 14 Jul 2014 15:57:23 +0000 (16:57 +0100)]
Introduce crash console APIs for crash reporting
This patch introduces platform APIs to initialise and
print a character on a designated crash console.
For the FVP platform, PL011_UART0 is the designated
crash console. The platform porting guide is also updated
to document the new APIs.
Change-Id: I5e97d8762082e0c88c8c9bbb479353eac8f11a66
Soby Mathew [Mon, 14 Jul 2014 14:43:21 +0000 (15:43 +0100)]
Parametrize baudrate and UART clock during console_init()
This patch adds baud rate and UART clock frequency as parameters
to the pl011 driver api console_init(). This allows each platform
to specify UART clock and baud rate according to their specific
hardware implementation.
Fixes ARM-software/tf-issues#215
Change-Id: Id13eef70a1c530e709b34dd1e6eb84db0797ced2
Soby Mathew [Tue, 24 Jun 2014 11:28:41 +0000 (12:28 +0100)]
Introduce asm console functions in TF
This patch replaces the pl011 console family of functions
with their equivalents defined in assembly. The baud rate is
defined by the PL011_BAUDRATE macro and IBRD and FBRD values
for pl011 are computed statically. This patch will enable
us to invoke the console functions without the C Runtime Stack.
Change-Id: Ic3f7b7370ded38bf9020bf746b362081b76642c7
Achin Gupta [Fri, 18 Jul 2014 17:38:28 +0000 (18:38 +0100)]
Simplify management of SCTLR_EL3 and SCTLR_EL1
This patch reworks the manner in which the M,A, C, SA, I, WXN & EE bits of
SCTLR_EL3 & SCTLR_EL1 are managed. The EE bit is cleared immediately after reset
in EL3. The I, A and SA bits are set next in EL3 and immediately upon entry in
S-EL1. These bits are no longer managed in the blX_arch_setup() functions. They
do not have to be saved and restored either. The M, WXN and optionally the C
bit are set in the enable_mmu_elX() function. This is done during both the warm
and cold boot paths.
Fixes ARM-software/tf-issues#226
Change-Id: Ie894d1a07b8697c116960d858cd138c50bc7a069
Achin Gupta [Thu, 26 Jun 2014 10:12:37 +0000 (11:12 +0100)]
Remove the concept of coherent stacks
This patch removes the allocation of memory for coherent stacks, associated
accessor function and some dead code which called the accessor function. It also
updates the porting guide to remove the concept and the motivation behind using
stacks allocated in coherent memory.
Fixes ARM-software/tf-issues#198
Change-Id: I00ff9a04f693a03df3627ba39727e3497263fc38
danh-arm [Fri, 25 Jul 2014 14:11:47 +0000 (15:11 +0100)]
Merge pull request #176 from danh-arm/jc/tf-issues/203-v3
Add support for printing version at runtime v3
Juan Castillo [Mon, 30 Jun 2014 10:41:46 +0000 (11:41 +0100)]
Add support for printing version at runtime
Print out Trusted Firmware version at runtime at each BL stage.
Message consists of TF version as defined statically in the Makefile
(e.g. v0.4), build mode (debug|release) and a customizable build
string:
1. By defining BUILD_STRING in command line when building TF
2. Default string is git commit ID
3. Empty if git meta-data is not available
Fixes ARM-software/tf-issues#203
Change-Id: I5c5ba438f66ab68810427d76b49c5b9177a957d6
Dan Handley [Fri, 25 Jul 2014 13:57:54 +0000 (14:57 +0100)]
Merge pull request #167 from jcastillo-arm/jc/tf-issues/217
FVP: Ensure system reset wake-up results in cold boot
Dan Handley [Fri, 25 Jul 2014 13:56:46 +0000 (14:56 +0100)]
Merge pull request #168 from sandrine-bailleux/sb/set-default-gic-arch
Define ARM_GIC_ARCH default value for all platforms
Dan Handley [Fri, 25 Jul 2014 13:54:38 +0000 (14:54 +0100)]
Merge pull request #174 from soby-mathew:sm/lean_printf_v2
Implement a leaner printf for Trusted Firmware
Soby Mathew [Thu, 12 Jun 2014 16:23:58 +0000 (17:23 +0100)]
Implement a leaner printf for Trusted Firmware
This patch implements a "tf_printf" which supports only the commonly
used format specifiers in Trusted Firmware, which uses a lot less
stack space than the stdlib printf function.
Fixes ARM-software/tf-issues#116
Change-Id: I7dfa1944f4c1e634b3e2d571f49afe02d109a351
Achin Gupta [Thu, 26 Jun 2014 08:58:52 +0000 (09:58 +0100)]
Remove coherent stack usage from the warm boot path
This patch uses stacks allocated in normal memory to enable the MMU early in the
warm boot path thus removing the dependency on stacks allocated in coherent
memory. Necessary cache and stack maintenance is performed when a cpu is being
powered down and up. This avoids any coherency issues that can arise from
reading speculatively fetched stale stack memory from another CPUs cache. These
changes affect the warm boot path in both BL3-1 and BL3-2.
The EL3 system registers responsible for preserving the MMU state are not saved
and restored any longer. Static values are used to program these system
registers when a cpu is powered on or resumed from suspend.
Change-Id: I8357e2eb5eb6c5f448492c5094b82b8927603784
Achin Gupta [Thu, 26 Jun 2014 07:59:07 +0000 (08:59 +0100)]
Make enablement of the MMU more flexible
This patch adds a 'flags' parameter to each exception level specific function
responsible for enabling the MMU. At present only a single flag which indicates
whether the data cache should also be enabled is implemented. Subsequent patches
will use this flag when enabling the MMU in the warm boot paths.
Change-Id: I0eafae1e678c9ecc604e680851093f1680e9cefa
Achin Gupta [Wed, 25 Jun 2014 18:26:22 +0000 (19:26 +0100)]
Remove coherent stack usage from the cold boot path
This patch reworks the cold boot path across the BL1, BL2, BL3-1 and BL3-2 boot
loader stages to not use stacks allocated in coherent memory for early platform
setup and enabling the MMU. Stacks allocated in normal memory are used instead.
Attributes for stack memory change from nGnRnE when the MMU is disabled to
Normal WBWA Inner-shareable when the MMU and data cache are enabled. It is
possible for the CPU to read stale stack memory after the MMU is enabled from
another CPUs cache. Hence, it is unsafe to turn on the MMU and data cache while
using normal stacks when multiple CPUs are a part of the same coherency
domain. It is safe to do so in the cold boot path as only the primary cpu
executes it. The secondary cpus are in a quiescent state.
This patch does not remove the allocation of coherent stack memory. That is done
in a subsequent patch.
Change-Id: I12c80b7c7ab23506d425c5b3a8a7de693498f830
Sandrine Bailleux [Thu, 17 Jul 2014 16:23:14 +0000 (17:23 +0100)]
Define ARM_GIC_ARCH default value for all platforms
The ARM_GIC_ARCH build option was supposed to default to 2 on all
platforms. However, the default value was set in the FVP makefile
so for all other platforms it wasn't even defined.
This patch moves the default value to the main Makefile. The platform
port can then override it if needed.
Change-Id: I8e2da1cce7ffa3ed18814bbdcbcf2578101f18a6
Juan Castillo [Fri, 11 Jul 2014 09:23:18 +0000 (10:23 +0100)]
FVP: Ensure system reset wake-up results in cold boot
platform_get_entrypoint() did not consider that a wakeup due to
System Reset Pin (by reading the power controller's PSYSR) requires
a cold boot. As a result, the code would execute the warm boot path
and eventually panic because entrypoint mailboxes are empty.
This patch ensures that the following wake-up reasons result in cold
boot:
- Cold Power-on
- System Reset Pin (includes reset by software)
Fixes ARM-software/tf-issues#217
Change-Id: I65ae0a0f7a46548b575900a5aac107d352b0e2cd
danh-arm [Fri, 11 Jul 2014 13:17:05 +0000 (14:17 +0100)]
Merge pull request #162 from jcastillo-arm/jc/tf-issues/194
Allow FP register context to be optional at build time
danh-arm [Fri, 11 Jul 2014 13:16:13 +0000 (14:16 +0100)]
Merge pull request #164 from sandrine-bailleux/sb/bl30-support-v2
Add support for BL3-0 image (v2)
danh-arm [Fri, 11 Jul 2014 10:19:27 +0000 (11:19 +0100)]
Merge pull request #163 from sandrine-bailleux/sb/tf-issue-117-v2
fvp: Reuse BL1 and BL2 memory through image overlaying (v2)
Sandrine Bailleux [Mon, 23 Jun 2014 16:00:23 +0000 (17:00 +0100)]
Update the documentation about the memory layout on FVP
Update the "Memory layout on FVP platforms" section in the Firmware
Design document to reflect the overlaying of BL1 and BL2 images
by BL3-1 and BL3-2.
Also update the Porting Guide document to mention the
BL31_PROGBITS_LIMIT and BL32_PROGBITS_LIMIT constants.
Change-Id: I0b23dae5b5b4490a01be7ff7aa80567cff34bda8
Sandrine Bailleux [Tue, 24 Jun 2014 13:19:36 +0000 (14:19 +0100)]
Add support for BL3-0 image
- Add support for loading a BL3-0 image in BL2. Information about
memory extents is populated by platform-specific code. Subsequent
handling of BL3-0 is also platform specific.
The BL2 main function has been broken down to improve readability.
The BL3-2 image is now loaded before the BL3-3 image to align with
the boot flow.
- Build system: Add support for specifying a BL3-0 image that will be
included into the FIP image.
- IO FIP driver: Add support for identifying a BL3-0 image inside a
FIP image.
- Update the documentation to reflect the above changes.
Change-Id: I067c184afd52ccaa86569f13664757570c86fc48
Sandrine Bailleux [Mon, 16 Jun 2014 15:12:27 +0000 (16:12 +0100)]
fvp: Reuse BL1 and BL2 memory through image overlaying
This patch re-organizes the memory layout on FVP as to give the
BL3-2 image as much memory as possible.
Considering these two facts:
- not all images need to live in memory at the same time. Once
in BL3-1, the memory used by BL1 and BL2 can be reclaimed.
- when BL2 loads the BL3-1 and BL3-2 images, it only considers the
PROGBITS sections of those 2 images. The memory occupied by the
NOBITS sections will be touched only at execution of the BL3-x
images;
Then it is possible to choose the different base addresses such that
the NOBITS sections of BL3-1 and BL3-2 overlay BL1 and BL2.
On FVP we choose to put:
- BL1 and BL3-1 at the top of the Trusted RAM, with BL3-1 NOBITS
sections overlaying BL1;
- BL3-2 at the bottom of the Trusted RAM, with its NOBITS sections
overlaying BL2;
This is illustrated by the following diagram:
0x0404_0000 ------------ ------------------
| BL1 | <= | BL3-1 NOBITS |
------------ <= ------------------
| | <= | BL3-1 PROGBITS |
------------ ------------------
| BL2 | <= | BL3-2 NOBITS |
------------ <= ------------------
| | <= | BL3-2 PROGBITS |
0x0400_0000 ------------ ------------------
New platform-specific constants have been introduced to easily check
at link time that BL3-1 and BL3-2 PROGBITS sections don't overwrite
BL1 and BL2. These are optional and the platform code is free to define
them or not. If not defined, the linker won't attempt to check
image overlaying.
Fixes ARM-software/tf-issues#117
Change-Id: I5981d1c3d66ee70eaac8bd052630c9ac6dd8b042
danh-arm [Thu, 10 Jul 2014 13:45:19 +0000 (14:45 +0100)]
Merge pull request #157 from sandrine-bailleux/sb/tf-issue-109
TF issue 109
danh-arm [Thu, 10 Jul 2014 13:44:24 +0000 (14:44 +0100)]
Merge pull request #146 from danh-arm/dh/refactor-fvp-gic
Refactor fvp config and gic code
danh-arm [Thu, 10 Jul 2014 13:43:48 +0000 (14:43 +0100)]
Merge pull request #161 from danh-arm/lm/calc-tcr-bits
Calculate TCR bits based on VA and PA
Juan Castillo [Wed, 25 Jun 2014 16:26:36 +0000 (17:26 +0100)]
Allow FP register context to be optional at build time
CTX_INCLUDE_FPREGS make variable allows us to include or exclude FP
registers from context structure, in case FP is not used by TSPD.
Fixes ARM-software/tf-issues#194
Change-Id: Iee41af382d691340c7ae21830ad1bbf95dad1f4b
Dan Handley [Fri, 20 Jun 2014 08:43:15 +0000 (09:43 +0100)]
Refactor fvp gic code to be a generic driver
Refactor the FVP gic code in plat/fvp/fvp_gic.c to be a generic ARM
GIC driver in drivers/arm/gic/arm_gic.c. Provide the platform
specific inputs in the arm_gic_setup() function so that the driver
has no explicit dependency on platform code.
Provide weak implementations of the platform interrupt controller
API in a new file, plat/common/plat_gic.c. These simply call through
to the ARM GIC driver.
Move the only remaining FVP GIC function, fvp_gic_init() to
plat/fvp/aarch64/fvp_common.c and remove plat/fvp/fvp_gic.c
Fixes ARM-software/tf-issues#182
Change-Id: Iea82fe095fad62dd33ba9efbddd48c57717edd21
Dan Handley [Fri, 20 Jun 2014 11:02:01 +0000 (12:02 +0100)]
Refactor fvp_config into common platform header
Changed the fvp_config array in fvp_common.c into a struct and
moved into a new optional common platform header,
include/plat/common/plat_config.h. Removed the config definitions
in fvp_def.h and updated all references to the platform config.
This makes the interface to the platform config cleaner and uses
a little less RAM.
Fixes ARM-software/tf-issues#180
Change-Id: I58dd7b3c150f24f7ee230a26fd57c827853ba803
Lin Ma [Fri, 27 Jun 2014 23:56:30 +0000 (16:56 -0700)]
Calculate TCR bits based on VA and PA
Currently the TCR bits are hardcoded in xlat_tables.c. In order to
map higher physical address into low virtual address, the TCR bits
need to be configured accordingly.
This patch is to save the max VA and PA and calculate the TCR.PS/IPS
and t0sz bits in init_xlat_tables function.
Change-Id: Ia7a58e5372b20200153057d457f4be5ddbb7dae4
Sandrine Bailleux [Fri, 13 Jun 2014 13:48:18 +0000 (14:48 +0100)]
fvp: Properly detect the location of BL1 R/W data
There was already a rudimentary mechanism to detect whether BL1
R/W data was loaded at the top or bottom of memory. Basically,
- either BL1 was loaded at the very end of the trusted RAM
- in all other cases BL1 was considered sitting at the bottom of
the memory and the memory usage structure was updated accordingly,
potentially resulting in critical memory waste.
For instance, if BL1 R/W base address was set to
(TZRAM_END - 4096 - bl1_size), it would virtually occupy the whole
memory.
This patch improves the mechanism to detect the location of BL1
to avoid such scenarios.
Change-Id: I224a9edf0fe8d34208545d84b28b63f2bb830d03
Sandrine Bailleux [Tue, 24 Jun 2014 13:02:34 +0000 (14:02 +0100)]
Remove concept of top/bottom image loading
This concept is no longer required since we now support loading of
images at fixed addresses only.
The image loader now automatically detects the position of the image
inside the current memory layout and updates the layout such that
memory fragmentation is minimised.
The 'attr' field of the meminfo data structure, which used to hold
the bottom/top loading information, has been removed. Also the 'next'
field has been removed as it wasn't used anywhere.
The 'init_bl2_mem_layout()' function has been moved out of common
code and put in BL1-specific code. It has also been renamed into
'bl1_init_bl2_mem_layout'.
Fixes ARM-software/tf-issues#109
Change-Id: I3f54642ce7b763d5ee3b047ad0ab59eabbcf916d
Andrew Thoelke [Fri, 27 Jun 2014 13:10:04 +0000 (14:10 +0100)]
Merge pull request #151 from vikramkanigiri/vk/t133-code-readability
Simplify entry point information generation code on FVP
Andrew Thoelke [Fri, 27 Jun 2014 11:53:26 +0000 (12:53 +0100)]
Merge pull request #155 from athoelke/at/support-foundation-v2.1
Support later revisions of the Foundation FVP
Andrew Thoelke [Thu, 26 Jun 2014 13:27:26 +0000 (14:27 +0100)]
Support later revisions of the Foundation FVP
The code in the FVP port which checks the platform type and
revision information in the SYS_ID register strictly supported
only the first revision of the Base and Foundation FVPs.
The current check also does not reflect the fact that the
board revision field is 'local' to the board type (HBI field).
Support for a new Foundation model is required now, and the
checking code is relaxed to allow execution (with a diagnostic)
on unrecognised revisions of the Base and Foundation FVP.
Change-Id: I7cd3519dfb56954aafe5f52ce1fcea0ee257ba9f
Andrew Thoelke [Thu, 26 Jun 2014 22:02:28 +0000 (23:02 +0100)]
Merge pull request #154 from athoelke/at/inline-mmio
Inline the mmio accessor functions
Andrew Thoelke [Thu, 26 Jun 2014 22:01:43 +0000 (23:01 +0100)]
Merge pull request #153 from athoelke/at/remove-psci-mpidr
Remove current CPU mpidr from PSCI common code
Andrew Thoelke [Mon, 9 Jun 2014 11:44:21 +0000 (12:44 +0100)]
Remove current CPU mpidr from PSCI common code
Many of the interfaces internal to PSCI pass the current CPU
MPIDR_EL1 value from function to function. This is not required,
and with inline access to the system registers is less efficient
than requiring the code to read that register whenever required.
This patch remove the mpidr parameter from the affected interfaces
and reduces code in FVP BL3-1 size by 160 bytes.
Change-Id: I16120a7c6944de37232016d7e109976540775602
danh-arm [Tue, 24 Jun 2014 15:48:31 +0000 (16:48 +0100)]
Merge pull request #152 from jcastillo-arm/jc/tf-issues/073-v2
Remove all checkpatch errors from codebase
danh-arm [Tue, 24 Jun 2014 15:48:18 +0000 (16:48 +0100)]
Merge pull request #150 from sandrine-bailleux/sb/fix-plat-print-gic-regs
fvp: Fix register name in 'plat_print_gic_regs' macro
danh-arm [Tue, 24 Jun 2014 15:44:37 +0000 (16:44 +0100)]
Merge pull request #149 from sandrine-bailleux/sb/warn-missing-include-dirs
Compile with '-Wmissing-include-dirs' flag
danh-arm [Tue, 24 Jun 2014 15:44:12 +0000 (16:44 +0100)]
Merge pull request #147 from athoelke/at/remove-bakery-mpidr
Remove calling CPU mpidr from bakery lock API
Andrew Thoelke [Tue, 24 Jun 2014 13:18:35 +0000 (14:18 +0100)]
Inline the mmio accessor functions
Making the simple mmio_read_*() and mmio_write_*() functions inline
saves 360 bytes of code in FVP release build.
Fixes ARM-software/tf-issues#210
Change-Id: I65134f9069f3b2d8821d882daaa5fdfe16355e2f
Juan Castillo [Fri, 13 Jun 2014 16:05:10 +0000 (17:05 +0100)]
Remove all checkpatch errors from codebase
Exclude stdlib files because they do not follow kernel code style.
Fixes ARM-software/tf-issues#73
Change-Id: I4cfafa38ab436f5ab22c277cb38f884346a267ab
Vikram Kanigiri [Mon, 2 Jun 2014 13:59:00 +0000 (14:59 +0100)]
Simplify entry point information generation code on FVP
This patch reworks FVP specific code responsible for determining
the entry point information for BL3-2 and BL3-3 stages when BL3-1
is configured as the reset handler.
Change-Id: Ia661ff0a6a44c7aabb0b6c1684b2e8d3642d11ec
Sandrine Bailleux [Tue, 3 Jun 2014 08:52:26 +0000 (09:52 +0100)]
fvp: Fix register name in 'plat_print_gic_regs' macro
The 'plat_print_gic_regs' macro was accessing the GICC_CTLR register
using the GICD_CTLR offset. This still generates the right code in
the end because GICD_CTLR == GICC_CTLR but this patch fixes it for
the logic of the code.
Change-Id: I7b17af50e587f07bec0e4c933e346088470c96f3
Andrew Thoelke [Mon, 9 Jun 2014 11:54:15 +0000 (12:54 +0100)]
Remove calling CPU mpidr from bakery lock API
The bakery lock code currently expects the calling code to pass
the MPIDR_EL1 of the current CPU.
This is not always done correctly. Also the change to provide
inline access to system registers makes it more efficient for the
bakery lock code to obtain the MPIDR_EL1 directly.
This change removes the mpidr parameter from the bakery lock
interface, and results in a code reduction of 160 bytes for the
ARM FVP port.
Fixes ARM-software/tf-issues#213
Change-Id: I7ec7bd117bcc9794a0d948990fcf3336a367d543
danh-arm [Mon, 23 Jun 2014 17:04:29 +0000 (18:04 +0100)]
Merge pull request #145 from athoelke/at/psci-memory-optimization-v2
PSCI memory optimizations (v2)
danh-arm [Mon, 23 Jun 2014 17:02:36 +0000 (18:02 +0100)]
Merge pull request #144 from athoelke/at/init-context-v2
Initialise CPU contexts from entry_point_info (v2)
Andrew Thoelke [Thu, 19 Jun 2014 23:36:14 +0000 (00:36 +0100)]
Correctly dimension the PSCI aff_map_node array
The array of affinity nodes is currently allocated for 32 entries
with the PSCI_NUM_AFFS value defined in psci.h. This is not enough
for large systems, and will substantially over allocate the array
for small systems.
This patch introduces an optional platform definition
PLATFORM_NUM_AFFS to platform_def.h. If defined this value is
used for PSCI_NUM_AFFS, otherwise a value of two times the number
of CPU cores is used.
The FVP port defines PLATFORM_NUM_AFFS to be 10 which saves
nearly 1.5KB of memory.
Fixes ARM-software/tf-issues#192
Change-Id: I68e30ac950de88cfbd02982ba882a18fb69c1445
Andrew Thoelke [Thu, 19 Jun 2014 23:38:03 +0000 (00:38 +0100)]
Eliminate psci_suspend_context array
psci_suspend_context is an array of cache-line aligned structures
containing the single power_state integer per cpu. This array is
the only structure indexed by the aff_map_node.data integer.
This patch saves 2KB of BL3-1 memory by placing the CPU
power_state value directly in the aff_map_node structure. As a
result, this value is now never cached and the cache clean when
writing the value is no longer required.
Fixes ARM-software/tf-issues#195
Change-Id: Ib4c70c8f79eed295ea541e7827977a588a19ef9b
Andrew Thoelke [Wed, 4 Jun 2014 20:10:52 +0000 (21:10 +0100)]
Initialise CPU contexts from entry_point_info
Consolidate all BL3-1 CPU context initialization for cold boot, PSCI
and SPDs into two functions:
* The first uses entry_point_info to initialize the relevant
cpu_context for first entry into a lower exception level on a CPU
* The second populates the EL1 and EL2 system registers as needed
from the cpu_context to ensure correct entry into the lower EL
This patch alters the way that BL3-1 determines which exception level
is used when first entering EL1 or EL2 during cold boot - this is now
fully determined by the SPSR value in the entry_point_info for BL3-3,
as set up by the platform code in BL2 (or otherwise provided to BL3-1).
In the situation that EL1 (or svc mode) is selected for a processor
that supports EL2, the context management code will now configure all
essential EL2 register state to ensure correct execution of EL1. This
allows the platform code to run non-secure EL1 payloads directly
without requiring a small EL2 stub or OS loader.
Change-Id: If9fbb2417e82d2226e47568203d5a369f39d3b0f
danh-arm [Mon, 23 Jun 2014 13:41:34 +0000 (14:41 +0100)]
Merge pull request #143 from athoelke/at/remove-nsram
Remove NSRAM from FVP memory map
danh-arm [Mon, 23 Jun 2014 13:40:20 +0000 (14:40 +0100)]
Merge pull request #140 from athoelke/at/psci_smc_handler
PSCI SMC handler improvements
Sandrine Bailleux [Mon, 23 Jun 2014 12:37:53 +0000 (13:37 +0100)]
Compile with '-Wmissing-include-dirs' flag
Add the '-Wmissing-include-dirs' flag to the CFLAGS and ASFLAGS
to make the build fail if the compiler or the assembler is given
a nonexistant directory in the list of directories to be searched
for header files.
Also remove 'include/bl1' and 'include/bl2' directories from the
search path for header files as they don't exist anymore.
Change-Id: I2475b78ba8b7b448b9d0afaa9ad975257f638b89
danh-arm [Mon, 23 Jun 2014 12:10:00 +0000 (13:10 +0100)]
Merge pull request #138 from athoelke/at/cpu-context
Move CPU context pointers into cpu_data
danh-arm [Mon, 23 Jun 2014 12:06:05 +0000 (13:06 +0100)]
Merge pull request #137 from athoelke/at/no-early-exceptions
Remove early_exceptions from BL3-1
danh-arm [Mon, 23 Jun 2014 11:47:47 +0000 (12:47 +0100)]
Merge pull request #136 from athoelke/at/cpu-data
Per-cpu data cache restructuring
danh-arm [Mon, 23 Jun 2014 11:43:58 +0000 (12:43 +0100)]
Merge pull request #142 from athoelke/at/fix-console_putc
Remove broken assertion in console_putc()
Andrew Thoelke [Fri, 20 Jun 2014 11:23:20 +0000 (12:23 +0100)]
Remove NSRAM from FVP memory map
This memory is not used by the FVP port and requires an additional
4KB translation table.
This patch removes the entry from the memory map and reduces the
number of allocated translation tables.
Fixes ARM-software/tf-issues#196
Change-Id: I5b959e4fe92f5f892ed127c40dbe6c85eed3ed72
Andrew Thoelke [Fri, 20 Jun 2014 10:12:39 +0000 (11:12 +0100)]
Remove broken assertion in console_putc()
The assertion in console_putc() would trigger a recursion that
exhausts the stack and eventually aborts.
This patch replaces the assertion with an error return if the
console has not been initialized yet.
Fixes ARM-software/tf-issues#208
Change-Id: I95f736ff215d69655eb5ba7ceac70dc1409d986a
danh-arm [Wed, 18 Jun 2014 17:34:31 +0000 (18:34 +0100)]
Merge pull request #135 from soby-mathew/sm/remove-reinit-of-timers
Remove re-initialisation of system timers after warm boot for FVP
Soby Mathew [Fri, 6 Jun 2014 09:18:52 +0000 (10:18 +0100)]
Remove re-initialisation of system timers after warm boot for FVP
This patch removes the reinitialisation of memory mapped system timer
registers after a warm boot for the FVP. The system timers in FVP are
in the 'Always ON' power domain which meant the reinitialisation was
redundant and it could have conflicted with the setup the normal
world has done.
The programming of CNTACR(x) and CNTNSAR, the system timer registers,
are removed from the warm boot path with this patch.
Fixes ARM-software/tf-issues#169
Change-Id: Ie982eb03d1836b15ef3cf1568de2ea68a08b443e
danh-arm [Tue, 17 Jun 2014 14:12:14 +0000 (15:12 +0100)]
Merge pull request #134 from jcastillo-arm/jc/tf-issues/179
Set correct value for SYS_ID_REV_SHIFT in FVP
Andrew Thoelke [Mon, 2 Jun 2014 11:38:12 +0000 (12:38 +0100)]
Remove early_exceptions from BL3-1
The crash reporting support and early initialisation of the
cpu_data allow the runtime_exception vectors to be used from
the start in BL3-1, removing the need for the additional
early_exception vectors and 2KB of code from BL3-1.
Change-Id: I5f8997dabbaafd8935a7455910b7db174a25d871
Andrew Thoelke [Mon, 2 Jun 2014 09:00:25 +0000 (10:00 +0100)]
Move CPU context pointers into cpu_data
Moving the context pointers for each CPU into the per-cpu data
allows for much more efficient access to the contexts for the
current CPU.
Change-Id: Id784e210d63cbdcddb44ac1591617ce668dbc29f
Andrew Thoelke [Mon, 2 Jun 2014 10:40:35 +0000 (11:40 +0100)]
Per-cpu data cache restructuring
This patch prepares the per-cpu pointer cache for wider use by:
* renaming the structure to cpu_data and placing in new header
* providing accessors for this CPU, or other CPUs
* splitting the initialization of the TPIDR pointer from the
initialization of the cpu_data content
* moving the crash stack initialization to a crash stack function
* setting the TPIDR pointer very early during boot
Change-Id: Icef9004ff88f8eb241d48c14be3158087d7e49a3
Juan Castillo [Fri, 13 Jun 2014 16:10:00 +0000 (17:10 +0100)]
Set correct value for SYS_ID_REV_SHIFT in FVP
According to documentation, the Rev field is located at bit 28 in
the V2M sysid register.
Fixes ARM-software/tf-issues#179
Change-Id: I2abb7bdc092ccd3f41f8962dc8d8d8e44e8dfdc3
danh-arm [Mon, 16 Jun 2014 11:45:08 +0000 (12:45 +0100)]
Merge pull request #133 from athoelke/at/crash-reporting-opt
Make the BL3-1 crash reporting optional
danh-arm [Mon, 16 Jun 2014 11:41:58 +0000 (12:41 +0100)]
Merge pull request #131 from athoelke/at/cm_get_context
Provide cm_get/set_context() for current CPU
danh-arm [Mon, 16 Jun 2014 11:41:48 +0000 (12:41 +0100)]
Merge pull request #130 from athoelke/at/inline-asm-sysreg-v2
Make system register functions inline assembly v2
danh-arm [Mon, 16 Jun 2014 10:58:21 +0000 (11:58 +0100)]
Merge pull request #128 from sandrine-bailleux/sb/make-load_image-ep-optional
Make the entry point argument optional in load_image()
achingupta [Thu, 12 Jun 2014 08:15:06 +0000 (09:15 +0100)]
Merge pull request #127 from sandrine-bailleux/sb/fix-pl011-fifo-polling
PL011: Fix a bug in the UART FIFO polling
achingupta [Thu, 12 Jun 2014 08:14:05 +0000 (09:14 +0100)]
Merge pull request #126 from sandrine-bailleux/sb/include-missing-hfile
Include 'platform_def.h' header file in 'crash_reporting.S'
achingupta [Thu, 12 Jun 2014 08:12:52 +0000 (09:12 +0100)]
Merge pull request #125 from sandrine-bailleux/sb/remove-bl2_el_change_mem_ptr
fvp: Remove unused 'bl2_el_change_mem_ptr' variable
Andrew Thoelke [Tue, 3 Jun 2014 10:50:53 +0000 (11:50 +0100)]
Make the BL3-1 crash reporting optional
This patch makes the console crash dump of processor register
state optional based on the CRASH_REPORTING make variable.
This defaults to only being enabled for DEBUG builds. This can
be overridden by setting a different value in the platform
makefile or on the make command line.
Change-Id: Icfa1b2d7ff0145cf0a85e8ad732f9cee7e7e993f
Andrew Thoelke [Wed, 14 May 2014 16:09:32 +0000 (17:09 +0100)]
Provide cm_get/set_context() for current CPU
All callers of cm_get_context() pass the calling CPU MPIDR to the
function. Providing a specialised version for the current
CPU results in a reduction in code size and better readability.
The current function has been renamed to cm_get_context_by_mpidr()
and the existing name is now used for the current-CPU version.
The same treatment has been done to cm_set_context(), although
only both forms are used at present in the PSCI and TSPD code.
Change-Id: I91cb0c2f7bfcb950a045dbd9ff7595751c0c0ffb
Andrew Thoelke [Tue, 10 Jun 2014 22:33:07 +0000 (23:33 +0100)]
Merge Pull Request #120 (patch 1) from 'linmaonly:lin_patch2'
Andrew Thoelke [Tue, 10 Jun 2014 15:37:37 +0000 (16:37 +0100)]
PSCI SMC handler improvements
The SMC handler for PSCI was not correctly handling calls from
secure states, or from AArch32.
This patch completes the handler implementation to correctly
detect secure callers and to clear the top bits in parameters from
AArch32 callers.
The patch also reorganises the switch statement to separate SMC64 and
SMC32 function IDs which allows the compiler to generate much smaller
code for the function.
Change-Id: I36b1ac81fb14253d257255d0477771d54fab0d11
Andrew Thoelke [Mon, 2 Jun 2014 14:44:43 +0000 (15:44 +0100)]
Make system register functions inline assembly
Replace the current out-of-line assembler implementations of
the system register and system instruction operations with
inline assembler.
This enables better compiler optimisation and code generation
when accessing system registers.
Fixes ARM-software/tf-issues#91
Change-Id: I149af3a94e1e5e5140a3e44b9abfc37ba2324476
Sandrine Bailleux [Thu, 29 May 2014 12:55:51 +0000 (13:55 +0100)]
fvp: Remove unused 'bl2_el_change_mem_ptr' variable
'bl2_el_change_mem_ptr' variable is a left over from the former
BL2/BL3-1 interface.
Change-Id: Ib0979c8e2809e103a41f9c5cc4afec7dd21ac9ab
Sandrine Bailleux [Wed, 28 May 2014 10:31:18 +0000 (11:31 +0100)]
Make the entry point argument optional in load_image()
There are cases where the entry point information is useless to the
caller, e.g. when an image just needs to be loaded in memory but won't
ever be executed.
This patch allows load_image() function to take a NULL pointer as the
entry point argument. In this case, it won't be populated.
Change-Id: Ie9394b054457706c6699926c5e0206e0c3851c56
Sandrine Bailleux [Mon, 2 Jun 2014 12:52:38 +0000 (13:52 +0100)]
PL011: Fix a bug in the UART FIFO polling
Before attempting to write a character, the PL011 driver polls
the PL011_UARTFR_TXFF bit to know whether the UART FIFO is full.
However, the comparison with 1 was incorrect because
PL011_UARTFR_TXFF is not at bit 0. This patch fixes it.
Change-Id: If78892345bbdc8a5e4ae4a1b7159753c609681b0
Sandrine Bailleux [Tue, 27 May 2014 14:46:07 +0000 (15:46 +0100)]
Include 'platform_def.h' header file in 'crash_reporting.S'
'crash_reporting.S' needs to include 'platform_def.h' to get the
definition of PLATFORM_CORE_COUNT.
Note: On FVP it was compiling because 'platform_def.h' gets included
through 'plat/fvp/include/plat_macros.S' but we don't want to rely on
that for other platforms.
Change-Id: I51e974776dd0f3bda10ad9849f5ef7b30c629833
Dan Handley [Tue, 3 Jun 2014 17:50:13 +0000 (18:50 +0100)]
Merge pull request #122 from 'danh-arm:dh/v0.4-docs'
Dan Handley [Tue, 3 Jun 2014 17:48:27 +0000 (18:48 +0100)]
Merge pull request #124 from 'danh-arm:sm/imf-documentation'