project/bcm63xx/u-boot.git
7 years agofix: phy: marvell: cp110: sata: update analog parameters according to latest ETP
Igal Liberman [Mon, 24 Apr 2017 15:45:26 +0000 (18:45 +0300)]
fix: phy: marvell: cp110: sata: update analog parameters according to latest ETP

Add SATA analog parameters initialization values according to
latest ETP.

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Igal Liberman <igall@marvell.com>
Reviewed-by: Stefan Roese <sr@denx.de>
7 years agofix: phy: marvell: cp110: fix the KR/SFI line 4 selector
Stefan Roese [Mon, 24 Apr 2017 15:45:25 +0000 (18:45 +0300)]
fix: phy: marvell: cp110: fix the KR/SFI line 4 selector

This patch fixes the following:
1. KR/SFI on lane #4 mux selector is 0x2 and not 0x1
2. Comment typo

Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Igal Liberman <igall@marvell.com>
Reviewed-by: Stefan Roese <sr@denx.de>
7 years agophy: marvell: add IGNORE COMPHY type
Stefan Roese [Mon, 24 Apr 2017 15:45:24 +0000 (18:45 +0300)]
phy: marvell: add IGNORE COMPHY type

This type tells u-boot to preserve the COMPHY settings as is
it is usefull in situations where the COMPHY was initialized by
earlier firmware.
Note that IGNORE is different from UNCONNECTED since setting
UNCONNECTED type will disconnect the COMPHY in the COMPHY MUX
which is a desired behaviour

Signed-off-by: Yehuda Yitschak <yehuday@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Igal Liberman <igall@marvell.com>
Reviewed-by: Stefan Roese <sr@denx.de>
7 years agophy: marvell: cp110: update utmi phy connection type
Stefan Roese [Mon, 24 Apr 2017 15:45:23 +0000 (18:45 +0300)]
phy: marvell: cp110: update utmi phy connection type

UTMI_PHY_TO_USB_HOST was used in USB3 UTMI dts node only, but there will
be USB2 UTMI dts node for some SoCs that have got USB2 controller, so rename
TO_USB_HOST to TO_USB3_HOST to distinguish TO_USB2_HOST in later on patches.

Signed-off-by: zachary <zhangzg@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Igal Liberman <igall@marvell.com>
Reviewed-by: Stefan Roese <sr@denx.de>
7 years agophy: marvell: cp110: add support for end point configuration
Stefan Roese [Mon, 24 Apr 2017 15:45:22 +0000 (18:45 +0300)]
phy: marvell: cp110: add support for end point configuration

The serdes was always configured in root complex mode.
this patch add new entry in device tree (per serdes)
which indicates whether the serdes is in end point mode.
if so, it skips the root complex configuration.

Signed-off-by: Haim Boot <hayim@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Igal Liberman <igall@marvell.com>
Reviewed-by: Stefan Roese <sr@denx.de>
7 years agophy: marvell: Replace PHY_TYPE_KR with PHY_TYPE_SFI
Stefan Roese [Mon, 24 Apr 2017 15:45:21 +0000 (18:45 +0300)]
phy: marvell: Replace PHY_TYPE_KR with PHY_TYPE_SFI

Use correct naming as done in the latest Marvell U-Boot version as well.

Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Igal Liberman <igall@marvell.com>
Reviewed-by: Stefan Roese <sr@denx.de>
7 years agofix: mvebu_ comphy: Update COMPHY sequence number
Konstantin Porotchkin [Wed, 19 Apr 2017 10:37:59 +0000 (13:37 +0300)]
fix: mvebu_ comphy: Update COMPHY sequence number

Use local static counter for maintaining the COMPHY chip-ID
upon its initialization.
The dev->seq originally used as the COMPHY chip-ID depends
on the device tree scan order and produces wrong results
that breaks the deficated PHYs init flow, which in turn
breaks the USB support.

Change-Id: I4e3f7ec36590a7f95dc94d9269a3c47fb708c4a9
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Igal Liberman <igall@marvell.com>
Cc: Stefan Chulski <stefanc@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Reviewed-by: Stefan Roese <sr@denx.de>
7 years agoarm: mvebu: Minor fixes in the AXP / A38x SERDES code
Uwe Kleine-König [Fri, 7 Apr 2017 10:56:26 +0000 (12:56 +0200)]
arm: mvebu: Minor fixes in the AXP / A38x SERDES code

- Fix spelling error of SERDES_VERSION
- Remove superfluous definition of this macro
- Remove unnecessary include of i2c.h

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Stefan Roese <sr@denx.de>
7 years agoarm64: mvebu: a8k: Add NAND configuration parameters
Konstantin Porotchkin [Wed, 5 Apr 2017 15:22:33 +0000 (18:22 +0300)]
arm64: mvebu: a8k: Add NAND configuration parameters

Add NAND configuration parameters to A8K shared config file.
Add defconfig for db-88f7040 board with boot from NAND setup.

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Igal Liberman <igall@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Reviewed-by: Stefan Roese <sr@denx.de>
7 years agoarm64: a8k: dts: Add support for NAND devices on A8K platform
Konstantin Porotchkin [Wed, 5 Apr 2017 15:22:32 +0000 (18:22 +0300)]
arm64: a8k: dts: Add support for NAND devices on A8K platform

Add NAND to CP master device tree. Add armada-7040-db-nand
device tree for the board configured with NAND boot device.
Add comment about boot device ID to armada-7040-db DTS.

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Igal Liberman <igall@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Reviewed-by: Stefan Roese <sr@denx.de>
7 years agoarm64: mvebu: a8k: Add support for NAND clock get
Konstantin Porotchkin [Wed, 5 Apr 2017 15:22:31 +0000 (18:22 +0300)]
arm64: mvebu: a8k: Add support for NAND clock get

Implement mvebu_get_nand_clock call for A8K family.
This function is used by PXA3XX NAND driver.

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Igal Liberman <igall@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Reviewed-by: Stefan Roese <sr@denx.de>
7 years agoarm64: mvebu: Trigger PCI devices scan at early init stage
Konstantin Porotchkin [Wed, 5 Apr 2017 14:42:33 +0000 (17:42 +0300)]
arm64: mvebu: Trigger PCI devices scan at early init stage

Add PCIe initialization at early init stage.
This operation has a side effect of detecting all PCIe
plug-in cards, so the operator is not obligated to issue
"pci enum" command though CLI for this purpose.

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Igal Liberman <igall@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Reviewed-by: Stefan Roese <sr@denx.de>
7 years agomvebu: dts: a80x0: Sync the DB DTS with standard config A
Konstantin Porotchkin [Tue, 28 Mar 2017 15:36:35 +0000 (18:36 +0300)]
mvebu: dts: a80x0: Sync the DB DTS with standard config A

Sync the default configuration of Armada-8040-DB with
Marvell u-boot-2015  standard configuration "A" for the same board.
The standard configuration "A" enables 2 PCIe slots on CP0
and 3 PCIe slots on CP1.
This is the main configuration used for u-boot  and Linux tests.
This patch also re-arranges the DTS file entries by grouping
all nodes related to CP0 and CP1.

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Igal Liberman <igall@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Reviewed-by: Stefan Roese <sr@denx.de>
7 years agofix: mvebu: pcie_dw: Allow probing empty PCIe slots
Konstantin Porotchkin [Tue, 28 Mar 2017 15:36:34 +0000 (18:36 +0300)]
fix: mvebu: pcie_dw: Allow probing empty PCIe slots

This patch allows probing all PCIe nodes defined in DTS
even if there no device connected to such node (no link).
Without this fix the driver returns -ENODEV when the PCIe
link is down. As result the pci_init function stops
scanning bus on first empty PCIe slot and all devices
located in higher numbered buses are not discovered.

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Igal Liberman <igall@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Reviewed-by: Stefan Roese <sr@denx.de>
7 years agonet: mvpp2: Add remove function that is called before the OS is started
Stefan Roese [Thu, 23 Mar 2017 16:01:59 +0000 (17:01 +0100)]
net: mvpp2: Add remove function that is called before the OS is started

This patch adds a remove function to the mvpp2 ethernet driver which is
called before the OS is started, doing:

- Allocate the used buffers back from the buffer manager
- Stop the BM activity

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Stefan Chulski <stefanc@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
7 years agoMerge branch 'next' of git://git.denx.de/u-boot-spi
Tom Rini [Mon, 8 May 2017 19:44:52 +0000 (15:44 -0400)]
Merge branch 'next' of git://git.denx.de/u-boot-spi

7 years agoMerge branch 'master' of git://git.denx.de/u-boot-sunxi
Tom Rini [Mon, 8 May 2017 19:44:44 +0000 (15:44 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-sunxi

7 years agoARM: keystone2: Add support for getting external clock dynamically
Lokesh Vutla [Wed, 3 May 2017 11:28:26 +0000 (16:58 +0530)]
ARM: keystone2: Add support for getting external clock dynamically

One some keystone2 platforms like K2G ICE, there is an option
to switch between 24MHz or 25MHz as sysclk. But the existing
driver assumes it is always 24MHz. Add support for getting
all reference clocks dynamically by reading boot pins.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
7 years agoARM: k2g: Add support for dynamic programming of PLL based on SYSCLK
Lokesh Vutla [Wed, 3 May 2017 11:28:25 +0000 (16:58 +0530)]
ARM: k2g: Add support for dynamic programming of PLL based on SYSCLK

K2G supports various sysclk frequencies which can be
determined using sysboot pins. PLLs should be configured
based on this sysclock frequency. Add PLL configurations
for all supported sysclk frequencies.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
7 years agoconfigs: ks2: Enable TI_COMMON_CMD_OPTIONS
Lokesh Vutla [Thu, 27 Apr 2017 10:14:03 +0000 (15:44 +0530)]
configs: ks2: Enable TI_COMMON_CMD_OPTIONS

Enable TI_COMMON_CMD_OPTIONS on all keystone2 platforms.
Also sync with savedefconfig.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
7 years agoconfigs: dra7xx: Enable TI_COMMON_CMD_OPTIONS
Lokesh Vutla [Thu, 27 Apr 2017 10:14:02 +0000 (15:44 +0530)]
configs: dra7xx: Enable TI_COMMON_CMD_OPTIONS

Enable TI_COMMON_CMD_OPTIONS on all dra7xx platforms.
Also sync with savedefconfig.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
7 years agoconfigs: am57xx: Enable TI_COMMON_CMD_OPTIONS
Lokesh Vutla [Thu, 27 Apr 2017 10:14:01 +0000 (15:44 +0530)]
configs: am57xx: Enable TI_COMMON_CMD_OPTIONS

Enable TI_COMMON_CMD_OPTIONS on all am57xx platforms.
Also sync with savedefconfig

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
7 years agoconfigs: am43xx: Enable TI_COMMON_CMD_OPTIONS
Lokesh Vutla [Thu, 27 Apr 2017 10:14:00 +0000 (15:44 +0530)]
configs: am43xx: Enable TI_COMMON_CMD_OPTIONS

Enable TI_COMMON_CMD_OPTIONS on all am43xx platforms.
Also sync with savedefconfig.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
7 years agoconfigs: am335x: Enable TI_COMMON_CMD_OPTIONS
Lokesh Vutla [Thu, 27 Apr 2017 10:13:59 +0000 (15:43 +0530)]
configs: am335x: Enable TI_COMMON_CMD_OPTIONS

Enable TI_COMMON_CMD_OPTIONS on all am335x platforms.
Also sync with savedefconfig.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
[trini: Re-sync, add in boneblack*, evm_hs_{norboot,spiboot,usbspl} configs]
Signed-off-by: Tom Rini <trini@konsulko.com>
7 years agoboard: ti: Define Kconfig symbol for common cmd options
Lokesh Vutla [Thu, 27 Apr 2017 10:13:58 +0000 (15:43 +0530)]
board: ti: Define Kconfig symbol for common cmd options

Instead of defining command options in every defconfig,
define a common Kconfig symbol that consolidates all command
options that are supported by any TI platform. Also use imply
keyword so that that specific option can be disabled if
not required.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
7 years agoAdd ARM errata workaround 852421 and 852423 for Cortex-A17
Nisal Menuka [Wed, 26 Apr 2017 21:18:01 +0000 (16:18 -0500)]
Add ARM errata workaround 852421 and 852423 for Cortex-A17

ARM errata 852421 and 852423 applies to r1p0, r1p1 and r1p2
revisions of Cortex-A17 processors. These workarounds
exist in Linux kernel and I thought it would be better
to add them in to U-Boot.

Signed-off-by: Nisal Menuka <nisalmenuka23@gmail.com>
7 years agoaspeed: Cleanup ast2500-u-boot.dtsi Device Tree
maxims@google.com [Mon, 17 Apr 2017 19:00:34 +0000 (12:00 -0700)]
aspeed: Cleanup ast2500-u-boot.dtsi Device Tree

Remove unnecessary apb and ahb nodes and just override necessary
nodes/values.

Signed-off-by: Maxim Sloyko <maxims@google.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agoaspeed: Refactor SCU to use consistent mask & shift
maxims@google.com [Mon, 17 Apr 2017 19:00:33 +0000 (12:00 -0700)]
aspeed: Refactor SCU to use consistent mask & shift

Refactor SCU header to use consistent Mask & Shift values.
Now, consistently, to read value from SCU register, mask needs
to be applied before shift.

Signed-off-by: Maxim Sloyko <maxims@google.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agoaspeed: Add support for Clocks needed by MACs
maxims@google.com [Mon, 17 Apr 2017 19:00:32 +0000 (12:00 -0700)]
aspeed: Add support for Clocks needed by MACs

Add support for clocks needed by MACs to ast2500 clock driver.
The clocks are D2-PLL, which is used by both MACs and PCLK_MAC1 and
PCLK_MAC2 for MAC1 and MAC2 respectively.

The rate of D2-PLL is hardcoded to 250MHz -- the value used in Aspeed
SDK. It is not entirely clear from the datasheet how this clock is used
by MACs, so not clear if the rate would ever need to be different. So,
for now, hardcoding it is probably safer.

The rate of PCLK_MAC{1,2} is chosen based on MAC speed selected through
hardware strapping.

So, the network driver would only need to enable these clocks, no need
to configure the rate.

Signed-off-by: Maxim Sloyko <maxims@google.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agoaspeed: Enable I2C in EVB defconfig
maxims@google.com [Mon, 17 Apr 2017 19:00:31 +0000 (12:00 -0700)]
aspeed: Enable I2C in EVB defconfig

Enable I2C driver in ast2500 Eval Board defconfig.
Also enable i2c command.

Signed-off-by: Maxim Sloyko <maxims@google.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agoaspeed: Add I2C Driver
maxims@google.com [Mon, 17 Apr 2017 19:00:30 +0000 (12:00 -0700)]
aspeed: Add I2C Driver

Add Device Model based I2C driver for ast2500/ast2400 SoCs.
The driver is very limited, it only supports master mode and
synchronous byte-by-byte reads/writes, no DMA or Pool Buffers.

Signed-off-by: Maxim Sloyko <maxims@google.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Heiko Schocher <hs@denx.de>
7 years agoaspeed: Add P-Bus clock in ast2500 clock driver
maxims@google.com [Mon, 17 Apr 2017 19:00:29 +0000 (12:00 -0700)]
aspeed: Add P-Bus clock in ast2500 clock driver

Add P-Bus Clock support to ast2500 clock driver.
This is the clock used by I2C devices.

Signed-off-by: Maxim Sloyko <maxims@google.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agoaspeed: Enable Pinctrl Driver in AST2500 EVB
maxims@google.com [Mon, 17 Apr 2017 19:00:28 +0000 (12:00 -0700)]
aspeed: Enable Pinctrl Driver in AST2500 EVB

Enable Pinctrl Driver in AST2500 Eval Board's defconfig

Signed-off-by: Maxim Sloyko <maxims@google.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agoaspeed: AST2500 Pinctrl Driver
maxims@google.com [Mon, 17 Apr 2017 19:00:27 +0000 (12:00 -0700)]
aspeed: AST2500 Pinctrl Driver

This driver uses Generic Pinctrl framework and is compatible with
the Linux driver for ast2500: it uses the same device tree
configuration.

Not all pins are supported by the driver at the moment, so it actually
compatible with ast2400. In general, however, there are differences that
in the future would be easier to maintain separately.

Signed-off-by: Maxim Sloyko <maxims@google.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agoaspeed: Refactor AST2500 RAM Driver and Sysreset Driver
maxims@google.com [Mon, 17 Apr 2017 19:00:26 +0000 (12:00 -0700)]
aspeed: Refactor AST2500 RAM Driver and Sysreset Driver

This change switches all existing users of ast2500 Watchdog to Driver
Model based Watchdog driver.

To perform system reset Sysreset Driver uses first Watchdog device found
via uclass_first_device call. Since the system is going to be reset
anyway it does not make much difference which watchdog is used.

Instead of using Watchdog to reset itself, SDRAM driver now uses Reset
driver to do that.

These were the only users of the old Watchdog API, so that API is
removed.

This all is done in one change to avoid having to maintain dual API for
watchdog in between.

Signed-off-by: Maxim Sloyko <maxims@google.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agoaspeed: Device Tree configuration for Reset Driver
maxims@google.com [Mon, 17 Apr 2017 19:00:25 +0000 (12:00 -0700)]
aspeed: Device Tree configuration for Reset Driver

Add Reset Driver configuration to ast2500 SoC Device Tree and bindings
for various reset signals

Signed-off-by: Maxim Sloyko <maxims@google.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agoaspeed: Reset Driver
maxims@google.com [Mon, 17 Apr 2017 19:00:24 +0000 (12:00 -0700)]
aspeed: Reset Driver

Add Reset Driver for ast2500 SoC. This driver uses Watchdog Timer to
perform resets and thus depends on it. The actual Watchdog device used
needs to be configured in Device Tree using "aspeed,wdt" property, which
must be WDT phandle, for example:

rst: reset-controller {
    compatible = "aspeed,ast2500-reset";
    aspeed,wdt = <&wdt1>;
}

Signed-off-by: Maxim Sloyko <maxims@google.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agoaspeed: Make SCU lock/unlock functions part of SCU API
maxims@google.com [Mon, 17 Apr 2017 19:00:23 +0000 (12:00 -0700)]
aspeed: Make SCU lock/unlock functions part of SCU API

Make functions for locking and unlocking SCU part of SCU API.
Many drivers need to modify settings in SCU and thus need to unlock it
first. This change makes it possible.

Signed-off-by: Maxim Sloyko <maxims@google.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agoaspeed: Watchdog Timer Driver
maxims@google.com [Mon, 17 Apr 2017 19:00:22 +0000 (12:00 -0700)]
aspeed: Watchdog Timer Driver

This driver supports ast2500 and ast2400 SoCs.
Only ast2500 supports reset_mask and thus the option of resettting
individual peripherals using WDT.

Signed-off-by: Maxim Sloyko <maxims@google.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agodm: Simple Watchdog uclass
maxims@google.com [Mon, 17 Apr 2017 19:00:21 +0000 (12:00 -0700)]
dm: Simple Watchdog uclass

This is a simple uclass for Watchdog Timers. It has four operations:
start, restart, reset, stop. Drivers must implement start, restart and
stop operations, while implementing reset is optional: It's default
implementation expires watchdog timer in one clock tick.

Signed-off-by: Maxim Sloyko <maxims@google.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agoaspeed: Update ast2500 Device Tree
maxims@google.com [Mon, 17 Apr 2017 19:00:20 +0000 (12:00 -0700)]
aspeed: Update ast2500 Device Tree

Pull in the Device Tree for ast2500 from the mainline Linux kernel.
The file is copied from
https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi

Signed-off-by: Maxim Sloyko <maxims@google.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agoARM: DT: STM32F746: add u-boot, dm-pre-reloc property to sub nodes
Vikas Manocha [Wed, 12 Apr 2017 21:16:36 +0000 (14:16 -0700)]
ARM: DT: STM32F746: add u-boot, dm-pre-reloc property to sub nodes

This patch is required for correct SPL device tree creation by fdtgrep
as fdtgrep looks for u-boot,dm-pre-reloc property of the node to include
it in the spl device tree.

Not adding it in these subnodes ignores the pin muxing of peripherals
which is almost always in the subnodes.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
7 years agoREADME: remove CONFIG_CMD_DATE
Chris Packham [Tue, 2 May 2017 09:30:49 +0000 (21:30 +1200)]
README: remove CONFIG_CMD_DATE

CONFIG_CMD_DATE was recently moved to Kconfig. Remove the now duplicate
description of the option.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agotools: moveconfig: cleanup README entires
Chris Packham [Tue, 2 May 2017 09:30:48 +0000 (21:30 +1200)]
tools: moveconfig: cleanup README entires

The Kconfig description replaces the description in the README file so
as options are migrated they can be removed from the README.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agotools: moveconfig: cleanup whitelist entries
Chris Packham [Tue, 2 May 2017 09:30:47 +0000 (21:30 +1200)]
tools: moveconfig: cleanup whitelist entries

After moving to KConfig and removing from all headers options should be
removed from config_whitelist.txt so the build starts complaining if
someone adds them back.

Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agotools: moveconfig: extract helper function for user confirmation
Chris Packham [Tue, 2 May 2017 09:30:46 +0000 (21:30 +1200)]
tools: moveconfig: extract helper function for user confirmation

Avoid repetitive code dealing with asking the user for confirmation.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agortc: Add DM support to ds1307
Chris Packham [Sat, 29 Apr 2017 03:20:29 +0000 (15:20 +1200)]
rtc: Add DM support to ds1307

Add an implementation of the ds1307 driver that uses the driver model
i2c APIs.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agoigep003x: Add netboot support
Pau Pajuelo [Sat, 1 Apr 2017 15:19:43 +0000 (17:19 +0200)]
igep003x: Add netboot support

netboot allows to boot an external image using TFTP and NFS protocols

Signed-off-by: Pau Pajuelo <ppajuelo@iseebcn.com>
Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Tested-by: Pau Pajuelo <ppajuel@gmail.com>
7 years agoigep003x: Add support for IGEP SMARC AM335x
Pau Pajuelo [Sat, 1 Apr 2017 15:18:40 +0000 (17:18 +0200)]
igep003x: Add support for IGEP SMARC AM335x

The IGEP SMARC AM335x is an industrial processor module with
following highlights:

  o AM3352 TI processor (Up to AM3359)
  o Cortex-A8 ARM CPU
  o SMARC form factor module
  o Up to 512 MB DDR3 SDRAM / 512 MB FLASH
  o WiFi a/b/g/n and Bluetooth v4.0 on-board
  o Ethernet 10/100/1000 Mbps and 10/100 Mbps controller on-board
  o JTAG debug connector available
  o Designed for industrial range purposes

Signed-off-by: Pau Pajuelo <ppajuelo@iseebcn.com>
Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Tested-by: Pau Pajuelo <ppajuel@gmail.com>
7 years agoigep003x: UBIize
Ladislav Michl [Sat, 1 Apr 2017 15:17:57 +0000 (17:17 +0200)]
igep003x: UBIize

Convert IGEP board to use UBI volumes for U-Boot, its environment and
kernel. With exception of first four sectors read by SoC BootROM whole
NAND is UBI managed.

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Reviewed-by: Heiko Schocher<hs@denx.de>
Tested-by: Pau Pajuelo <ppajuel@gmail.com>
7 years agoigep0033: Rename to igep003x
Ladislav Michl [Sat, 1 Apr 2017 15:17:16 +0000 (17:17 +0200)]
igep0033: Rename to igep003x

Rename igep0033 to igep003x as IGEP SMARC AM335x module (igep0034)
can use the same source files.

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Tested-by: Pau Pajuelo <ppajuel@gmail.com>
7 years agomtd: nand: Consolidate nand spl loaders implementation
Ladislav Michl [Sun, 16 Apr 2017 13:31:59 +0000 (15:31 +0200)]
mtd: nand: Consolidate nand spl loaders implementation

nand_spl_load_image implementation was copied over into three
different drivers and now with nand_spl_read_block used for
ubispl situation gets even worse. For now use least intrusive
solution and #include the same implementation to nand drivers.

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Tested-by: Pau Pajuelo <ppajuel@gmail.com>
7 years agoARM: am33xx: define BOOT_DEVICE_ONENAND
Ladislav Michl [Sat, 1 Apr 2017 15:15:04 +0000 (17:15 +0200)]
ARM: am33xx: define BOOT_DEVICE_ONENAND

am33xx does not support OneNAND, but we need this define anyway
to let UBI SPL code compile.

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Tested-by: Pau Pajuelo <ppajuel@gmail.com>
7 years agoARM: am33xx: fix typo in spl.h
Ladislav Michl [Sat, 1 Apr 2017 15:14:28 +0000 (17:14 +0200)]
ARM: am33xx: fix typo in spl.h

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Tested-by: Pau Pajuelo <ppajuel@gmail.com>
7 years agostm32f7: remove not needed configuration from board config
Vikas Manocha [Mon, 10 Apr 2017 22:03:07 +0000 (15:03 -0700)]
stm32f7: remove not needed configuration from board config

This patch removes:
- CONFIG_CMD_MEM: enabled by default
- CONFIG_DESIGNWARE_ETH : not being used anywhere.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
cc: Christophe KERELLO <christophe.kerello@st.com>

7 years agostm32f7: add support for stm32f769 disco board
Vikas Manocha [Mon, 10 Apr 2017 22:03:06 +0000 (15:03 -0700)]
stm32f7: add support for stm32f769 disco board

This board support stm32f7 family device stm32f769-I with 2MB internal Flash &
512KB RAM.
STM32F769 lines offer the performance of the Cortex-M7 core (with double
precision floating point unit) running up to 216 MHz.

To compile for stm32f769 board, use same defconfig as stm32f746-disco,
the only difference is to pass "DEVICE_TREE=stm32f769-disco".

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
cc: Christophe KERELLO <christophe.kerello@st.com>

7 years agostm32f7: move board specific pin muxing to dts
Vikas Manocha [Mon, 10 Apr 2017 22:03:05 +0000 (15:03 -0700)]
stm32f7: move board specific pin muxing to dts

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
cc: Christophe KERELLO <christophe.kerello@st.com>

7 years agostm32f7: increase the max no of pin configuration to 70
Vikas Manocha [Mon, 10 Apr 2017 22:03:04 +0000 (15:03 -0700)]
stm32f7: increase the max no of pin configuration to 70

The number of pins to be configured could be more than 50 e.g. in case
of sdram controller, there are about 56 pins (32 data lines, 12 address
& some control signals).

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
cc: Christophe KERELLO <christophe.kerello@st.com>

7 years agostm32f7: sdram: correct sdram configuration as per micron sdram
Vikas Manocha [Mon, 10 Apr 2017 22:03:03 +0000 (15:03 -0700)]
stm32f7: sdram: correct sdram configuration as per micron sdram

Actually the sdram memory on stm32f746 discovery board is micron part
MT48LC_4M32_B2B5_6A. This patch does the modification required in the
device tree node & driver for the same.

Also we are passing here all the timing parameters in terms of clock
cycles, so no need to convert time(ns or ms) to cycles.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
cc: Christophe KERELLO <christophe.kerello@st.com>

7 years agostm32f7: enable board info read from device tree
Vikas Manocha [Mon, 10 Apr 2017 22:03:02 +0000 (15:03 -0700)]
stm32f7: enable board info read from device tree

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
cc: Christophe KERELLO <christophe.kerello@st.com>

7 years agostm32f7: stm32f746-disco: read memory info from device tree
Vikas Manocha [Mon, 10 Apr 2017 22:03:01 +0000 (15:03 -0700)]
stm32f7: stm32f746-disco: read memory info from device tree

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
cc: Christophe KERELLO <christophe.kerello@st.com>

7 years agostm32f746: to switch on user LED1 & read user button
Vikas Manocha [Mon, 10 Apr 2017 22:03:00 +0000 (15:03 -0700)]
stm32f746: to switch on user LED1 & read user button

All discovery boards have one user button & one user LED. Here we are
just reading the button status & switching ON the user LED.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
cc: Christophe KERELLO <christophe.kerello@st.com>

7 years agostm32f7: use stm32f7 gpio driver supporting driver model
Vikas Manocha [Mon, 10 Apr 2017 22:02:59 +0000 (15:02 -0700)]
stm32f7: use stm32f7 gpio driver supporting driver model

With this gpio driver supporting DM, there is no need to enable clocks
for different gpios (for pin muxing) in the board specific code.

Need to increase the allocatable area required before relocation from 0x400 to
0xC00 becuase of 10 new gpio devices(& new gpio class) added in device tree.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
cc: Christophe KERELLO <christophe.kerello@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agoARM: DT: stm32f7: add gpio device tree nodes
Vikas Manocha [Mon, 10 Apr 2017 22:02:58 +0000 (15:02 -0700)]
ARM: DT: stm32f7: add gpio device tree nodes

Also created alias for gpios for stm32f7 discovery board. Based on these
aliases, it would be possible to get gpio devices by sequence.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
cc: Christophe KERELLO <christophe.kerello@st.com>

7 years agodm: gpio: Add driver for stm32f7 gpio controller
Vikas Manocha [Mon, 10 Apr 2017 22:02:57 +0000 (15:02 -0700)]
dm: gpio: Add driver for stm32f7 gpio controller

This patch adds gpio driver supporting driver model for stm32f7 gpio.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Christophe KERELLO <christophe.kerello@st.com>
[trini: Add depends on STM32]
Signed-off-by: Tom Rini <trini@konsulko.com>
7 years agostm32f7: sdram: use sdram device tree node to configure sdram controller
Vikas Manocha [Mon, 10 Apr 2017 22:02:56 +0000 (15:02 -0700)]
stm32f7: sdram: use sdram device tree node to configure sdram controller

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
cc: Christophe KERELLO <christophe.kerello@st.com>

7 years agostm32f7: use clock driver to enable sdram controller clock
Vikas Manocha [Mon, 10 Apr 2017 22:02:55 +0000 (15:02 -0700)]
stm32f7: use clock driver to enable sdram controller clock

This patch also removes the sdram/fmc clock enable from board specific
code.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
cc: Christophe KERELLO <christophe.kerello@st.com>

7 years agostm32f7: use driver model for sdram initialization
Vikas Manocha [Mon, 10 Apr 2017 22:02:54 +0000 (15:02 -0700)]
stm32f7: use driver model for sdram initialization

As driver model takes care of pin control configuraion, this patch also
removes the sdram/fmc pin configuration.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
cc: Christophe KERELLO <christophe.kerello@st.com>

7 years agoARM: DT: stm32f7: add sdram pin contol node
Vikas Manocha [Mon, 10 Apr 2017 22:02:53 +0000 (15:02 -0700)]
ARM: DT: stm32f7: add sdram pin contol node

Also added DT binding doc for stm32 fmc(flexible memory controller).

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
cc: Christophe KERELLO <christophe.kerello@st.com>

7 years agostm32f7: dm: add driver model support for sdram
Vikas Manocha [Mon, 10 Apr 2017 22:02:52 +0000 (15:02 -0700)]
stm32f7: dm: add driver model support for sdram

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
cc: Christophe KERELLO <christophe.kerello@st.com>

7 years agostm32f7: sdram: move sdram driver code to ram drivers area
Vikas Manocha [Mon, 10 Apr 2017 22:02:51 +0000 (15:02 -0700)]
stm32f7: sdram: move sdram driver code to ram drivers area

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
cc: Christophe KERELLO <christophe.kerello@st.com>

7 years agostm32f7: use clock driver to enable qspi controller clock
Vikas Manocha [Mon, 10 Apr 2017 22:02:50 +0000 (15:02 -0700)]
stm32f7: use clock driver to enable qspi controller clock

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
cc: Christophe KERELLO <christophe.kerello@st.com>

7 years agospl: make image arg or fdt blob address reconfigurable
Vikas Manocha [Fri, 7 Apr 2017 22:38:13 +0000 (15:38 -0700)]
spl: make image arg or fdt blob address reconfigurable

At present fdt blob or argument address being passed to kernel is fixed at
compile time using macro CONFIG_SYS_SPL_ARGS_ADDR. FDT blob from
different media like nand, nor flash are copied to the address pointed
by the macro.
The problem is, it makes args/fdt blob compulsory to copy which is not required
in cases like for NOR Flash. This patch removes this limitation.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
7 years agoarm: am57xx: cl-som-am57x: enable USB commands
Uri Mashiach [Thu, 23 Feb 2017 13:39:41 +0000 (15:39 +0200)]
arm: am57xx: cl-som-am57x: enable USB commands

Add CONFIG_CMD_USB to the defconfig file.

Signed-off-by: Uri Mashiach <uri.mashiach@compulab.co.il>
Reviewed-by: Tom Rini <trini@konsulko.com>
7 years agoarm: am57xx: cl-som-am57x: enable USB storage
Uri Mashiach [Thu, 23 Feb 2017 13:39:40 +0000 (15:39 +0200)]
arm: am57xx: cl-som-am57x: enable USB storage

Add CONFIG_USB_STORAGE to the defconfig file.

Signed-off-by: Uri Mashiach <uri.mashiach@compulab.co.il>
Reviewed-by: Tom Rini <trini@konsulko.com>
7 years agoarm: am57xx: cl-som-am57x: fix USB scan
Uri Mashiach [Thu, 23 Feb 2017 13:39:39 +0000 (15:39 +0200)]
arm: am57xx: cl-som-am57x: fix USB scan

USB bus scan attempt:
----------------------------------cut----------------------------------
=> usb start
starting USB...
USB0:   Register 2000140 NbrPorts 2
Starting the controller
USB XHCI 1.00
scanning bus 0 for devices... data abort
pc : [<fff6240e>]          lr : [<fff623b3>]
reloc pc : [<8081b40e>]    lr : [<8081b3b3>]
sp : fdf42930  ip : fdf42960     fp : 00000000
r10: 00000001  r9 : fdf42ef0     r8 : 48890020
r7 : 00000002  r6 : fffa5840     r5 : fff8b140  r4 : fdf429c0
r3 : 00000000  r2 : 00000004     r1 : 00000000  r0 : 00000000
Flags: nZcv  IRQs off  FIQs off  Mode SVC_32
Resetting CPU ...

resetting ...
----------------------------------cut----------------------------------

Fix by enabling USB configuration in the SPL.

Signed-off-by: Uri Mashiach <uri.mashiach@compulab.co.il>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Igor Grinberg <grinberg@compulab.co.il>
7 years agoarm: am57xx: cl-som-am57x: invoke clock API to enable/disable clocks
Uri Mashiach [Thu, 23 Feb 2017 13:39:38 +0000 (15:39 +0200)]
arm: am57xx: cl-som-am57x: invoke clock API to enable/disable clocks

Invoke enable_usb_clocks during board_usb_init and disable_usb_clocks
during board_usb_exit to enable and disable clocks respectively.

Modifications:
* Enable USB clocks in the OMAP version of the function
  board_usb_init.
* Disable USB clocks in the OMAP version of the function
  board_usb_cleanup.

Cc: Marek Vasut <marex@denx.de>
Signed-off-by: Uri Mashiach <uri.mashiach@compulab.co.il>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
7 years agousb: host: xhci-omap: fix double weak board_usb_init functions
Uri Mashiach [Thu, 23 Feb 2017 13:39:37 +0000 (15:39 +0200)]
usb: host: xhci-omap: fix double weak board_usb_init functions

A weak version of the function board_usb_init is implemented in:
common/usb.c
drivers/usb/host/xhci-omap.c

To fix the double implementations:
* Convert the board_usb_init function in drivers/usb/host/xhci-omap.c
  normal (not weak).
* The function board_usb_init in drivers/usb/host/xhci-omap.c calls to
  the weak function omap_xhci_board_usb_init.
* Rename board version of the function board_usb_init to
  omap_xhci_board_usb_init.
  Done only for boards that defines CONFIG_USB_XHCI_OMAP.

To achieve the same flexibility with the function board_usb_cleanup:
* Add a normal (not weak) implementation of the function
  board_usb_cleanup in drivers/usb/host/xhci-omap.c
* The function board_usb_cleanup in drivers/usb/host/xhci-omap.c calls
  to the weak function omap_xhci_board_usb_cleanup.
* Rename board version of the function board_usb_cleanup to
  omap_xhci_board_usb_cleanup.
  Done only for boards that defines CONFIG_USB_XHCI_OMAP.

Cc: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Uri Mashiach <uri.mashiach@compulab.co.il>
Acked-by: Marek Vasut <marex@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Roger Quadros <rogerq@ti.com>
7 years agoarm: usb: dra7xx: xHCI registers based on USB port index
Uri Mashiach [Thu, 23 Feb 2017 13:39:36 +0000 (15:39 +0200)]
arm: usb: dra7xx: xHCI registers based on USB port index

Modify the determination of the base address of xHCI registers of DRA7XX
targets.
Before the commit: by the target.
After the commit: by the USB port index.

Cc: Lokesh Vutla <lokeshvutla@ti.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Roger Quadros <rogerq@ti.com>
Signed-off-by: Uri Mashiach <uri.mashiach@compulab.co.il>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Roger Quadros <rogerq@ti.com>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Marek Vasut <marex@denx.de>
7 years agoarm: dra7xx: move CONFIG_DRA7XX to Kconfig
Uri Mashiach [Thu, 23 Feb 2017 13:39:35 +0000 (15:39 +0200)]
arm: dra7xx: move CONFIG_DRA7XX to Kconfig

The symbol CONFIG_DRA7XX is needed for Kconfig conditions.

Cc: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Uri Mashiach <uri.mashiach@compulab.co.il>
Reviewed-by: Tom Rini <trini@konsulko.com>
7 years agoPrepare v2017.05
Tom Rini [Mon, 8 May 2017 14:11:08 +0000 (10:11 -0400)]
Prepare v2017.05

Signed-off-by: Tom Rini <trini@konsulko.com>
7 years agoboard/BuR/common: incorrect check of dtb
xypron.glpk@gmx.de [Fri, 5 May 2017 18:57:32 +0000 (20:57 +0200)]
board/BuR/common: incorrect check of dtb

The logical expression to check the dtb is incorrect in
load_devicetree.

The problem was indicated by cppcheck.

The inconsistent variable name dtppart is changed to dtbpart.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Hannes Schmelzer <oe5hpm@oevsv.at>
Acked-by: Hannes Schmelzer <oe5hpm@oevsv.at>
7 years agotools: sunxi: avoid read after end of string
xypron.glpk@gmx.de [Thu, 4 May 2017 20:26:42 +0000 (22:26 +0200)]
tools: sunxi: avoid read after end of string

The evaluation of option -c is incorrect:

According to the C99 standard endptr in the first strtol is always
set as &endptr is not NULL.
So the first part of the or condition is always true.
If all digits in optarg are valid endptr will point to the closing \0
and the second strtol will read beyond the end of the string optarg
points to.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
7 years agorelocate-rela: add missing va_end()
xypron.glpk@gmx.de [Wed, 3 May 2017 20:40:11 +0000 (22:40 +0200)]
relocate-rela: add missing va_end()

va_start must always be matched by va_end.

The problem was indicated by cppcheck.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
7 years agolib: circbuf: avoid possible null pointer dereference
xypron.glpk@gmx.de [Wed, 3 May 2017 21:20:10 +0000 (23:20 +0200)]
lib: circbuf: avoid possible null pointer dereference

We should not first dereference p and afterwards assert that is
was not NULL. Instead do the assert first.

The problem was indicated by cppcheck.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
7 years agoarm64: mvebu: incorrect check of fdt address cells
xypron.glpk@gmx.de [Wed, 3 May 2017 21:31:58 +0000 (23:31 +0200)]
arm64: mvebu: incorrect check of fdt address cells

In dram_init_banksize there seems to be a typo concerning
a plausibility check of the fdt.
Testing sc > 2 twice does not make any sense.

The problem was indicated by cppcheck.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
7 years agomeson: gxbb: increase CONFIG_SYS_BOOTM_LEN
xypron.glpk@gmx.de [Fri, 14 Apr 2017 17:54:40 +0000 (19:54 +0200)]
meson: gxbb: increase CONFIG_SYS_BOOTM_LEN

A feature rich Linux kernel needs more than 8 MiB.
Hence enlarge CONFIG_SYS_BOOTM_LEN to 64 MiB for the GXBB systems.
As all known GXBB systems have at least 512 MiB of RAM this poses no problem.

Cc: Andreas Färber <afaerber@suse.de>
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
7 years agoMerge branch 'master' of git://git.denx.de/u-boot-spi
Tom Rini [Fri, 5 May 2017 20:45:30 +0000 (16:45 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-spi

7 years agosunxi: add support for Banana Pi M2 Plus board
Icenowy Zheng [Wed, 3 May 2017 15:45:09 +0000 (23:45 +0800)]
sunxi: add support for Banana Pi M2 Plus board

Banana Pi M2 Plus is an Allwinner H3-based SBC by Sinovoip, which has
already mainline device tree file that have landed into U-Boot source
tree.

Add a defconfig file for it and add the MAINTAINERS items.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
7 years agodrivers: spi: Remove duplicate .probe method
Suniel Mahesh [Wed, 3 May 2017 06:17:29 +0000 (11:47 +0530)]
drivers: spi: Remove duplicate .probe method

.probe method has been assigned twice when declaring
a driver with U_BOOT_DRIVER(). Removed one of them.
Here is the last commit which had the duplicate entry:
"spi: omap3: Convert to driver model"
(sha1: 77b8d04854f486741471ad02b93b473b5b3d72f8)

Signed-off-by: Suniel Mahesh <suniel.spartan@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
7 years agoenv_sf: use DIV_ROUND_UP to calculate number of sectors to erase
Andreas Fenkart [Sat, 8 Apr 2017 09:59:34 +0000 (11:59 +0200)]
env_sf: use DIV_ROUND_UP to calculate number of sectors to erase

simpler to read

Signed-off-by: Andreas Fenkart <afenkart@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@openedev.com>
7 years agoenv_sf: re-order error handling in single-buffer env_relocate_spec
Andreas Fenkart [Sat, 8 Apr 2017 09:59:33 +0000 (11:59 +0200)]
env_sf: re-order error handling in single-buffer env_relocate_spec

this makes it easier comparable to the double-buffered version

Signed-off-by: Andreas Fenkart <afenkart@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@openedev.com>
7 years agoenf_sf: reuse setup_flash_device instead of open coding it
Andreas Fenkart [Sat, 8 Apr 2017 09:59:32 +0000 (11:59 +0200)]
enf_sf: reuse setup_flash_device instead of open coding it

setup_flash_device selects one of two code paths depending on the driver
model being used (=CONFIG_DM_SPI_FLASH). env_relocate_spec only used
the non driver-model code path. I'm unsure why, either none of the
platforms that need relocation use the driver model, or - worse - the
driver model is not yet usable when relocating.

Signed-off-by: Andreas Fenkart <afenkart@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@openedev.com>
7 years agoenv_sf: factor out prepare_flash_device
Andreas Fenkart [Sat, 8 Apr 2017 09:59:31 +0000 (11:59 +0200)]
env_sf: factor out prepare_flash_device

copy&paste code found in single/double buffered code path

Signed-off-by: Andreas Fenkart <afenkart@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@openedev.com>
7 years agozynq: spi: Honour the activation / deactivation delay
Moritz Fischer [Thu, 8 Dec 2016 20:11:09 +0000 (12:11 -0800)]
zynq: spi: Honour the activation / deactivation delay

This is not currently implemented. Add support for this so that the
Chrome OS EC can be used reliably.

Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
Acked-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jagan@openedev.com>
7 years agospi: atmel: check GPIO validity before using cs_gpios
Wenyou Yang [Fri, 7 Apr 2017 07:14:46 +0000 (15:14 +0800)]
spi: atmel: check GPIO validity before using cs_gpios

Before using the cs_gpio, check if the GPIO is valid or not.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
7 years agosunxi: enable SATA on Banana Pi M2 Ultra
Icenowy Zheng [Mon, 1 May 2017 06:31:57 +0000 (14:31 +0800)]
sunxi: enable SATA on Banana Pi M2 Ultra

Banana Pi M2 Ultra has a SATA port connected to the internal SATA
controller of R40 SoC. The controller's 1.2v VDD is connected to ELDO3
and the 2.5v VDD is connected to DLDO4.

Enable these regulators as well as the SATA support of Banana Pi M2
Ultra, by adding needed config lines into its defconfig.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
7 years agosunxi: add clock configuration of R40 sata
Icenowy Zheng [Mon, 1 May 2017 06:31:56 +0000 (14:31 +0800)]
sunxi: add clock configuration of R40 sata

R40 has a similar SATA controller with the ones on A10/A20, but with a
reset line added (like other peripherals on sun6i+), and two extra VDD
pins added (1.2v and 2.5v).

Add clock configuration of R40 SATA.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
7 years agoARM: sunxi: use imply instead of bare default y in Kconfig
Masahiro Yamada [Fri, 28 Apr 2017 10:42:19 +0000 (19:42 +0900)]
ARM: sunxi: use imply instead of bare default y in Kconfig

Fix annoying config redefines in SoC/board level Kconfig.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
7 years agoARM: sunxi: move board/sunxi/Kconfig to arch/arm/mach-sunxi/Kconfig
Masahiro Yamada [Fri, 28 Apr 2017 10:42:18 +0000 (19:42 +0900)]
ARM: sunxi: move board/sunxi/Kconfig to arch/arm/mach-sunxi/Kconfig

For the consistent location of SoC-level Kconfig.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>