Justin Chadwell [Mon, 29 Jul 2019 16:13:10 +0000 (17:13 +0100)]
Support larger RSA key sizes when using MBEDTLS
Previously, TF-A could not support large RSA key sizes as the
configuration options passed to MBEDTLS prevented storing and performing
calculations with the larger, higher-precision numbers required. With
these changes to the arguments passed to MBEDTLS, TF-A now supports
using 3072 (3K) and 4096 (4K) keys in certificates.
Change-Id: Ib73a6773145d2faa25c28d04f9a42e86f2fd555f
Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
Soby Mathew [Thu, 12 Sep 2019 12:34:27 +0000 (12:34 +0000)]
Merge "libc: fix sparse warning for __assert()" into integration
Soby Mathew [Thu, 12 Sep 2019 12:33:20 +0000 (12:33 +0000)]
Merge "doc: Updated user guide with new Mbed TLS version number" into integration
Soby Mathew [Thu, 12 Sep 2019 12:33:02 +0000 (12:33 +0000)]
Merge "intel: agilex: Fix psci power domain off" into integration
Soby Mathew [Thu, 12 Sep 2019 12:31:22 +0000 (12:31 +0000)]
Merge changes from topic "jc/mte_enable" into integration
* changes:
Add documentation for CTX_INCLUDE_MTE_REGS
Enable MTE support in both secure and non-secure worlds
Soby Mathew [Thu, 12 Sep 2019 12:29:46 +0000 (12:29 +0000)]
Merge "plat: xilinx: zynqmp: Initialize IPI table from zynqmp_config_setup()" into integration
Soby Mathew [Thu, 12 Sep 2019 11:38:42 +0000 (11:38 +0000)]
Merge "Zeus: apply the MSR SSBS instruction" into integration
Soby Mathew [Thu, 12 Sep 2019 11:14:21 +0000 (11:14 +0000)]
Merge "Add UBSAN support and handlers" into integration
Soby Mathew [Thu, 12 Sep 2019 11:11:34 +0000 (11:11 +0000)]
Merge changes I072c0f61,I798401f4,I9648ef55,I7225d9fa,Ife682288, ... into integration
* changes:
rcar_gen3: drivers: ddr_b: Update DDR setting for H3, M3, M3N
rcar_gen3: drivers: qos: update QoS setting
rcar_gen3: drivers: ddr_b: Fix checkpatch errors in headers
rcar_gen3: drivers: ddr_b: Fix line-over-80s
rcar_gen3: drivers: ddr_b: Further checkpatch cleanups
rcar_gen3: drivers: ddr_b: Clean up camel case
rcar_get3: drivers: ddr_b: Basic checkpatch fixes
rcar_get3: drivers: ddr: Partly unify register macros between DDR A and B
rcar_get3: drivers: ddr: Clean up common code
Soby Mathew [Thu, 12 Sep 2019 10:58:43 +0000 (10:58 +0000)]
Merge changes from topic "amlogic-refactoring" into integration
* changes:
amlogic: Fix includes order
amlogic: Fix header guards
amlogic: Fix prefixes in the SoC specific files
amlogic: Fix prefixes in the PM code
amlogic: Fix prefixes in the SCPI related code
amlogic: Fix prefixes in the MHU code
amlogic: Fix prefixes in the SIP/SVC code
amlogic: Fix prefixes in the thermal driver
amlogic: Fix prefixes in the private header file
amlogic: Fix prefixes in the efuse driver
amlogic: Fix prefixes in the platform macros file
amlogic: Fix prefixes in the helpers file
amlogic: Rework Makefiles
amlogic: Move the SIP SVC code to common directory
amlogic: Move topology file to common directory
amlogic: Move thermal code to common directory
amlogic: Move MHU code to common directory
amlogic: Move efuse code to common directory
amlogic: Move platform macros assembly file to common directory
amlogic: Introduce unified private header file
amlogic: Move SCPI code to common directory
amlogic: Move the SHA256 DMA driver to common directory
amlogic: Move assembly helpers to common directory
amlogic: Introduce directory parameters in the makefiles
meson: Rename platform directory to amlogic
Hadi Asyrafi [Thu, 12 Sep 2019 07:14:01 +0000 (15:14 +0800)]
intel: agilex: Fix psci power domain off
Disable gic cpu interface for powered down cpu. This patch also removes
core reset during power off as core reset will be done during power on
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I2ca96d876b6e71e56d24a9a7e184b6d6226b8673
Carlo Caione [Tue, 3 Sep 2019 11:38:58 +0000 (12:38 +0100)]
amlogic: Fix includes order
As part of the code refactoring fix the order of the include files
across all the source files.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Change-Id: Ice72f687cc26ee881a9051168149467688100cfb
Carlo Caione [Wed, 28 Aug 2019 09:14:46 +0000 (10:14 +0100)]
amlogic: Fix header guards
Make the header guards more generic and contextually remove the
GXBB_BL31_PLAT_PARAM_VAL value that is unused on the GXL platform.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Change-Id: I842fa2e084e71280ae17b39c67877e844821a171
Soby Mathew [Wed, 11 Sep 2019 16:21:29 +0000 (16:21 +0000)]
Merge "mbedtls: use #include <...> instead of "..."" into integration
John Tsichritzis [Tue, 13 Aug 2019 09:28:25 +0000 (10:28 +0100)]
Zeus: apply the MSR SSBS instruction
Zeus supports the SSBS mechanism and also the new MSR instruction to
immediately apply the mitigation. Hence, the new instruction is utilised
in the Zeus-specific reset function.
Change-Id: I962747c28afe85a15207a0eba4146f9a115b27e7
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
Justin Chadwell [Tue, 20 Aug 2019 10:01:52 +0000 (11:01 +0100)]
Add UBSAN support and handlers
This patch adds support for the Undefined Behaviour sanitizer. There are
two types of support offered - minimalistic trapping support which
essentially immediately crashes on undefined behaviour and full support
with full debug messages.
The full support relies on ubsan.c which has been adapted from code used
by OPTEE.
Change-Id: I417c810f4fc43dcb56db6a6a555bfd0b38440727
Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
Masahiro Yamada [Fri, 26 Jul 2019 11:21:39 +0000 (20:21 +0900)]
libc: fix sparse warning for __assert()
Sparse warns this:
lib/libc/assert.c:29:6: error: symbol '__assert' redeclared with different type (originally declared at include/lib/libc/assert.h:36) - different modifiers
Add __dead2 to match the header declaration and C definition.
I also changed '__dead2 void' to 'void __dead2' for the consistency
with other parts.
Change-Id: Iefa4f0e787c24fa7e7e499d2e7baf54d4deb49ef
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Jolly Shah [Tue, 27 Aug 2019 18:23:08 +0000 (11:23 -0700)]
plat: xilinx: zynqmp: Initialize IPI table from zynqmp_config_setup()
Common ipi_table needs to be initialized before using any
IPI command (i.e send/receive). Move zynqmp ipi config table
initialization from sip_svc_setup() to zynqmp_config_setup().
Change-Id: Ic8aaa0728a43936cd4c6e1ed590e01ba8f0fbf5b
Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Soby Mathew [Tue, 10 Sep 2019 14:32:59 +0000 (14:32 +0000)]
Merge changes from topic "yg/stm32mp1_wdg_updates" into integration
* changes:
mmc: stm32_sdmmc2: correctly manage block size
mmc: stm32_sdmmc2: manage max-frequency property from DT
stm32mp1: move check_header() to common code
stm32mp1: keep console during runtime
stm32mp1: sp_min: initialize MMU and cache earlier
stm32mp1: add support for LpDDR3
stm32mp1: use a common function to check spinlock is available
clk: stm32mp: enable RTCAPB clock for dual-core chips
stm32mp1: check if the SoC is single core
stm32mp1: print information about board
stm32mp1: print information about SoC
stm32mp1: add watchdog support
Justin Chadwell [Thu, 18 Jul 2019 15:16:32 +0000 (16:16 +0100)]
Add documentation for CTX_INCLUDE_MTE_REGS
A new build flag, CTX_INCLUDE_MTE_REGS, has been added; this patch adds
documentation for it in the User Guide along with instructions of what
different values mean.
Change-Id: I430a9c6ced06b1b6be317edbeff4f5530e30f63a
Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
Justin Chadwell [Thu, 18 Jul 2019 13:25:33 +0000 (14:25 +0100)]
Enable MTE support in both secure and non-secure worlds
This patch adds support for the new Memory Tagging Extension arriving in
ARMv8.5. MTE support is now enabled by default on systems that support
at EL0. To enable it at ELx for both the non-secure and the secure
world, the compiler flag CTX_INCLUDE_MTE_REGS includes register saving
and restoring when necessary in order to prevent register leakage
between the worlds.
Change-Id: I2d4ea993d6b11654ea0d4757d00ca20d23acf36c
Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
Carlo Caione [Wed, 28 Aug 2019 14:32:22 +0000 (15:32 +0100)]
amlogic: Fix prefixes in the SoC specific files
Remove the GXBB prefix where needed and add SoC specific prefixes for
GXBB/GXL.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Change-Id: Ic3eb3a77ca2d9c779a9dee5cee786e9c16ecdb27
Carlo Caione [Wed, 28 Aug 2019 14:19:56 +0000 (15:19 +0100)]
amlogic: Fix prefixes in the PM code
Remove the GXBB prefix from the code in the common directory and add
SoC-specific prefixes in the SoC specific code.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Change-Id: Ic983ef70b0ef23f95088dd8df488d8c42c3bc030
Carlo Caione [Wed, 28 Aug 2019 09:08:24 +0000 (10:08 +0100)]
amlogic: Fix prefixes in the SCPI related code
Add a new aml_* prefix to the SCPI related function calls.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Change-Id: I697812ac1c0df28cbb639a1dc3e838f1107fb739
Carlo Caione [Wed, 28 Aug 2019 08:46:18 +0000 (09:46 +0100)]
amlogic: Fix prefixes in the MHU code
Make the MHU code AML specific adding a new aml_* prefix and remove the
GXBB prefix from the register names.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Change-Id: I8f20918e29f08542bd71bd679f88e65b4efaa7d2
Carlo Caione [Mon, 26 Aug 2019 12:04:12 +0000 (13:04 +0100)]
amlogic: Fix prefixes in the SIP/SVC code
All the SIP/SVC related code is currently the same between GXL and GXBB.
Rename function names and register names to avoid hardcoding the GXBB
prefix.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Change-Id: I7e58ab68489df8d4762663fc01fb64e6899cc8bf
Carlo Caione [Sun, 25 Aug 2019 17:09:59 +0000 (18:09 +0100)]
amlogic: Fix prefixes in the thermal driver
No need to have a special SoC-specific prefix.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Change-Id: I0da543e7d92d56604e79440a98027ffd9a2eaa59
Carlo Caione [Sun, 25 Aug 2019 17:09:03 +0000 (18:09 +0100)]
amlogic: Fix prefixes in the private header file
The header file is shared between all the SoCs. Better avoiding
hardcoding the SoC name in the function names.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Change-Id: I9074871bd1ed8a702c1a656e0f50f2d3c6cb0425
Carlo Caione [Sun, 25 Aug 2019 16:26:27 +0000 (17:26 +0100)]
amlogic: Fix prefixes in the efuse driver
The efuse driver is hardcoding the GXBB prefix. No need to do that since
the driver is shared between multiple SoCs.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Change-Id: I97691b0bbd55170d8216d301a3fc04feb8c2af2e
Carlo Caione [Sat, 24 Aug 2019 17:51:48 +0000 (18:51 +0100)]
amlogic: Fix prefixes in the platform macros file
Fixing at the same time the related register names.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Change-Id: Ib1130d50abe6088f1c0826878d1ae454a0f23008
Carlo Caione [Sat, 24 Aug 2019 17:47:06 +0000 (18:47 +0100)]
amlogic: Fix prefixes in the helpers file
The code is the common directory is now generic, no need to have the SoC
prefix hardcoded in the function names.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Change-Id: Ied3a5e506b9abd4c2d6f893bafef50019bff24f1
Carlo Caione [Sat, 24 Aug 2019 17:37:46 +0000 (18:37 +0100)]
amlogic: Rework Makefiles
Now that every piece is in place, the makefiles can be refactored and
slightly beautified removing useless and redundant parts.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Change-Id: If74e1909df52d475cf4b0dfed819d07d3a4c85b9
Carlo Caione [Sat, 24 Aug 2019 16:52:40 +0000 (17:52 +0100)]
amlogic: Move the SIP SVC code to common directory
The code is the same between GXBB and GXL. Move it to the common source
directory.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Change-Id: I875689a6fd029971aa755fc2725217e90ed06b6c
Carlo Caione [Sat, 24 Aug 2019 16:50:16 +0000 (17:50 +0100)]
amlogic: Move topology file to common directory
As done already for multiple files, move the topology file to the common
directory.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Change-Id: Iaca357a089593ad58c35c05c929239132249dcda
Carlo Caione [Sat, 24 Aug 2019 16:48:11 +0000 (17:48 +0100)]
amlogic: Move thermal code to common directory
As for most of the Amlogic code, this is common between the Amlogic
SoCs. Move the code to the common directory.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Change-Id: Id3f0073ff1f0b9ddbe964f80303323ee4a2f27b0
Carlo Caione [Sat, 24 Aug 2019 16:46:04 +0000 (17:46 +0100)]
amlogic: Move MHU code to common directory
The MHU code is shared between all the supported platforms. Move it to
the common directory instead.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Change-Id: Iaf53122866eae85c13f772927d16836dcfa877a3
Carlo Caione [Sat, 24 Aug 2019 16:43:33 +0000 (17:43 +0100)]
amlogic: Move efuse code to common directory
The efuse code is the same between GXL and GXBB. Move the code to common
directory.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Change-Id: Ie37f21d1907a36292724f1fb645a78041fe4a6b3
Carlo Caione [Sat, 24 Aug 2019 16:36:32 +0000 (17:36 +0100)]
amlogic: Move platform macros assembly file to common directory
The platform macros are shared between all the SoCs. Move it to common
directory.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Change-Id: Ia04c3ffe4d7b068aa701268ed99f69995d8db92b
Carlo Caione [Sat, 24 Aug 2019 16:31:51 +0000 (17:31 +0100)]
amlogic: Introduce unified private header file
Now that also the SHA256 DMA driver is shared between all the SoCs, we
can have one single private platform header file.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Change-Id: I77d51915f9d8233aeceeed66ed1f491573402cfc
Carlo Caione [Sat, 24 Aug 2019 16:28:23 +0000 (17:28 +0100)]
amlogic: Move SCPI code to common directory
The SCPI code is the same between GXBB and GXL. No need to have it
replicated for each SoCs. Move it to the common directory.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Change-Id: I7e416caf1e9538b3ce7702c0363ee00a054e2451
Carlo Caione [Sat, 24 Aug 2019 16:17:30 +0000 (17:17 +0100)]
amlogic: Move the SHA256 DMA driver to common directory
The SHA256 DMA driver can be used by multiple SoCs. Move it to the
common directory.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Change-Id: I96319eeeeeebd503ef0dcb07c0e4ff6a67afeaa5
Carlo Caione [Fri, 23 Aug 2019 19:02:32 +0000 (20:02 +0100)]
amlogic: Move assembly helpers to common directory
The assembly helpers are common to all the amlogic SoCs. Move the .S
file to the common directory.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Change-Id: I0d8616a7ae22dbcb14848cefd0149b6bb5814ea6
Carlo Caione [Fri, 23 Aug 2019 18:34:44 +0000 (19:34 +0100)]
amlogic: Introduce directory parameters in the makefiles
Make the platform name a parameter for the source directories. Besides a
cosmetic fix, this is going to be helpful when reusing the same Makefile
for different SoCs.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Change-Id: I307897a21800cca8ad68a5ab8972d27e9356ff2a
Carlo Caione [Fri, 23 Aug 2019 17:28:36 +0000 (18:28 +0100)]
meson: Rename platform directory to amlogic
Meson is the internal code name for the SoC family. The correct name for
the platform should be Amlogic. Change the name of the platform
directory.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Change-Id: Icc140e1ea137f12117acbf64c7dcb1a8b66b345d
Sandrine Bailleux [Thu, 5 Sep 2019 09:11:31 +0000 (09:11 +0000)]
Merge "intel: stratix10: Fix reliance on hard coded clock information" into integration
zelalem-aweke [Wed, 4 Sep 2019 21:16:51 +0000 (16:16 -0500)]
doc: Updated user guide with new Mbed TLS version number
Signed-off-by: zelalem-aweke <zelalem.aweke@arm.com>
Change-Id: Ib12ecc0b283274c74cdfa57caf9e1a105dce3afe
Masahiro Yamada [Wed, 4 Sep 2019 05:09:07 +0000 (14:09 +0900)]
mbedtls: use #include <...> instead of "..."
The #include "mbedtls/check_config.h" directive first searches for
the header in the relative path to mbedtls_config.h, i.e.
include/drivers/auth/mbedtls/mbedtls/check_config.h
Obviously, it does not exist since check_config.h is located in
the mbedtls project.
It is more sensible to use #include <...> form.
Change-Id: If72a71381f84e7748a2c9f07dd1176559d9bb1d2
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Alexei Fedorov [Tue, 3 Sep 2019 11:00:06 +0000 (11:00 +0000)]
Merge "uniphier: set CONSOLE_FLAG_TRANSLATE_CRLF and clean up console driver" into integration
Masahiro Yamada [Tue, 23 Jul 2019 03:53:41 +0000 (12:53 +0900)]
uniphier: set CONSOLE_FLAG_TRANSLATE_CRLF and clean up console driver
This console driver sends '\r' before 'n', not after.
It works, but the convention is "\r\n" (i.e. CRLF)
Instead of fixing it in the driver, set CONSOLE_FLAG_TRANSLATE_CRLF
to leave it to the framework.
Change-Id: I2154e29313739a40dff70cfb5c0f8989136d4ad2
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Yann Gautier [Tue, 11 Jun 2019 18:03:07 +0000 (20:03 +0200)]
mmc: stm32_sdmmc2: correctly manage block size
DBLOCKSIZE should be filled such as the data size is 2^DBLOCKSIZE.
Hence it is calculated with __builtin_ctz.
Change-Id: Id6b5ff9b594afc4fc523a388011beed307e6abd1
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Yann Gautier [Tue, 28 May 2019 09:54:50 +0000 (11:54 +0200)]
mmc: stm32_sdmmc2: manage max-frequency property from DT
If the max-frequency property is provided in the device tree mmc node,
it should be managed. The max allowed frequency will be the min between
this property value and what the card can support.
Change-Id: I885b676c3300d2670a0fe4c6ecab87758b5893ad
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Yann Gautier [Fri, 19 Apr 2019 08:48:36 +0000 (10:48 +0200)]
stm32mp1: move check_header() to common code
This function can be used on several stm32mp devices, it is then moved in
plat/st/common/stm32mp_common.c.
Change-Id: I862debe39604410f71a9ddc28713026362e9ecda
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Yann Gautier [Wed, 24 Apr 2019 14:14:22 +0000 (16:14 +0200)]
stm32mp1: keep console during runtime
The runtime console is only kept in DEBUG configuration.
Change-Id: I0447dfcacb9a63a12bcdab7c55584d70c3220e5b
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Yann Gautier [Thu, 11 Jul 2019 08:45:09 +0000 (10:45 +0200)]
stm32mp1: sp_min: initialize MMU and cache earlier
This change enhances performance and security in BL32 stage.
Change-Id: I64df5995fc6b04f6cf42d6a00a6d3d0f602b5407
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Yann Gautier [Tue, 16 Apr 2019 14:20:58 +0000 (16:20 +0200)]
stm32mp1: add support for LpDDR3
This change enables LpDDR3 initialization with PMIC.
Change-Id: I2409a808335dfacd69a8517cb8510cee98bb8161
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Yann Gautier [Wed, 22 May 2019 17:13:51 +0000 (19:13 +0200)]
stm32mp1: use a common function to check spinlock is available
To use spinlocks, MMU should be enabled, as well as data cache.
A common function is created (moved from clock file).
It is then used whenever a spinlock has to be taken, in BSEC and clock
drivers.
Change-Id: I94baed0114a2061ad71bd5287a91bf7f1c6821f6
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Yann Gautier [Mon, 20 May 2019 12:39:26 +0000 (14:39 +0200)]
clk: stm32mp: enable RTCAPB clock for dual-core chips
In order to correctly manage the bring-up of non boot CPUs, the RTCAPB
clock needs to be enabled.
It controls the access to backup registers, where the CPU entrypoint
will be stored.
Change-Id: Ifeeceb4faf64bc9e0778030444f437cc0bb27272
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Yann Gautier [Tue, 4 Jun 2019 16:23:10 +0000 (18:23 +0200)]
stm32mp1: check if the SoC is single core
Among the variants of STM32MP, the STM32MP151 is a single Cortex-A7 chip.
A function is added to check the part number of the SoC.
If it corresponds to STM32MP151A or STM32MP151C, then the chip has a single
Cortex-A7.
Change-Id: Icac2015c5d03ce0bcb8e99bbaf1ec8ada34be49c
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Yann Gautier [Mon, 13 May 2019 16:34:48 +0000 (18:34 +0200)]
stm32mp1: print information about board
On STMicroelectronics boards, the board information is stored in OTP.
This OTP is described in device tree, in BSEC board_id node.
Change-Id: Ieccbdcb048343680faac8dc577b75c67ac106f5b
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Yann Gautier [Tue, 4 Jun 2019 16:02:37 +0000 (18:02 +0200)]
stm32mp1: print information about SoC
This information is located in DBGMCU registers.
Change-Id: I480aa046fed9992e3d9665b1f0520bc4b6cfdf30
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Yann Gautier [Tue, 4 Jun 2019 16:06:34 +0000 (18:06 +0200)]
stm32mp1: add watchdog support
Introduce driver for STM32 IWDG peripheral (Independent Watchdog).
It is configured according to device tree content and should be enabled
from there.
The watchdog is not started by default. It can be started after an HW
reset if the dedicated OTP is fused.
The watchdog also needs to be frozen if a debugger is attached.
This is done by configuring the correct bits in DBGMCU.
This configuration is allowed by checking BSEC properties.
An increase of BL2 size is also required when adding this new code.
Change-Id: Ide7535d717885ce2f9c387cf17afd8b5607f3e7f
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Paul Beesley [Mon, 2 Sep 2019 10:22:38 +0000 (10:22 +0000)]
Merge "Added SPCI to the glossary" into integration
Paul Beesley [Thu, 29 Aug 2019 16:05:28 +0000 (16:05 +0000)]
Merge "Move assembly newline function into common debug code" into integration
Artsem Artsemenka [Thu, 29 Aug 2019 12:47:53 +0000 (13:47 +0100)]
Added SPCI to the glossary
Change-Id: I576ae161477f4a69336d15a7741e566bb103124a
Signed-off-by: Artsem Artsemenka <artsem.artsemenka@arm.com>
Justin Chadwell [Tue, 20 Aug 2019 09:58:49 +0000 (10:58 +0100)]
Move assembly newline function into common debug code
Printing a newline is a relatively common functionality for code to want
to do. Therefore, this patch now moves this function into a common part
of the code that anyone can use.
Change-Id: I2cad699fde00ef8d2aabf8bf35742ddd88d090ba
Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
Chiaki Fujii [Mon, 8 Jul 2019 14:44:56 +0000 (23:44 +0900)]
rcar_gen3: drivers: ddr_b: Update DDR setting for H3, M3, M3N
[IPL/DDR]
- Update H3, M3, M3N DDR setting rev.0.37.
Signed-off-by: Chiaki Fujii <chiaki.fujii.wj@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I072c0f61cd896e74e4e1eee39d313f82cf2f7295
Yoshifumi Hosoya [Mon, 1 Jul 2019 10:45:41 +0000 (19:45 +0900)]
rcar_gen3: drivers: qos: update QoS setting
[IPL/QoS]
- Update M3 Ver.3.0 QoS setting rev.0.04.
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I798401f417df6a352d94311ea07a1e96ba562f6a
Marek Vasut [Thu, 8 Aug 2019 15:13:03 +0000 (17:13 +0200)]
rcar_gen3: drivers: ddr_b: Fix checkpatch errors in headers
Clean up the DDR B header files and remove checkpatch errors.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I9648ef5511df299688fd5284513812d32a1f8064
Marek Vasut [Thu, 8 Aug 2019 14:34:22 +0000 (16:34 +0200)]
rcar_gen3: drivers: ddr_b: Fix line-over-80s
Fix as many line-over-80s as possible. There are still a few remaining,
which would need further refactoring.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I7225d9fab658d05e3315d8c3fa3c9f3bbb1ab40d
Marek Vasut [Wed, 7 Aug 2019 17:56:09 +0000 (19:56 +0200)]
rcar_gen3: drivers: ddr_b: Further checkpatch cleanups
Address more checkpatch CHECKs and ERRORs, no functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: Ife682288cef3afa860571b2aca647c9ffe936125
Marek Vasut [Wed, 7 Aug 2019 17:17:42 +0000 (19:17 +0200)]
rcar_gen3: drivers: ddr_b: Clean up camel case
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: Ifda28578f326b1d4518560384d50ae98806db26e
Marek Vasut [Wed, 7 Aug 2019 17:02:26 +0000 (19:02 +0200)]
rcar_get3: drivers: ddr_b: Basic checkpatch fixes
Do basic automated checkpatch fixes on the ddr_b, no functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: Ie401ec049a05d2c4c8044749994391adea171679
Marek Vasut [Wed, 7 Aug 2019 16:19:26 +0000 (18:19 +0200)]
rcar_get3: drivers: ddr: Partly unify register macros between DDR A and B
The ddr_a and ddr_b register macros are the same for the most part,
unify them into a single header.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I8f55d6d779837215339ac0010e8c8ab5f6748d75
Marek Vasut [Wed, 7 Aug 2019 16:05:05 +0000 (18:05 +0200)]
rcar_get3: drivers: ddr: Clean up common code
Do minor coding style changes to the common DDR init code to make it
checkpatch compliant and move macros out into rcar_def.h.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I67eadf8099e4ff8702105c9e07b13f308d9dbe3d
Paul Beesley [Wed, 28 Aug 2019 13:05:51 +0000 (13:05 +0000)]
Merge "intel: agilex: Clear PLL lostlock bypass mode" into integration
Sandrine Bailleux [Tue, 27 Aug 2019 22:50:42 +0000 (22:50 +0000)]
Merge "tegra: add support for multi console interface" into integration
Paul Beesley [Fri, 23 Aug 2019 11:26:57 +0000 (11:26 +0000)]
Merge "AArch64: Disable Secure Cycle Counter" into integration
Alexei Fedorov [Tue, 13 Aug 2019 14:17:53 +0000 (15:17 +0100)]
AArch64: Disable Secure Cycle Counter
This patch fixes an issue when secure world timing information
can be leaked because Secure Cycle Counter is not disabled.
For ARMv8.5 the counter gets disabled by setting MDCR_El3.SCCD
bit on CPU cold/warm boot.
For the earlier architectures PMCR_EL0 register is saved/restored
on secure world entry/exit from/to Non-secure state, and cycle
counting gets disabled by setting PMCR_EL0.DP bit.
'include\aarch64\arch.h' header file was tided up and new
ARMv8.5-PMU related definitions were added.
Change-Id: I6f56db6bc77504634a352388990ad925a69ebbfa
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
Paul Beesley [Tue, 20 Aug 2019 14:47:56 +0000 (14:47 +0000)]
Merge "plat/arm: Introduce corstone700 platform." into integration
Paul Beesley [Tue, 20 Aug 2019 14:14:03 +0000 (14:14 +0000)]
Merge "rcar_gen3: plat: Rename RCAR_PRODUCT_* to PRR_PRODUCT_*" into integration
Manish Pandey [Wed, 28 Nov 2018 11:20:37 +0000 (11:20 +0000)]
plat/arm: Introduce corstone700 platform.
This patch adds support for Corstone-700 foundation IP, which integrates
both Cortex-M0+ and Cortex-A(Host) processors in one handy, flexible
subsystem.
This is an example implementation of Corstone-700 IP host firmware.
Cortex-M0+ will take care of boot stages 1 and 2(BL1/BL2) as well as
bringing Host out RESET. Host will start execution directly from BL32 and
then will jump to Linux.
It is an initial port and additional features are expected to be added
later.
Change-Id: I7b5c0278243d574284b777b2408375d007a7736e
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Paul Beesley [Tue, 20 Aug 2019 14:12:40 +0000 (14:12 +0000)]
Merge "rcar_gen3: plat: Factor out PRR_ macros into rcar_def.h" into integration
Paul Beesley [Tue, 20 Aug 2019 09:38:32 +0000 (09:38 +0000)]
Merge "intel: agilex: HMC driver calculate DDR size" into integration
Paul Beesley [Tue, 20 Aug 2019 09:37:37 +0000 (09:37 +0000)]
Merge "console: add a flag to prepend '\r' in the multi-console framework" into integration
Alexei Fedorov [Tue, 20 Aug 2019 09:31:16 +0000 (09:31 +0000)]
Merge "Fix for N1
1043202 Errata Workaround" into integration
Paul Beesley [Tue, 20 Aug 2019 09:25:00 +0000 (09:25 +0000)]
Merge "Coverity fix: Remove GGC ignore -Warray-bounds" into integration
laurenw-arm [Mon, 19 Aug 2019 16:06:18 +0000 (11:06 -0500)]
Fix for N1
1043202 Errata Workaround
ISB instruction was removed from the N1
1043202 Errata Workaround [1], this
fix is adding the ISB instruction back in.
[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-
466751330-10325/index.html
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: I74eac7f6ad38991c36d423ad6aa44558033ad388
Hadi Asyrafi [Fri, 16 Aug 2019 09:07:42 +0000 (17:07 +0800)]
intel: agilex: HMC driver calculate DDR size
Driver will calculate DDR size instead of using hardcoded value
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I642cf2180929965ef12bd5ae4393b2f3d0dcddde
Masahiro Yamada [Tue, 23 Jul 2019 03:32:58 +0000 (12:32 +0900)]
console: add a flag to prepend '\r' in the multi-console framework
Currently, console drivers prepend '\r' to '\n' by themselves. This is
common enough to be supported in the framework.
Add a new flag, CONSOLE_FLAG_TRANSLATE_CRLF. A driver can set this
flag to ask the framework to transform LF into CRLF instead of doing
it by itself.
Change-Id: I4f5c5887591bc0a8749a105abe62b6562eaf503b
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Hadi Asyrafi [Fri, 16 Aug 2019 03:08:14 +0000 (11:08 +0800)]
intel: agilex: Clear PLL lostlock bypass mode
To provide glitchless clock to downstream logic even if clock toggles
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I728d64d0ba3b4492125bea5b0737fc83180356f1
Deepika Bhavnani [Wed, 14 Aug 2019 21:56:46 +0000 (00:56 +0300)]
Coverity fix: Remove GGC ignore -Warray-bounds
GCC diagnostics were added to ignore array boundaries, instead
of ignoring GCC warning current code will check for array boundaries
and perform and array update only for valid elements.
Resolves: `CID 246574` `CID 246710` `CID 246651`
Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com>
Change-Id: I7530ecf7a1707351c6ee87e90cc3d33574088f57
Paul Beesley [Fri, 16 Aug 2019 14:48:32 +0000 (14:48 +0000)]
Merge "FVP: Add Delay Timer driver to BL1 and BL31" into integration
Paul Beesley [Fri, 16 Aug 2019 13:44:26 +0000 (13:44 +0000)]
Merge "Reduce the number of memory leaks in cert_create" into integration
Alexei Fedorov [Fri, 16 Aug 2019 13:15:59 +0000 (14:15 +0100)]
FVP: Add Delay Timer driver to BL1 and BL31
SMMUv3 driver functions which are called from BL1 and BL31
currently use counter-based poll method for testing status
bits. Adding Delay Timer driver to BL1 and BL31 is required
for timeout-based implementation using timer delay functions
for SMMU and other drivers.
This patch adds new function `fvp_timer_init()` which
initialises either System level generic or SP804 timer based on
FVP_USE_SP804_TIMER build flag.
In BL2U `bl2u_early_platform_setup()` function the call to
`arm_bl2u_early_platform_setup()` (which calls
`generic_delay_timer_init()` ignoring FVP_USE_SP804_TIMER flag),
is replaced with `arm_console_boot_init()` and `fvp_timer_init()`.
Change-Id: Ifd8dcebf4019e877b9bc5641551deef77a44c0d1
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
Marek Vasut [Tue, 6 Aug 2019 17:13:22 +0000 (19:13 +0200)]
rcar_gen3: plat: Rename RCAR_PRODUCT_* to PRR_PRODUCT_*
Rename RCAR_PRODUCT_* to PRR_PRODUCT_* and drop the duplicate
RCAR_PRODUCT_* macro.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I6b2789790b85edb79c026f0860d70f323d113d96
Marek Vasut [Tue, 6 Aug 2019 16:58:38 +0000 (18:58 +0200)]
rcar_gen3: plat: Factor out PRR_ macros into rcar_def.h
Pull out the PRR_* macros into rcar_def.h and remove multiple copies of
it. Now that there are still RCAR_* macros in rcar_def.h too and they
have the exact same meaning as the PRR_* macros, but that's for another
patch.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: Icb7f61b971b1a23102bd1b9f58cda580660a55fc
Justin Chadwell [Mon, 12 Aug 2019 11:19:21 +0000 (12:19 +0100)]
Reduce the number of memory leaks in cert_create
The valgrind checks for cert_create have not been run in a long while -
as such there are a few memory leaks present. This patch fixes a few of
the major ones reported by valgrind. However, a few do remain.
Change-Id: Iab002fb2b0090043287d43fb54a4d18928c2ed85
Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
Paul Beesley [Fri, 16 Aug 2019 12:41:45 +0000 (12:41 +0000)]
Merge "FVP_Base_AEMv8A platform: Fix cache maintenance operations" into integration
Alexei Fedorov [Mon, 29 Jul 2019 16:22:53 +0000 (17:22 +0100)]
FVP_Base_AEMv8A platform: Fix cache maintenance operations
This patch fixes FVP_Base_AEMv8A model hang issue with
ARMv8.4+ with cache modelling enabled configuration.
Incorrect L1 cache flush operation to PoU, using CLIDR_EL1
LoUIS field, which is required by the architecture to be
zero for ARMv8.4-A with ARMv8.4-S2FWB feature is replaced
with L1 to L2 and L2 to L3 (if L3 is present) cache flushes.
FVP_Base_AEMv8A model can be configured with L3 enabled by
setting `cluster0.l3cache-size` and `cluster1.l3cache-size`
to non-zero values, and presence of L3 is checked in
`aem_generic_core_pwr_dwn` function by reading
CLIDR_EL1.Ctype3 field value.
Change-Id: If3de3d4eb5ed409e5b4ccdbc2fe6d5a01894a9af
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
Paul Beesley [Fri, 16 Aug 2019 10:24:53 +0000 (10:24 +0000)]
Merge changes from topic "lm/juno_dyn_cfg" into integration
* changes:
Juno: Use shared mbedtls heap between bl1 and bl2
Juno: add basic support for dynamic config