Naga Sureshkumar Relli [Fri, 1 Jul 2016 07:22:41 +0000 (12:52 +0530)]
bl31: Add error reporting registers
This patch adds cpumerrsr_el1 and l2merrsr_el1 to the register dump on
error for applicable CPUs.
These registers hold the ECC errors on L1 and L2 caches.
This patch updates the A53, A57, A72, A73 (l2merrsr_el1 only) CPU libraries.
Signed-off-by: Naga Sureshkumar Relli <nagasure@xilinx.com>
danh-arm [Mon, 4 Jul 2016 17:05:15 +0000 (18:05 +0100)]
Merge pull request #651 from Xilinx/zynqmp_uart
zynqmp: Make UART selectable
danh-arm [Mon, 4 Jul 2016 15:32:24 +0000 (16:32 +0100)]
Merge pull request #652 from soby-mathew/sm/pmf_psci_stat
Introduce PMF and implement PSCI STAT APIs
Soby Mathew [Mon, 23 May 2016 15:07:53 +0000 (16:07 +0100)]
Enable PSCI_STAT_COUNT/RESIDENCY for ARM standard platforms
This patch enables optional PSCI functions `PSCI_STAT_COUNT` and
`PSCI_STAT_RESIDENCY` for ARM standard platforms. The optional platform
API 'translate_power_state_by_mpidr()' is implemented for the Juno
platform. 'validate_power_state()' on Juno downgrades PSCI CPU_SUSPEND
requests for the system power level to the cluster power level.
Hence, it is not suitable for validating the 'power_state' parameter
passed in a PSCI_STAT_COUNT/RESIDENCY call.
Change-Id: I9548322676fa468d22912392f2325c2a9f96e4d2
Yatharth Kochar [Mon, 9 May 2016 17:26:35 +0000 (18:26 +0100)]
Add optional PSCI STAT residency & count functions
This patch adds following optional PSCI STAT functions:
- PSCI_STAT_RESIDENCY: This call returns the amount of time spent
in power_state in microseconds, by the node represented by the
`target_cpu` and the highest level of `power_state`.
- PSCI_STAT_COUNT: This call returns the number of times a
`power_state` has been used by the node represented by the
`target_cpu` and the highest power level of `power_state`.
These APIs provides residency statistics for power states that has
been used by the platform. They are implemented according to v1.0
of the PSCI specification.
By default this optional feature is disabled in the PSCI
implementation. To enable it, set the boolean flag
`ENABLE_PSCI_STAT` to 1. This also sets `ENABLE_PMF` to 1.
Change-Id: Ie62e9d37d6d416ccb1813acd7f616d1ddd3e8aff
Yatharth Kochar [Fri, 11 Mar 2016 14:20:19 +0000 (14:20 +0000)]
Add Performance Measurement Framework(PMF)
This patch adds Performance Measurement Framework(PMF) in the
ARM Trusted Firmware. PMF is implemented as a library and the
SMC interface is provided through ARM SiP service.
The PMF provides capturing, storing, dumping and retrieving the
time-stamps, by enabling the development of services by different
providers, that can be easily integrated into ARM Trusted Firmware.
The PMF capture and retrieval APIs can also do appropriate cache
maintenance operations to the timestamp memory when the caller
indicates so.
`pmf_main.c` consists of core functions that implement service
registration, initialization, storing, dumping and retrieving
the time-stamp.
`pmf_smc.c` consists SMC handling for registered PMF services.
`pmf.h` consists of the macros that can be used by the PMF service
providers to register service and declare time-stamp functions.
`pmf_helpers.h` consists of internal macros that are used by `pmf.h`
By default this feature is disabled in the ARM trusted firmware.
To enable it set the boolean flag `ENABLE_PMF` to 1.
NOTE: The caller is responsible for specifying the appropriate cache
maintenance flags and for acquiring/releasing appropriate locks
before/after capturing/retrieving the time-stamps.
Change-Id: Ib45219ac07c2a81b9726ef6bd9c190cc55e81854
Soren Brinkmann [Fri, 10 Jun 2016 16:57:14 +0000 (09:57 -0700)]
zynqmp: Add option to select between Cadence UARTs
Add build time option 'cadence1' for ZYNQMP_CONSOLE to select the 2nd
UART available in the SoC.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
danh-arm [Wed, 15 Jun 2016 14:57:02 +0000 (15:57 +0100)]
Merge pull request #650 from Xilinx/zynqmp-updates
Zynqmp updates
Soren Brinkmann [Thu, 9 Jun 2016 20:36:27 +0000 (13:36 -0700)]
build_macros: Add 'add_define_val' macro
Add a convenience macro to add a build definition with a value.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
danh-arm [Mon, 13 Jun 2016 12:50:58 +0000 (13:50 +0100)]
Merge pull request #629 from ljerry/tf_issue_398
Bring IO storage dummy driver
danh-arm [Mon, 13 Jun 2016 10:27:31 +0000 (11:27 +0100)]
Merge pull request #648 from ashutoshksingh/integration
opteed: assume aarch64 for optee
danh-arm [Mon, 13 Jun 2016 10:09:08 +0000 (11:09 +0100)]
Merge pull request #646 from davwan01/dw/gicv3-wakeup
CSS: Add support to wake up the core from wfi in GICv3
danh-arm [Mon, 13 Jun 2016 10:08:19 +0000 (11:08 +0100)]
Merge pull request #635 from jenswi-linaro/qemu
Add support for QEMU virt ARMv8-A
Ashutosh Singh [Fri, 27 May 2016 14:51:17 +0000 (15:51 +0100)]
opteed: assume aarch64 for optee
OPTEE to execute in aarch64 bit mode, set it accordingly
when execution transitions from EL3 to EL1
Change-Id: I59f2f940bdc1aac10543045b006a137d107ec95f
Signed-off-by: Ashutosh Singh <ashutosh.singh@arm.com>
Jens Wiklander [Mon, 7 Dec 2015 13:37:10 +0000 (14:37 +0100)]
Add support for QEMU virt ARMv8-A target
This patch adds support for the QEMU virt ARMv8-A target.
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
danh-arm [Wed, 8 Jun 2016 15:06:43 +0000 (16:06 +0100)]
Merge pull request #642 from soby-mathew/sm/override_rotpk
Allow dynamic overriding of ROTPK verification
danh-arm [Wed, 8 Jun 2016 12:30:03 +0000 (13:30 +0100)]
Merge pull request #643 from sandrine-bailleux-arm/sb/checkpatch-conf-file
Move checkpatch options in a configuration file
danh-arm [Wed, 8 Jun 2016 12:20:35 +0000 (13:20 +0100)]
Merge pull request #639 from danh-arm/dh/import-libfdt
Import libfdt v1.4.1 and related changes
David Wang [Tue, 7 Jun 2016 01:22:40 +0000 (09:22 +0800)]
CSS: Add support to wake up the core from wfi in GICv3
In GICv3 mode, the non secure group1 interrupts are signalled via the
FIQ line in EL3. To support waking up from CPU_SUSPEND to standby on
these systems, EL3 should route FIQ to EL3 temporarily before wfi and
restore the original setting after resume. This patch makes this change
for the CSS platforms in the `css_cpu_standby` psci pm ops hook.
Change-Id: Ibf3295d16e2f08da490847c1457bc839e1bac144
Mirela Simonovic [Tue, 7 Jun 2016 16:15:40 +0000 (18:15 +0200)]
zynqmp: pm: Added NODE_IPI_APU slave node ID in pm_defs.h
NODE_IPI_APU is the node ID of APU's IPI device. If APU should be
woken-up on an IPI from FPD power down, this node shall be set as
the wake-up source upon suspend.
Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
danh-arm [Tue, 7 Jun 2016 08:35:02 +0000 (09:35 +0100)]
Merge pull request #645 from sandrine-bailleux-arm/sb/improve-load-image-comments
Update comments in load_image()
Sandrine Bailleux [Fri, 27 May 2016 13:08:10 +0000 (14:08 +0100)]
Update comments in load_image()
- Fix the function documentation.
Since commit
16948ae1, load_image() uses image IDs rather than image
names.
- Clarify the consequences of a null entry point argument.
- Slightly reorganize the code to remove an unnecessary 'if' statement.
Change-Id: Iebea3149a37f23d3b847a37a206ed23f7e8ec717
danh-arm [Mon, 6 Jun 2016 09:54:28 +0000 (10:54 +0100)]
Merge pull request #644 from sandrine-bailleux-arm/sb/rm-outdated-comment
xlat lib: Remove out-dated comment
Sandrine Bailleux [Thu, 2 Jun 2016 10:19:59 +0000 (11:19 +0100)]
Move checkpatch options in a configuration file
At the moment, the top Makefile specifies the options to pass to the
checkpatch script in order to check the coding style. The checkpatch
script also supports reading its options from a configuration file
rather than from the command line.
This patch makes use of this feature and moves the checkpatch options
out of the Makefile. This simplifies the Makefile and makes things
clearer.
This patch also adds some more checkpatch options:
--showfile
--ignore FILE_PATH_CHANGES
--ignore AVOID_EXTERNS
--ignore NEW_TYPEDEFS
--ignore VOLATILE
The rationale behind each of these options has been documented
in the configuration file.
Change-Id: I423e1abe5670c0f57046cbf705f89a8463898676
Soby Mathew [Tue, 24 May 2016 14:05:15 +0000 (15:05 +0100)]
Allow dynamic overriding of ROTPK verification
A production ROM with TBB enabled must have the ability to boot test software
before a real ROTPK is deployed (e.g. manufacturing mode). Previously the
function plat_get_rotpk_info() must return a valid ROTPK for TBB to succeed.
This patch adds an additional bit `ROTPK_NOT_DEPLOYED` in the output `flags`
parameter from plat_get_rotpk_info(). If this bit is set, then the ROTPK
in certificate is used without verifying against the platform value.
Fixes ARM-software/tf-issues#381
Change-Id: Icbbffab6bff8ed76b72431ee21337f550d8fdbbb
danh-arm [Fri, 3 Jun 2016 16:27:45 +0000 (17:27 +0100)]
Merge pull request #641 from antonio-nino-diaz-arm/an/fvp-set-nv-ctr
Implement plat_set_nv_ctr for FVP platforms
danh-arm [Fri, 3 Jun 2016 16:26:59 +0000 (17:26 +0100)]
Merge pull request #640 from sandrine-bailleux-arm/sb/fix-syntax-error
Fix a syntax error in plat/arm/common/aarch64/arm_common.c
danh-arm [Fri, 3 Jun 2016 14:12:51 +0000 (15:12 +0100)]
Merge pull request #637 from yatharth-arm/yk/genfw-1134
Add support for ARM Cortex-A73 MPCore Processor
danh-arm [Fri, 3 Jun 2016 14:12:37 +0000 (15:12 +0100)]
Merge pull request #636 from soby-mathew/sm/cpu_ctx_rem_aarch32_regs
Build option to include AArch32 registers in cpu context
Sandrine Bailleux [Fri, 3 Jun 2016 14:00:46 +0000 (15:00 +0100)]
Fix a syntax error
Building TF with ERROR_DEPRECATED=1 fails because of a missing
semi-column. This patch fixes this syntax error.
Change-Id: I98515840ce74245b0a0215805f85c8e399094f68
Dan Handley [Thu, 2 Jun 2016 14:28:23 +0000 (15:28 +0100)]
Minor libfdt changes to enable TF integration
* Move libfdt API headers to include/lib/libfdt
* Add libfdt.mk helper makefile
* Remove unused libfdt files
* Minor changes to fdt.h and libfdt.h to make them C99 compliant
Co-Authored-By: Jens Wiklander <jens.wiklander@linaro.org>
Change-Id: I425842c2b111dcd5fb6908cc698064de4f77220e
Dan Handley [Thu, 2 Jun 2016 13:23:40 +0000 (14:23 +0100)]
Import libfdt v1.4.1
Imports libfdt code from https://git.kernel.org/cgit/utils/dtc/dtc.git
tag "v1.4.1" commit
302fca9f4c283e1994cf0a5a9ce1cf43ca15e6d2.
Change-Id: Ia0d966058beee55a9047e80d8a05bbe4f71d8446
Dan Handley [Thu, 2 Jun 2016 17:21:02 +0000 (18:21 +0100)]
Exclude more files from checkpatch and checkcodebase
Exclude documentation files from the `make checkcodebase` target
(these files were already excluded from checkpatch).
Also exclude libfdt files to prepare for import of this library.
Change-Id: Iee597ed66494de2b11cf84096f771f1f04472d5b
Dan Handley [Thu, 2 Jun 2016 16:15:13 +0000 (17:15 +0100)]
Move stdlib header files to include/lib/stdlib
* Move stdlib header files from include/stdlib to include/lib/stdlib for
consistency with other library headers.
* Fix checkpatch paths to continue excluding stdlib files.
* Create stdlib.mk to define the stdlib source files and include directories.
* Include stdlib.mk from the top level Makefile.
* Update stdlib header path in the fip_create Makefile.
* Update porting-guide.md with the new paths.
Change-Id: Ia92c2dc572e9efb54a783e306b5ceb2ce24d27fa
Antonio Nino Diaz [Fri, 20 May 2016 13:14:16 +0000 (14:14 +0100)]
Implement plat_set_nv_ctr for FVP platforms
Replaced placeholder implementation of plat_set_nv_ctr for FVP
platforms by a working one.
On FVP, the mapping of region DEVICE2 has been changed from RO to RW
to prevent exceptions when writing to the NV counter, which is
contained in this region.
Change-Id: I56a49631432ce13905572378cbdf106f69c82f57
Soby Mathew [Tue, 17 May 2016 13:01:32 +0000 (14:01 +0100)]
Build option to include AArch32 registers in cpu context
The system registers that are saved and restored in CPU context include
AArch32 systems registers like SPSR_ABT, SPSR_UND, SPSR_IRQ, SPSR_FIQ,
DACR32_EL2, IFSR32_EL2 and FPEXC32_EL2. Accessing these registers on an
AArch64-only (i.e. on hardware that does not implement AArch32, or at
least not at EL1 and higher ELs) platform leads to an exception. This patch
introduces the build option `CTX_INCLUDE_AARCH32_REGS` to specify whether to
include these AArch32 systems registers in the cpu context or not. By default
this build option is set to 1 to ensure compatibility. AArch64-only platforms
must set it to 0. A runtime check is added in BL1 and BL31 cold boot path to
verify this.
Fixes ARM-software/tf-issues#386
Change-Id: I720cdbd7ed7f7d8516635a2ec80d025f478b95ee
Sandrine Bailleux [Tue, 31 May 2016 15:47:29 +0000 (16:47 +0100)]
xlat lib: Remove out-dated comment
As of commit
e1ea9290bb, if the attributes of an inner memory region
are different than the outer region, new page tables are generated
regardless of how "restrictive" they are. This patch removes an
out-dated comment still referring to the old priority system based
on which attributes were more restrictive.
Change-Id: Ie7fc1629c90ea91fe50315145f6de2f3995e5e00
Yatharth Kochar [Tue, 9 Feb 2016 12:00:03 +0000 (12:00 +0000)]
Add support for ARM Cortex-A73 MPCore Processor
This patch adds ARM Cortex-A73 MPCore Processor support
in the CPU specific operations framework. It also includes
this support for the Base FVP port.
Change-Id: I0e26b594f2ec1d28eb815db9810c682e3885716d
Soren Brinkmann [Sun, 29 May 2016 16:48:44 +0000 (09:48 -0700)]
zynqmp: Remove double ';'
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Soren Brinkmann [Sun, 29 May 2016 16:48:26 +0000 (09:48 -0700)]
zynqmp: Fix spelling of endianness
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
danh-arm [Fri, 27 May 2016 13:10:42 +0000 (14:10 +0100)]
Merge pull request #632 from rockchip-linux/support-for-gpio-driver-v2
rockchip/rk3399: Support the gpio driver and configure
danh-arm [Fri, 27 May 2016 10:11:47 +0000 (11:11 +0100)]
Merge pull request #634 from sandrine-bailleux-arm/sb/exception-vectors
Improve robustness and readability of exception code
danh-arm [Fri, 27 May 2016 10:08:45 +0000 (11:08 +0100)]
Merge pull request #633 from soby-mathew/sm/psci_wfi_hook
PSCI: Add pwr_domain_pwr_down_wfi() hook in plat_psci_ops
danh-arm [Fri, 27 May 2016 10:07:20 +0000 (11:07 +0100)]
Merge pull request #627 from soby-mathew/sm/fvp_ccn502_sup_1
Add CCN support to FVP
Caesar Wang [Wed, 25 May 2016 11:05:19 +0000 (19:05 +0800)]
rockchip: support system off function for rk3399
if define power off gpio, BL31 will do system power off through
gpio control.
Caesar Wang [Wed, 25 May 2016 11:04:47 +0000 (19:04 +0800)]
rockchip: support reset SoC through gpio for rk3399
If define a reset gpio, BL31 will use gpio to reset SOC,
otherwise use CRU reset.
Caesar Wang [Wed, 25 May 2016 11:03:04 +0000 (19:03 +0800)]
rockchip: add reset or power off gpio configuration for rk3399
We add plat parameter structs to support BL2 to pass variable-length,
variable-type parameters to BL31. The parameters are structured as a
link list. During bl31 setup time, we travse the list to process each
parameter. throuth this way, we can get the reset or power off gpio
parameter, and do hardware control in BL31. This structure also can
pass other parameter to BL31 in future.
Caesar Wang [Wed, 25 May 2016 11:21:43 +0000 (19:21 +0800)]
rockchip: support rk3399 gpio driver
There are 5 groups of GPIO (GPIO0~GPIO4), totally have 122 GPIOs
on rk3399 platform.
The pull direction(pullup or pulldown) for all of GPIOs are
software-programmable.
At the moment, we add the gpio basic driver since reset or power off
the devices from gpio configuration for BL31.
Caesar Wang [Wed, 25 May 2016 10:48:45 +0000 (18:48 +0800)]
gpio: support gpio set/get pull status
On some platform gpio can set/get pull status when input, add these
function so we can set/get gpio pull status when need it. And they are
optional function.
Sandrine Bailleux [Tue, 24 May 2016 15:22:59 +0000 (16:22 +0100)]
Fill exception vectors with zero bytes
The documentation of the GNU assembler specifies the following about
the .align assembler directive:
"the padding bytes are normally zero. However, on some systems, if
the section is marked as containing code and the fill value is
omitted, the space is filled with no-op instructions."
(see https://sourceware.org/binutils/docs/as/Align.html)
When building Trusted Firmware, the AArch64 GNU assembler uses a
mix of zero bytes and no-op instructions as the padding bytes to
align exception vectors.
This patch mandates to use zero bytes to be stored in the padding
bytes in the exception vectors. In the AArch64 instruction set, no
valid instruction encodes as zero so this effectively inserts
illegal instructions. Should this code end up being executed for
any reason, it would crash immediately. This gives us an extra
protection against misbehaving code at no extra cost.
Change-Id: I4f2abb39d0320ca0f9d467fc5af0cb92ae297351
Sandrine Bailleux [Tue, 24 May 2016 15:56:03 +0000 (16:56 +0100)]
Introduce some helper macros for exception vectors
This patch introduces some assembler macros to simplify the
declaration of the exception vectors. It abstracts the section
the exception code is put into as well as the alignments
constraints mandated by the ARMv8 architecture. For all TF images,
the exception code has been updated to make use of these macros.
This patch also updates some invalid comments in the exception
vector code.
Change-Id: I35737b8f1c8c24b6da89b0a954c8152a4096fa95
Soren Brinkmann [Thu, 19 May 2016 14:20:14 +0000 (07:20 -0700)]
zynqmp: PSCI: Wait for FW completing wake requests
Powering up cores didn't wait for the PMUFW to complete the request,
which could result in cores failing to power up in Linux.
Reported-by: Koteswararao Nayudu <kotin@xilinx.com>
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Soby Mathew [Wed, 27 Apr 2016 13:46:28 +0000 (14:46 +0100)]
PSCI: Add pwr_domain_pwr_down_wfi() hook in plat_psci_ops
This patch adds a new optional platform hook `pwr_domain_pwr_down_wfi()` in
the plat_psci_ops structure. This hook allows the platform to perform platform
specific actions including the wfi invocation to enter powerdown. This hook
is invoked by both psci_do_cpu_off() and psci_cpu_suspend_start() functions.
The porting-guide.md is also updated for the same.
This patch also modifies the `psci_power_down_wfi()` function to invoke
`plat_panic_handler` incase of panic instead of the busy while loop.
Fixes ARM-Software/tf-issues#375
Change-Id: Iba104469a1445ee8d59fb3a6fdd0a98e7f24dfa3
Soby Mathew [Thu, 24 Mar 2016 10:12:42 +0000 (10:12 +0000)]
Add CCN support to FVP platform port
This patch adds support to select CCN driver for FVP during build.
A new build option `FVP_INTERCONNECT_DRIVER` is added to allow
selection between the CCI and CCN driver. Currently only the CCN-502
variant is supported on FVP.
The common ARM CCN platform helper file now verifies the cluster
count declared by platform is equal to the number of root node
masters exported by the ARM Standard platform.
Change-Id: I71d7b4785f8925ed499c153b2e9b9925fcefd57a
Soby Mathew [Wed, 23 Mar 2016 17:14:57 +0000 (17:14 +0000)]
CCN: Add API to query the PART0 ID from CCN
This patch adds the API `ccn_get_part0_id` to query the PART0 ID from the
PERIPHERAL_ID 0 register in the CCN driver. This ID allows to distinguish
the variant of CCN present on the system and possibly enable dynamic
configuration of the IP based on the variant. Also added an assert in
`ccn_master_to_rn_id_map()` to ensure that the master map bitfield provided
by the platform is within the expected interface id.
Change-Id: I92d2db7bd93a9be8a7fbe72a522cbcba0aba2d0e
Soren Brinkmann [Fri, 20 May 2016 14:05:00 +0000 (07:05 -0700)]
zynqmp: Ignore the revision field of the IDCODE
The revision field may change between silicon revisions without changing
the mapping to a part. This avoids errors like:
ERROR: Incorrect XILINX IDCODE 0x14738093, maskid 0x4600093
NOTICE: ATF running on XCZUUNKN/EP108 v3/RTL5.1 at 0xfffe5000
on parts with a newer revision.
Reported-by: Love Kumar <love.kumar@xilinx.com>
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Alistair Francis <alistair.francis@xilinx.com>
Tested-by: Love Kumar <love.kumar@xilinx.com>
Stefan Krsmanovic [Fri, 20 May 2016 13:51:09 +0000 (15:51 +0200)]
zynqmp: Add bakery_lock to protect APU_PWRCTRL register access
Access to APU_PWRCTRL register is protected during suspend/wakeup pocedure
in order to save valid state. If more than one CPU is accessing this register
it can be left in corrupted state during read-modify-write process.
Signed-off-by: Stefan Krsmanovic <stefan.krsmanovic@aggios.com>
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Stefan Krsmanovic [Fri, 20 May 2016 13:51:08 +0000 (15:51 +0200)]
zynqmp: Put pm_secure_lock in coherent memory region
DEFINE_BAKERY_LOCK() macro is used to put lock in coherent memory region.
ARM Trusted Firmware design guide, chapter 11 states that bakery_lock data
structures should be allocated in coherent memory region because it is
accessed by multiple CPUs with mismatched shareability, cacheability and
memory attributes.
Signed-off-by: Stefan Krsmanovic <stefan.krsmanovic@aggios.com>
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Anes Hadziahmetagic [Thu, 12 May 2016 14:17:34 +0000 (16:17 +0200)]
zynqmp: pm: Implement pm_register_notifier PM API function
Signed-off-by: Anes Hadziahmetagic <anes.hadziahmetagic@aggios.com>
Signed-off-by: Filip Drazic <filip.drazic@aggios.com>
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Anes Hadziahmetagic [Thu, 12 May 2016 14:17:30 +0000 (16:17 +0200)]
zynqmp: pm: Implemented 'get_op_characteristic' PM API call
Signed-off-by: Anes Hadziahmetagic <anes.hadziahmetagic@aggios.com>
Signed-off-by: Filip Drazic <filip.drazic@aggios.com>
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Filip Drazic [Thu, 12 May 2016 14:17:31 +0000 (16:17 +0200)]
zynqmp: pm: Removed double declaration of pm_ipi_send functions
Functions pm_ipi_send and pm_ipi_send_sync are declared in pm_ipi.h
Signed-off-by: Filip Drazic <filip.drazic@aggios.com>
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Soren Brinkmann [Fri, 22 Apr 2016 17:02:46 +0000 (10:02 -0700)]
zynqmp: Reduce mapped memory area
The GIC area is specified larger than it needs to be and can be reduced.
Which allows reducing the structures required for the translation tables
as well.
This results in a reduction of memory footprint of ca. 4k.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
danh-arm [Tue, 24 May 2016 15:12:08 +0000 (16:12 +0100)]
Merge pull request #625 from antonio-nino-diaz-arm/an/delay-timer-v2
Implement generic delay timer and use it on platforms
Antonio Nino Diaz [Thu, 5 May 2016 14:25:02 +0000 (15:25 +0100)]
Replace Rockchip delay timer by generic one
Use the generic delay timer instead of having a specific platform
file for configuring it.
Change-Id: Ifa68b9c97cd96ae1190cee74d22d729af95e4537
Antonio Nino Diaz [Thu, 5 May 2016 14:23:56 +0000 (15:23 +0100)]
Replace MediaTek delay timer by generic one
Use the generic delay timer instead of having a specific platform
file for configuring it.
Change-Id: If6b8f60bc04230f4b85b2bcc1b670fc65461214e
Antonio Nino Diaz [Tue, 17 May 2016 08:48:10 +0000 (09:48 +0100)]
Replace SP804 timer by generic delay timer on FVP
Added a build flag to select the generic delay timer on FVP instead
of the SP804 timer. By default, the generic one will be selected. The
user guide has been updated.
Change-Id: Ica34425c6d4ed95a187b529c612f6d3b26b78bc6
Antonio Nino Diaz [Wed, 18 May 2016 09:37:25 +0000 (10:37 +0100)]
Implement generic delay timer
Add delay timer implementation based on the system generic counter.
This either uses the platform's implementation of
`plat_get_syscnt_freq()` or explicit clock multiplier/divider values
provided by the platform.
The current implementation of udelay has been modified to avoid
unnecessary calculations while waiting on the loop and to make it
easier to check for overflows.
Change-Id: I9062e1d506dc2f68367fd9289250b93444721732
Antonio Nino Diaz [Thu, 19 May 2016 09:00:28 +0000 (10:00 +0100)]
Implement plat_get_syscnt_freq2 on platforms
Replaced plat_get_syscnt_freq by plat_get_syscnt_freq2 on all
upstream platforms.
Change-Id: I3248f3f65a16dc5e9720012a05c35b9e3ba6abbe
Antonio Nino Diaz [Wed, 18 May 2016 15:53:31 +0000 (16:53 +0100)]
Add 32 bit version of plat_get_syscnt_freq
Added plat_get_syscnt_freq2, which is a 32 bit variant of the 64 bit
plat_get_syscnt_freq. The old one has been flagged as deprecated.
Common code has been updated to use this new version. Porting guide
has been updated.
Change-Id: I9e913544926c418970972bfe7d81ee88b4da837e
Gerald Lejeune [Tue, 21 Jul 2015 12:15:12 +0000 (14:15 +0200)]
Bring IO storage dummy driver
Allow to handle cases where some images are pre-loaded (by debugger for
instance) without introducing many switches in files calling load_* functions.
Fixes: arm-software/tf-issues#398
Signed-off-by: Gerald Lejeune <gerald.lejeune@st.com>
danh-arm [Thu, 12 May 2016 14:04:44 +0000 (15:04 +0100)]
Merge pull request #622 from mtk09422/hw-crypt-v3
Hw crypt v3
Yi Zheng [Wed, 11 May 2016 10:45:20 +0000 (18:45 +0800)]
MT8173: Add Sip function for MTK HW crypt driver
Change-Id: Idc40cc6243e532567ec4334ae37d97c003c90bfa
Signed-off-by: Yi Zheng <yi.zheng@mediatek.com>
Jimmy Huang [Wed, 11 May 2016 10:04:09 +0000 (18:04 +0800)]
mt8173: Reorganize plat SiP functions
Due to the changes in Mediatek platform common code, we need to move
plat related SiP functions to plat folder.
Change-Id: I6b14b988235205a5858b4bf49043bc79d0512b06
Signed-off-by: Jimmy Huang <jimmy.huang@mediatek.com>
danh-arm [Wed, 11 May 2016 09:56:25 +0000 (10:56 +0100)]
Merge pull request #619 from sandrine-bailleux-arm/sb/rockchip-assertions
Rockchip: Add some debug assertions in the PMU driver
Sandrine Bailleux [Thu, 5 May 2016 09:04:15 +0000 (10:04 +0100)]
Rockchip: Add some debug assertions in the PMU driver
This patch adds some debug assertions ensuring that array indices
are within the bounds of the array.
Change-Id: I96ee81d14834c1e92cdfb7e60b49995cdacfd93a
danh-arm [Wed, 4 May 2016 16:10:31 +0000 (17:10 +0100)]
Merge pull request #618 from rockchip-linux/fixes-for-suspend/resume
rockchip: support the suspend/resume for rk3399
danh-arm [Wed, 4 May 2016 12:47:49 +0000 (13:47 +0100)]
Merge pull request #617 from leon-chen-mtk/refactor_common_1
Refactor MediaTek platform common code
Caesar Wang [Sun, 10 Apr 2016 06:11:07 +0000 (14:11 +0800)]
rockchip: support the suspend/resume for rk3399
This patch adds to support the suspend/resume for rk3399 SoCs.
Signed-off-by: Shengfei xu <xsf@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
danh-arm [Wed, 4 May 2016 09:32:41 +0000 (10:32 +0100)]
Merge pull request #614 from soby-mathew/sm/rem_fvp_ve_memmap
FVP: Remove VE memory map support and change default GIC driver
Leon Chen [Thu, 28 Apr 2016 06:07:42 +0000 (14:07 +0800)]
Refactor MediaTek platform common code
Refactor MediaTek platform common code for further mt6795 upstream.
Soby Mathew [Thu, 7 Apr 2016 16:40:04 +0000 (17:40 +0100)]
Change the default driver to GICv3 in FVP
This patch changes the default driver for FVP platform from the deprecated
GICv3 legacy to the GICv3 only driver. This means that the default build of
Trusted Firmware will not be able boot Linux kernel with GICv2 FDT blob. The
user guide is also updated to reflect this change of default GIC driver for
FVP.
Change-Id: Id6fc8c1ac16ad633dabb3cd189b690415a047764
Soby Mathew [Wed, 13 Jan 2016 17:06:00 +0000 (17:06 +0000)]
Remove support for legacy VE memory map in FVP
This patch removes support for legacy Versatile Express memory map for the
GIC peripheral in the FVP platform. The user guide is also updated for the
same.
Change-Id: Ib8cfb819083aca359e5b46b5757cb56cb0ea6533
danh-arm [Wed, 27 Apr 2016 11:31:23 +0000 (12:31 +0100)]
Merge pull request #597 from hzhuang1/emmc_v3.2
Emmc v3
Haojian Zhuang [Fri, 18 Mar 2016 14:08:26 +0000 (22:08 +0800)]
drivers: add emmc stack
In a lot of embedded platforms, eMMC device is the only one storage
device. So loading content from eMMC device is required in ATF.
Create the emmc stack that could co-work with IO block driver.
Support to read/write/erase eMMC blocks on both rpmb and normal
user area. Support to change the IO speed and bus width.
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Haojian Zhuang [Thu, 21 Apr 2016 02:52:52 +0000 (10:52 +0800)]
Document: add MAX_IO_BLOCK_DEVICES platform macro
Add MAX_IO_BLOCK_DEVICES in porting guide. It's necessary to define
this macro to support io block device. With this macro, multiple
block devices could be opened at the same time. Each block device
stores its own state.
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Haojian Zhuang [Fri, 18 Mar 2016 07:14:19 +0000 (15:14 +0800)]
IO: support block device type
FIP is accessed as memory-mapped type. eMMC is block device type.
In order to support FIP based on eMMC, add the new io_block layer.
io_block always access eMMC device as block size. And it'll only
copy the required data into buffer in io_block driver. So preparing
an temporary buffer is required.
When use io_block device, MAX_IO_BLOCK_DEVICES should be declared
in platform_def.h. It's used to support multiple block devices.
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
danh-arm [Wed, 27 Apr 2016 08:58:56 +0000 (09:58 +0100)]
Merge pull request #612 from sandrine-bailleux-arm/sb/fix-xlat-lib-path
Doc: Fix the path to the xlat lib
danh-arm [Wed, 27 Apr 2016 08:40:05 +0000 (09:40 +0100)]
Merge pull request #610 from bjackman/bj/fip-create-exit-code
fip_create: Fix exit status for missing output filename (2)
danh-arm [Wed, 27 Apr 2016 08:38:40 +0000 (09:38 +0100)]
Merge pull request #611 from sandrine-bailleux-arm/sb/fix-init_xlation_table_inner
Fix computation of L1 bitmask in the translation table lib
Sandrine Bailleux [Tue, 26 Apr 2016 13:49:57 +0000 (14:49 +0100)]
Doc: Fix the path to the xlat lib
The translation table library code has moved from lib/aarch64/ to
lib/xlat_tables/ since commit
3ca9928df but the Porting Guide still
points to the old location. This patch fixes this issue.
Change-Id: I983a9a100d70eacf6bac71725ffbb4bb5f3732b0
Brendan Jackman [Mon, 25 Apr 2016 07:35:35 +0000 (15:35 +0800)]
fip_create: Fix exit status for missing output filename
Change-Id: I0d298eea9eaf47121c87637c7395e5d9868aa272
Sandrine Bailleux [Fri, 22 Apr 2016 09:47:33 +0000 (10:47 +0100)]
Fix computation of L1 bitmask in the translation table lib
This patch fixes the computation of the bitmask used to isolate
the level 1 field of a virtual address. The whole computation needs
to work on 64-bit values to produce the correct bitmask value.
XLAT_TABLE_ENTRIES_MASK being a C constant, it is a 32-bit value
so it needs to be extended to a 64-bit value before it takes part
in any other computation.
This patch fixes this bug by casting XLAT_TABLE_ENTRIES_MASK as
an unsigned long long.
Note that this bug doesn't manifest itself in practice because
address spaces larger than 39 bits are not yet supported in the
Trusted Firmware.
Change-Id: I955fd263ecb691ca94b29b9c9f576008ce1d87ee
danh-arm [Tue, 26 Apr 2016 13:58:57 +0000 (14:58 +0100)]
Merge pull request #605 from yatharth-arm/yk/sys_counter_fix
Conditionally compile `plat_get_syscnt_freq()` in ARM standard platforms
Yatharth Kochar [Tue, 26 Apr 2016 09:36:29 +0000 (10:36 +0100)]
Conditionally compile `plat_get_syscnt_freq()` in ARM standard platforms
This patch puts the definition of `plat_get_syscnt_freq()`
under `#ifdef ARM_SYS_CNTCTL_BASE` in arm_common.c file.
This is the fix for compilation error introduced by commit-id
`
749ade4`, for platforms that use arm_common.c but do not
provide a memory mapped interface to the generic counter.
Fixes ARM-software/tf-issues#395
Change-Id: I2f2b10bd9500fa15308541ccb15829306a76a745
Michal Simek [Mon, 15 Jun 2015 12:22:50 +0000 (14:22 +0200)]
zynqmp: FSBL->ATF handover
Parse the parameter structure the FSBL populates, to populate the bl32
and bl33 image structures.
Cc: Sarat Chand Savitala <saratcha@xilinx.com>
Cc: petalinux-dev@xilinx.com
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
[ SB
- pass pointers to structs instead of structs
- handle execution state parameter
- populate bl32 SPSR
- add documentation
- query bootmode and consider missing handoff parameters an error when
not in JTAG boot mode
]
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Soren Brinkmann [Mon, 18 Apr 2016 18:49:42 +0000 (11:49 -0700)]
zynqmp: Introduce zynqmp_get_bootmode
Provide a function to retrieve the bootmode.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Soren Brinkmann [Mon, 18 Apr 2016 18:27:48 +0000 (11:27 -0700)]
zynqmp: Remove bogus comment
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Soren Brinkmann [Thu, 14 Apr 2016 17:27:00 +0000 (10:27 -0700)]
zynqmp: Revise memory configuration options
Drop the current configuration options for selecting the location of
the ATF and TSP (ZYNQMP_ATF_LOCATION, ZYNQMP_TSP_RAM_LOCATION).
The new configuration provides one default setup (ATF in OCM,
BL32 in DRAM). Additionally, the new configuration options
- ZYNQMP_ATF_MEM_BASE
- ZYNQMP_ATF_MEM_SIZE
- ZYNQMP_BL32_MEM_BASE
- ZYNQMP_BL32_MEM_SIZE
can be used to freely configure the memory locations used for ATF and
secure payload.
Also, allow setting the BL33 entry point via PRELOADED_BL33_BASE.
Cc: petalinux-dev@xilinx.com
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Alistair Francis <alistair.francis@xilinx.com>
danh-arm [Mon, 25 Apr 2016 13:52:14 +0000 (14:52 +0100)]
Merge pull request #604 from sandrine-bailleux-arm/sb/validate-psci_cpu_on_start-args
Validate psci_cpu_on_start() arguments
danh-arm [Mon, 25 Apr 2016 13:50:46 +0000 (14:50 +0100)]
Merge pull request #602 from rockchip-linux/fixes-for-coreboot_v1
rockchip: fixes for the required