Antonio Nino Diaz [Tue, 5 Apr 2016 10:38:49 +0000 (11:38 +0100)]
Remove BL32_BASE when building without SPD for FVP
Previously, when building TF without SPD support, BL2 tried to load a
BL32 image from the FIP and fails to find one, which resulted on
warning messages on the console. Even if there is a BL32 image in the
FIP it shouldn't be loaded because there is no way to transfer
control to the Secure Payload without SPD support.
The Makefile has been modified to pass a define of the form
SPD_${SPD} to the source code the same way it's done for PLAT. The
define SPD_none is then used to undefine BL32_BASE when BL32 is not
used to prevent BL2 from trying to load a BL32 image and failing,
thus removing the warning messages mentioned above.
Fixes ARM-software/tf-issues#287
Change-Id: Ifeb6f1c26935efb76afd353fea88e87ba09e9658
danh-arm [Wed, 6 Apr 2016 11:43:33 +0000 (12:43 +0100)]
Merge pull request #581 from rockchip-linux/rockchip-atf-
20160405
Support for Rockchip's family SoCs
Tony Xie [Fri, 15 Jan 2016 09:17:32 +0000 (17:17 +0800)]
Support for Rockchip's family SoCs
This patch adds to support the RK3368 and RK3399 SoCs.
RK3368/RK3399 is one of the Rockchip family SoCs, which is an
multi-cores ARM SoCs.
This patch adds support to boot the Trusted Firmware on RK3368/RK3399
SoCs, and adds support to boot secondary CPUs, enter/exit core
power states for all CPUs in the slow/fast clusters.
This is the initial version for rockchip SoCs.(RK3368/RK3399 and next SoCs)
* Support arm gicv2 & gicv3.
* Boot up multi-cores CPU.
* Add generic CPU helper functions.
* Support suspend/resume.
* Add system_off & system_reset implementation.
* Add delay timer platform implementation.
* Support the new porting interface for the PSCI implementation.
Change-Id: I704bb3532d65e8c70dbd99b512c5e6e440ea6f43
Signed-off-by: Tony Xie <tony.xie@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Shengfei xu <xsf@rock-chips.com>
danh-arm [Mon, 4 Apr 2016 12:39:32 +0000 (13:39 +0100)]
Merge pull request #580 from soby-mathew/sm/ret_type_plat_ns_ep
Modify return type of plat_get_ns_image_entrypoint()
Soby Mathew [Wed, 23 Mar 2016 10:11:10 +0000 (10:11 +0000)]
Modify return type of plat_get_ns_image_entrypoint()
This patch modifies the return type of the platform API
`plat_get_ns_image_entrypoint()` from `unsigned long` to
`uintptr_t` in accordance with the coding guidelines.
Change-Id: Icb4510ca98b706aa4d535fe27e203394184fb4ca
danh-arm [Fri, 1 Apr 2016 16:41:10 +0000 (17:41 +0100)]
Merge pull request #577 from antonio-nino-diaz-arm/an/remove-xlat-helpers
Remove xlat_helpers.c
danh-arm [Fri, 1 Apr 2016 16:40:54 +0000 (17:40 +0100)]
Merge pull request #576 from mtk09422/bl31-security
mt8173: Protect BL31 memory from non-secure access
Jimmy Huang [Tue, 29 Mar 2016 09:42:41 +0000 (17:42 +0800)]
mt8173: Protect BL31 memory from non-secure access
BL31 usually handles confidential stuff, its memory must not be
read/write accessible from non-secure world. This patch protects
the BL31 memory range from non-secure read/write access.
Change-Id: I442fb92b667bb2f9a62d471a90508b1ba4489911
Signed-off-by: Jimmy Huang <jimmy.huang@mediatek.com>
Antonio Nino Diaz [Thu, 31 Mar 2016 08:08:56 +0000 (09:08 +0100)]
Remove xlat_helpers.c
lib/aarch64/xlat_helpers.c defines helper functions to build
translation descriptors, but no common code or upstream platform
port uses them. As the rest of the xlat_tables code evolves, there
may be conflicts with these helpers, therefore this code should be
removed.
Change-Id: I9f5be99720f929264818af33db8dada785368711
danh-arm [Thu, 31 Mar 2016 10:42:14 +0000 (11:42 +0100)]
Merge pull request #570 from davwan01/bl31-in-dram
Add support to load BL31 in DRAM
danh-arm [Thu, 31 Mar 2016 08:39:45 +0000 (09:39 +0100)]
Merge pull request #554 from ljerry/tf_issue_368_ter
Enable asynchronous abort exceptions during boot
David Wang [Mon, 7 Mar 2016 03:02:57 +0000 (11:02 +0800)]
Add support to load BL31 in DRAM
This patch adds an option to the ARM common platforms to load BL31 in the
TZC secured DRAM instead of the default secure SRAM.
To enable this feature, set `ARM_BL31_IN_DRAM` to 1 in build options.
If TSP is present, then setting this option also sets the TSP location
to DRAM and ignores the `ARM_TSP_RAM_LOCATION` build flag.
To use this feature, BL2 platform code must map in the DRAM used by
BL31. The macro ARM_MAP_BL31_SEC_DRAM is provided for this purpose.
Currently, only the FVP BL2 platform code maps in this DRAM.
Change-Id: If5f7cc9deb569cfe68353a174d4caa48acd78d67
Gerald Lejeune [Tue, 22 Mar 2016 10:11:46 +0000 (11:11 +0100)]
Add ISR_EL1 to crash report
Bring ISR bits definition as a mnemonic for troublershooters as well.
Signed-off-by: Gerald Lejeune <gerald.lejeune@st.com>
Gerald Lejeune [Tue, 22 Mar 2016 10:07:04 +0000 (11:07 +0100)]
Remove DAIF bits handling macros
These macros are unused and redundant with other CPU system registers
functions.
Moreover enable_serror() function implementation may not reach its purpose
because it does not handle the value of SCR_EL3.EA.
Signed-off-by: Gerald Lejeune <gerald.lejeune@st.com>
Gerald Lejeune [Tue, 22 Mar 2016 08:29:23 +0000 (09:29 +0100)]
Enable asynchronous abort exceptions during boot
Asynchronous abort exceptions generated by the platform during cold boot are
not taken in EL3 unless SCR_EL3.EA is set.
Therefore EA bit is set along with RES1 bits in early BL1 and BL31 architecture
initialisation. Further write accesses to SCR_EL3 preserve these bits during
cold boot.
A build flag controls SCR_EL3.EA value to keep asynchronous abort exceptions
being trapped by EL3 after cold boot or not.
For further reference SError Interrupts are also known as asynchronous external
aborts.
On Cortex-A53 revisions below r0p2, asynchronous abort exceptions are taken in
EL3 whatever the SCR_EL3.EA value is.
Fixes arm-software/tf-issues#368
Signed-off-by: Gerald Lejeune <gerald.lejeune@st.com>
danh-arm [Tue, 29 Mar 2016 14:39:01 +0000 (15:39 +0100)]
Merge pull request #561 from antonio-nino-diaz-arm/an/bootwrapper
Enable preloaded BL33 alternative boot flow
danh-arm [Tue, 29 Mar 2016 14:29:47 +0000 (15:29 +0100)]
Merge pull request #560 from sandrine-bailleux-arm/sb/restructure-doc
Simplify Firmware Design document
danh-arm [Tue, 29 Mar 2016 14:26:46 +0000 (15:26 +0100)]
Merge pull request #559 from soby-mathew/sm/cpu_ops_verbose_log
Make cpu operations warning a VERBOSE print
Sandrine Bailleux [Tue, 26 Jan 2016 15:00:40 +0000 (15:00 +0000)]
Simplify Firmware Design document
The Firmware Design document is meant to provide a general overview
of the Trusted Firmware code. Although it is useful to provide some
guidance around the responsibilities of the platform layer, it should
not provide too much platform specific implementation details. Right
now, some sections are too tied to the implementation on ARM
platforms. This makes the Firmware Design document harder to digest.
This patch simplifies this aspect of the Firmware Design document.
The sections relating the platform initialisations performed by the
different BL stages have been simplified and the extra details about
the ARM platforms implementation have been moved to the Porting Guide
when appropriate.
This patch also provides various documentation fixes and additions
in the Firmware Design and Platform Porting Guide. In particular:
- Update list of SMCs supported by BL1.
- Remove MMU setup from architectural inits, as it is actually
performed by platform code.
- Similarly, move runtime services initialisation, BL2 image
initialization and BL33 execution out of the platform
initialisation paragraph.
- List SError interrupt unmasking as part of BL1 architectural
initialization.
- Mention Trusted Watchdog enabling in BL1 on ARM platforms.
- Fix order of steps in "BL2 image load and execution" section.
- Refresh section about GICv3/GICv2 drivers initialisation on
ARM platforms.
Change-Id: I32113c4ffdc26687042629cd8bbdbb34d91e3c14
Soby Mathew [Mon, 21 Mar 2016 10:36:47 +0000 (10:36 +0000)]
Make cpu operations warning a VERBOSE print
The assembler helper function `print_revision_warning` is used when a
CPU specific operation is enabled in the debug build (e.g. an errata
workaround) but doesn't apply to the executing CPU's revision/part number.
However, in some cases the system integrator may want a single binary to
support multiple platforms with different IP versions, only some of which
contain a specific erratum. In this case, the warning can be emitted very
frequently when CPUs are being powered on/off.
This patch modifies this warning print behaviour so that it is emitted only
when LOG_LEVEL >= LOG_LEVEL_VERBOSE. The `debug.h` header file now contains
guard macros so that it can be included in assembly code.
Change-Id: Ic6e7a07f128dcdb8498a5bfdae920a8feeea1345
danh-arm [Wed, 16 Mar 2016 11:02:54 +0000 (11:02 +0000)]
Merge pull request #552 from antonio-nino-diaz-arm/an/cache-dts
Add cache topology info to FVP DTBs
danh-arm [Wed, 16 Mar 2016 11:02:28 +0000 (11:02 +0000)]
Merge pull request #550 from antonio-nino-diaz-arm/an/dead_loops
Remove all non-configurable dead loops
Antonio Nino Diaz [Mon, 1 Feb 2016 13:57:25 +0000 (13:57 +0000)]
Remove all non-configurable dead loops
Added a new platform porting function plat_panic_handler, to allow
platforms to handle unexpected error situations. It must be
implemented in assembly as it may be called before the C environment
is initialized. A default implementation is provided, which simply
spins.
Corrected all dead loops in generic code to call this function
instead. This includes the dead loop that occurs at the end of the
call to panic().
All unnecesary wfis from bl32/tsp/aarch64/tsp_exceptions.S have
been removed.
Change-Id: I67cb85f6112fa8e77bd62f5718efcef4173d8134
danh-arm [Mon, 14 Mar 2016 16:07:12 +0000 (16:07 +0000)]
Merge pull request #547 from ljerry/tf_issue_371
Add "size" function to IO memmap device driver
Gerald Lejeune [Wed, 18 Mar 2015 13:41:42 +0000 (14:41 +0100)]
Add "size" function to IO memmap device driver
Hence memmap device can be used to load an image without being wrapped in a
FIP.
Fixes arm-software/tf-issues#371
Signed-off-by: Gerald Lejeune <gerald.lejeune@st.com>
danh-arm [Fri, 11 Mar 2016 04:45:46 +0000 (04:45 +0000)]
Merge pull request #546 from mtk09422/mtk-bl31-update
Mtk bl31 update
danh-arm [Fri, 11 Mar 2016 04:45:32 +0000 (04:45 +0000)]
Merge pull request #542 from sandrine-bailleux-arm/km/pt-zero
Initialize all translation table entries
danh-arm [Fri, 11 Mar 2016 04:45:19 +0000 (04:45 +0000)]
Merge pull request #538 from sandrine-bailleux-arm/sb/extend-memory-types
Extend memory attributes to map non-cacheable memory
danh-arm [Wed, 9 Mar 2016 08:45:23 +0000 (08:45 +0000)]
Merge pull request #541 from antonio-nino-diaz-arm/an/secondary-cpu-init
Initialize secondary CPUs during cold boot
danh-arm [Wed, 9 Mar 2016 08:44:47 +0000 (08:44 +0000)]
Merge pull request #540 from antonio-nino-diaz-arm/an/porting_guide
Porting guide: Clarify API that don't follow AAPCS
danh-arm [Wed, 9 Mar 2016 08:44:24 +0000 (08:44 +0000)]
Merge pull request #539 from antonio-nino-diaz-arm/an/fix-std-compilation
Compile stdlib C files individually
Jimmy Huang [Mon, 16 Nov 2015 05:44:31 +0000 (13:44 +0800)]
mt8173: support big core PLL control in system suspend flow
This patch adds big core ARMPLL control in system suspend flow.
Change-Id: I27a45dbbb360f17ff0b524a125630358ee2277e2
Signed-off-by: Louis Yu <louis.yu@mediatek.com>
Signed-off-by: Jimmy Huang <jimmy.huang@mediatek.com>
Jimmy Huang [Fri, 4 Mar 2016 16:53:25 +0000 (00:53 +0800)]
mt8173: Remove gpio driver support
We no longer need to control power signal via gpio during system off,
thus remove gpio driver support from platform code.
Change-Id: I6dfec129fa163330951f37b45b71ba5b90355c3b
Signed-off-by: Jimmy Huang <jimmy.huang@mediatek.com>
Jimmy Huang [Fri, 4 Mar 2016 12:18:58 +0000 (20:18 +0800)]
mt8173: Add #error directive to prevent RESET_TO_BL31
MT8173 platform code is incompatible with RESET_TO_BL31, add #error
directive to prevent the case.
We also move mt8173_def.h and plat_private.h to include directory, and
remove some unnecessary code.
Change-Id: I47b8d0a506820a4ea1fbe8c8fb0ec6c68d88feb5
Signed-off-by: Jimmy Huang <jimmy.huang@mediatek.com>
Antonio Nino Diaz [Tue, 23 Feb 2016 12:04:58 +0000 (12:04 +0000)]
Initialize secondary CPUs during cold boot
The previous reset code in BL1 performed the following steps in
order:
1. Warm/Cold boot detection.
If it's a warm boot, jump to warm boot entrypoint.
2. Primary/Secondary CPU detection.
If it's a secondary CPU, jump to plat_secondary_cold_boot_setup(),
which doesn't return.
3. CPU initialisations (cache, TLB...).
4. Memory and C runtime initialization.
For a secondary CPU, steps 3 and 4 are never reached. This shouldn't
be a problem in most cases, since current implementations of
plat_secondary_cold_boot_setup() either panic or power down the
secondary CPUs.
The main concern is the lack of secondary CPU initialization when
bare metal EL3 payloads are used in case they don't take care of this
initialisation themselves.
This patch moves the detection of primary/secondary CPU after step 3
so that the CPU initialisations are performed per-CPU, while the
memory and the C runtime initialisation are only performed on the
primary CPU. The diagrams used in the ARM Trusted Firmware Reset
Design documentation file have been updated to reflect the new boot
flow.
Platforms ports might be affected by this patch depending on the
behaviour of plat_secondary_cold_boot_setup(), as the state of the
platform when entering this function will be different.
Fixes ARM-software/tf-issues#342
Change-Id: Icbf4a0ee2a3e5b856030064472f9fa6696f2eb9e
Antonio Nino Diaz [Mon, 8 Feb 2016 10:39:42 +0000 (10:39 +0000)]
Porting guide: Clarify API that don't follow AAPCS
This patch clarifies a porting API in the Porting Guide that do not
follow the ARM Architecture Program Calling Standards (AAPCS). The
list of registers that are allowed to be clobbered by this API has
been updated in the Porting Guide.
Fixes ARM-software/tf-issues#259
Change-Id: Ibf2adda2e1fb3e9b8f53d8a918d5998356eb8fce
Kristina Martsenko [Thu, 11 Feb 2016 18:11:56 +0000 (18:11 +0000)]
Initialize all translation table entries
The current translation table code maps in a series of regions, zeroing
the unmapped table entries before and in between the mapped regions. It
doesn't, however, zero the unmapped entries after the last mapped
region, leaving those entries at whatever value that memory has
initially.
This is bad because those values can look like valid translation table
entries, pointing to valid physical addresses. The CPU is allowed to do
speculative reads from any such addresses. If the addresses point to
device memory, the results can be unpredictable.
This patch zeroes the translation table entries following the last
mapped region, ensuring all table entries are either valid or zero
(invalid).
In addition, it limits the value of ADDR_SPACE_SIZE to those allowed by
the architecture and supported by the current code (see D4.2.5 in the
Architecture Reference Manual). This simplifies this patch a lot and
ensures existing code doesn't do unexpected things.
Change-Id: Ic28b6c3f89d73ef58fa80319a9466bb2c7131c21
Sandrine Bailleux [Tue, 1 Mar 2016 14:01:03 +0000 (14:01 +0000)]
Extend memory attributes to map non-cacheable memory
At the moment, the memory translation library allows to create memory
mappings of 2 types:
- Device nGnRE memory (named MT_DEVICE in the library);
- Normal, Inner Write-back non-transient, Outer Write-back
non-transient memory (named MT_MEMORY in the library).
As a consequence, the library code treats the memory type field as a
boolean: everything that is not device memory is normal memory and
vice-versa.
In reality, the ARMv8 architecture allows up to 8 types of memory to
be used at a single time for a given exception level. This patch
reworks the memory attributes such that the memory type is now defined
as an integer ranging from 0 to 7 instead of a boolean. This makes it
possible to extend the list of memory types supported by the memory
translation library.
The priority system dictating memory attributes for overlapping
memory regions has been extended to cope with these changes but the
algorithm at its core has been preserved. When a memory region is
re-mapped with different memory attributes, the memory translation
library examines the former attributes and updates them only if
the new attributes create a more restrictive mapping. This behaviour
is unchanged, only the manipulation of the value has been modified
to cope with the new format.
This patch also introduces a new type of memory mapping in the memory
translation library: MT_NON_CACHEABLE, meaning Normal, Inner
Non-cacheable, Outer Non-cacheable memory. This can be useful to map
a non-cacheable memory region, such as a DMA buffer for example.
The rules around the Execute-Never (XN) bit in a translation table
for an MT_NON_CACHEABLE memory mapping have been aligned on the rules
used for MT_MEMORY mappings:
- If the memory is read-only then it is also executable (XN = 0);
- If the memory is read-write then it is not executable (XN = 1).
The shareability field for MT_NON_CACHEABLE mappings is always set as
'Outer-Shareable'. Note that this is not strictly needed since
shareability is only relevant if the memory is a Normal Cacheable
memory type, but this is to align with the existing device memory
mappings setup. All Device and Normal Non-cacheable memory regions
are always treated as Outer Shareable, regardless of the translation
table shareability attributes.
This patch also removes the 'ATTR_SO' and 'ATTR_SO_INDEX' #defines.
They were introduced to map memory as Device nGnRnE (formerly called
"Strongly-Ordered" memory in the ARMv7 architecture) but were not
used anywhere in the code base. Removing them avoids any confusion
about the memory types supported by the library.
Upstream platforms do not currently use the MT_NON_CACHEABLE memory
type.
NOTE: THIS CHANGE IS SOURCE COMPATIBLE BUT PLATFORMS THAT RELY ON THE
BINARY VALUES OF `mmap_attr_t` or the `attr` argument of
`mmap_add_region()` MAY BE BROKEN.
Change-Id: I717d6ed79b4c845a04e34132432f98b93d661d79
Antonio Nino Diaz [Mon, 22 Feb 2016 16:44:41 +0000 (16:44 +0000)]
Add cache topology info to FVP DTBs
From version 4.0 onwards, the ARM64 Linux kernel expects the device
tree to indicate the cache hierarchy. Failing to provide this
information results in the following warning message to be printed by
the kernel:
`Unable to detect cache hierarchy from DT for CPU x`
All the FVP device trees provided in the TF source tree have been
modified to add this information.
Fixes ARM-software/tf-issues#325
Change-Id: I0ff888992e602b81a0fe1744a86151d625727511
Antonio Nino Diaz [Mon, 15 Feb 2016 14:53:10 +0000 (14:53 +0000)]
Enable preloaded BL33 alternative boot flow
Enable alternative boot flow where BL2 does not load BL33 from
non-volatile storage, and BL31 hands execution over to a preloaded
BL33.
The flag used to enable this bootflow is BL33_BASE, which must hold
the entrypoint address of the BL33 image. The User Guide has been
updated with an example of how to use this option with a bootwrapped
kernel.
Change-Id: I48087421a7b0636ac40dca7d457d745129da474f
Antonio Nino Diaz [Fri, 26 Feb 2016 10:46:44 +0000 (10:46 +0000)]
Compile stdlib C files individually
All C files of stdlib were included into std.c, which was the file
that the Makefile actually compiled. This is a poor way of compiling
all the files and, while it may work fine most times, it's
discouraged.
In this particular case, each C file included its own headers, which
were later included into std.c. For example, this caused problems
because a duplicated typedef of u_short in both subr_prf.c and
types.h. While that may require an issue on its own, this kind of
problems are avoided if all C files are as independent as possible.
Change-Id: I9a7833fd2933003f19a5d7db921ed8542ea2d04a
danh-arm [Fri, 26 Feb 2016 09:47:05 +0000 (09:47 +0000)]
Merge pull request #533 from yatharth-arm/yk/genfw-1292
Fix the inconsistencies in bl1_tbbr_image_descs[]
danh-arm [Fri, 26 Feb 2016 09:45:20 +0000 (09:45 +0000)]
Merge pull request #534 from jcastillo-arm/jc/fix_pl011
Fix potential deadlock in PL011 init function
Juan Castillo [Tue, 23 Feb 2016 17:12:18 +0000 (17:12 +0000)]
Fix potential deadlock in PL011 init function
The PL011 initialization function disables the UART, flushes the FIFO
and waits for the current character to be transmitted before applying
the configuration and enabling the UART. This waiting might result in
a deadlock if the FIFO is disabled while another CPU is printing a
message since the flush of FIFO will never finish.
This patch fixes the problem by removing the flush operation and the
loop for last character completion from the initialization function.
The UART is disabled, configured and enabled again.
Change-Id: I1ca0b6bd9f352c12856f10f174a9f6eaca3ab4ea
Yatharth Kochar [Mon, 1 Feb 2016 11:04:46 +0000 (11:04 +0000)]
Fix the inconsistencies in bl1_tbbr_image_descs[]
This patch fixes inconsistencies in bl1_tbbr_image_descs[]
and miscellaneous fixes in Firmware Update code.
Following are the changes:
* As part of the original FWU changes, a `copied_size`
field was added to `image_info_t`. This was a subtle binary
compatibility break because it changed the size of the
`bl31_params_t` struct, which could cause problems if
somebody used different versions of BL2 or BL31, one with
the old `image_info_t` and one with the new version.
This patch put the `copied_size` within the `image_desc_t`.
* EXECUTABLE flag is now stored in `ep_info.h.attr` in place
of `image_info.h.attr`, associating it to an entrypoint.
* The `image_info.image_base` is only relevant for secure
images that are copied from non-secure memory into secure
memory. This patch removes initializing `image_base` for
non secure images in the bl1_tbbr_image_descs[].
* A new macro `SET_STATIC_PARAM_HEAD` is added for populating
bl1_tbbr_image_descs[].ep_info/image_info.h members statically.
The version, image_type and image attributes are now
populated using this new macro.
* Added PLAT_ARM_NVM_BASE and PLAT_ARM_NVM_SIZE to avoid direct
usage of V2M_FLASH0_XXX in plat/arm/common/arm_bl1_fwu.c.
* Refactoring of code/macros related to SECURE and EXECUTABLE flags.
NOTE: PLATFORM PORTS THAT RELY ON THE SIZE OF `image_info_t`
OR USE the "EXECUTABLE" BIT WITHIN `image_info_t.h.attr`
OR USE THEIR OWN `image_desc_t` ARRAY IN BL1, MAY BE
BROKEN BY THIS CHANGE. THIS IS CONSIDERED UNLIKELY.
Change-Id: Id4e5989af7bf0ed263d19d3751939da1169b561d
danh-arm [Mon, 22 Feb 2016 13:23:49 +0000 (13:23 +0000)]
Merge pull request #532 from soby-mathew/vk/configure_mmap_macros
Rationalise MMU and Page table related constants on ARM platforms
Vikram Kanigiri [Wed, 20 Jan 2016 15:57:35 +0000 (15:57 +0000)]
Rationalise MMU and Page table related constants on ARM platforms
`board_arm_def.h` contains multiple definitions of
`PLAT_ARM_MMAP_ENTRIES` and `MAX_XLAT_TABLES` that are optimised for
memory usage depending upon the chosen build configuration. To ease
maintenance of these constants, this patch replaces their multiple
definitions with a single set of definitions that will work on all ARM
platforms.
Platforms can override the defaults with optimal values by enabling the
`ARM_BOARD_OPTIMISE_MMAP` build option. An example has been provided in
the Juno ADP port.
Additionally, `PLAT_ARM_MMAP_ENTRIES` is increased by one to accomodate
future ARM platforms.
Change-Id: I5ba6490fdd1e118cc9cc2d988ad7e9c38492b6f0
danh-arm [Mon, 22 Feb 2016 10:02:29 +0000 (10:02 +0000)]
Merge pull request #518 from hzhuang1/pl061_gpio_v5
Pl061 gpio v5
danh-arm [Fri, 19 Feb 2016 18:22:08 +0000 (18:22 +0000)]
Merge pull request #525 from antonio-nino-diaz-arm/an/fix-gpio-includes
Fix gpio includes of mt8173 platform to avoid collision.
danh-arm [Fri, 19 Feb 2016 18:21:34 +0000 (18:21 +0000)]
Merge pull request #531 from soby-mathew/sm/multicluster_fvp
Allow multi cluster topology definitions for ARM platforms
Soby Mathew [Mon, 1 Feb 2016 14:04:34 +0000 (14:04 +0000)]
Allow multi cluster topology definitions for ARM platforms
The common topology description helper funtions and macros for
ARM Standard platforms assumed a dual cluster system. This is not
flexible enough to scale to multi cluster platforms. This patch does
the following changes for more flexibility in defining topology:
1. The `plat_get_power_domain_tree_desc()` definition is moved from
`arm_topology.c` to platform specific files, that is `fvp_topology.c`
and `juno_topology.c`. Similarly the common definition of the porting
macro `PLATFORM_CORE_COUNT` in `arm_def.h` is moved to platform
specific `platform_def.h` header.
2. The ARM common layer porting macros which were dual cluster specific
are now removed and a new macro PLAT_ARM_CLUSTER_COUNT is introduced
which must be defined by each ARM standard platform.
3. A new mandatory ARM common layer porting API
`plat_arm_get_cluster_core_count()` is introduced to enable the common
implementation of `arm_check_mpidr()` to validate MPIDR.
4. For the FVP platforms, a new build option `FVP_NUM_CLUSTERS` has been
introduced which allows the user to specify the cluster count to be
used to build the topology tree within Trusted Firmare. This enables
Trusted Firmware to be built for multi cluster FVP models.
Change-Id: Ie7a2e38e5661fe2fdb2c8fdf5641d2b2614c2b6b
danh-arm [Thu, 18 Feb 2016 18:36:00 +0000 (18:36 +0000)]
Merge pull request #523 from jcastillo-arm/jc/genfw-791
ARM platforms: rationalise memory attributes of shared memory
danh-arm [Thu, 18 Feb 2016 18:35:37 +0000 (18:35 +0000)]
Merge pull request #530 from antonio-nino-diaz-arm/an/p_printf
Add support for %p in tf_printf()
danh-arm [Thu, 18 Feb 2016 18:34:33 +0000 (18:34 +0000)]
Merge pull request #529 from sandrine-bailleux/sb/a57-sw-optim-ref
Cortex-A57: Add link to software optimization guide
danh-arm [Thu, 18 Feb 2016 18:34:23 +0000 (18:34 +0000)]
Merge pull request #528 from antonio-nino-diaz-arm/an/user_guide
Move up FVP versions in the user guide
danh-arm [Thu, 18 Feb 2016 18:34:11 +0000 (18:34 +0000)]
Merge pull request #527 from antonio-nino-diaz-arm/an/non_ascii
Remove non-ASCII character from comment
danh-arm [Thu, 18 Feb 2016 18:33:59 +0000 (18:33 +0000)]
Merge pull request #526 from antonio-nino-diaz-arm/an/missing_doc
Add missing build options to the User Guide
danh-arm [Thu, 18 Feb 2016 18:33:39 +0000 (18:33 +0000)]
Merge pull request #524 from jcastillo-arm/jc/tf-issues/319
Improve memory layout documentation
Sandrine Bailleux [Tue, 9 Feb 2016 17:01:37 +0000 (17:01 +0000)]
Cortex-A57: Add link to software optimization guide
This patch adds a link to the Cortex-A57 Software Optimization Guide
in the ARM CPU Specific Build Macros document to justify the default
value of the A57_DISABLE_NON_TEMPORAL_HINT build flag.
Change-Id: I9779e42a4bb118442b2b64717ce143314ec9dd16
Antonio Nino Diaz [Tue, 2 Feb 2016 12:03:38 +0000 (12:03 +0000)]
Add support for %p in tf_printf()
This patch adds support for the `%p` format specifier in tf_printf()
following the example of the printf implementation of the stdlib used
in the trusted firmware.
Fixes ARM-software/tf-issues#292
Change-Id: I0b3230c783f735d3e039be25a9405f00023420da
Juan Castillo [Wed, 13 Jan 2016 15:01:09 +0000 (15:01 +0000)]
ARM platforms: rationalise memory attributes of shared memory
The shared memory region on ARM platforms contains the mailboxes and,
on Juno, the payload area for communication with the SCP. This shared
memory may be configured as normal memory or device memory at build
time by setting the platform flag 'PLAT_ARM_SHARED_RAM_CACHED' (on
Juno, the value of this flag is defined by 'MHU_PAYLOAD_CACHED').
When set as normal memory, the platform port performs the corresponding
cache maintenance operations. From a functional point of view, this is
the equivalent of setting the shared memory as device memory, so there
is no need to maintain both options.
This patch removes the option to specify the shared memory as normal
memory on ARM platforms. Shared memory is always treated as device
memory. Cache maintenance operations are no longer needed and have
been replaced by data memory barriers to guarantee that payload and
MHU are accessed in the right order.
Change-Id: I7f958621d6a536dd4f0fa8768385eedc4295e79f
Antonio Nino Diaz [Wed, 17 Feb 2016 11:00:37 +0000 (11:00 +0000)]
Fix gpio includes of mt8173 platform to avoid collision.
All files including plat/mediatek/mt8173/drivers/gpio/gpio.h were
using system includes instead of user includes, which may cause the
wrong version of the header to be included. Said includes have been
changed to user includes to make sure that the included file is the
wanted one.
Change-Id: I29bdfe96fbd9a7900875e2357bbb43f3ea431fa5
Antonio Nino Diaz [Fri, 5 Feb 2016 11:12:24 +0000 (11:12 +0000)]
Add missing build options to the User Guide
The folowing build options were missing from the User Guide and have been
documented:
- CTX_INCLUDE_FPREGS
- DISABLE_PEDANTIC
- BUILD_STRING
- VERSION_STRING
- BUILD_MESSAGE_TIMESTAMP
Change-Id: I6a9c39ff52cad8ff04deff3ac197af84d437b8b7
danh-arm [Wed, 17 Feb 2016 10:01:03 +0000 (10:01 +0000)]
Merge pull request #522 from danh-arm/vk/rework-interconnect-drivers
Rework use of interconnect drivers
Vikram Kanigiri [Mon, 15 Feb 2016 11:54:14 +0000 (11:54 +0000)]
Rework use of interconnect drivers
ARM Trusted Firmware supports 2 different interconnect peripheral
drivers: CCI and CCN. ARM platforms are implemented using either of the
interconnect peripherals.
This patch adds a layer of abstraction to help ARM platform ports to
choose the right interconnect driver and corresponding platform support.
This is as described below:
1. A set of ARM common functions have been implemented to initialise an
interconnect and for entering/exiting a cluster from coherency. These
functions are prefixed as "plat_arm_interconnect_". Weak definitions of
these functions have been provided for each type of driver.
2.`plat_print_interconnect_regs` macro used for printing CCI registers is
moved from a common arm_macros.S to cci_macros.S.
3. The `ARM_CONFIG_HAS_CCI` flag used in `arm_config_flags` structure
is renamed to `ARM_CONFIG_HAS_INTERCONNECT`.
Change-Id: I02f31184fbf79b784175892d5ce1161b65a0066c
danh-arm [Tue, 16 Feb 2016 12:47:05 +0000 (12:47 +0000)]
Merge pull request #521 from vikramkanigiri/vk/rearchitect_security
Perform security setup separately for each ARM platform
danh-arm [Tue, 16 Feb 2016 12:46:28 +0000 (12:46 +0000)]
Merge pull request #520 from vikramkanigiri/vk/scp_flexibility
Vk/scp flexibility
danh-arm [Tue, 16 Feb 2016 12:45:59 +0000 (12:45 +0000)]
Merge pull request #519 from vikramkanigiri/vk/misc_plat_reorg
Vk/misc plat reorg
Vikram Kanigiri [Thu, 14 Jan 2016 14:26:27 +0000 (14:26 +0000)]
Make SCP_BL2(U) image loading configurable on CSS platforms
Current code mandates loading of SCP_BL2/SCP_BL2U images for all
CSS platforms. On future ARM CSS platforms, the Application
Processor (AP) might not need to load these images. So, these
items can be removed from the FIP on those platforms.
BL2 tries to load SCP_BL2/SCP_BL2U images if their base
addresses are defined causing boot error if the images are not
found in FIP.
This change adds a make flag `CSS_LOAD_SCP_IMAGES` which if set
to `1` does:
1. Adds SCP_BL2, SCP_BL2U images to FIP.
2. Defines the base addresses of these images so that AP loads
them.
And vice-versa if it is set to `0`. The default value is set to
`1`.
Change-Id: I5abfe22d5dc1e9d80d7809acefc87b42a462204a
Vikram Kanigiri [Wed, 10 Feb 2016 14:50:53 +0000 (14:50 +0000)]
Perform security setup separately for each ARM platform
Prior to this patch, it was assumed that on all ARM platforms the bare
minimal security setup required is to program TrustZone protection. This
would always be done by programming the TZC-400 which was assumed to be
present in all ARM platforms. The weak definition of
platform_arm_security_setup() in plat/arm/common/arm_security.c
reflected these assumptions.
In reality, each ARM platform either decides at runtime whether
TrustZone protection needs to be programmed (e.g. FVPs) or performs
some security setup in addition to programming TrustZone protection
(e.g. NIC setup on Juno). As a result, the weak definition of
plat_arm_security_setup() is always overridden.
When a platform needs to program TrustZone protection and implements the
TZC-400 peripheral, it uses the arm_tzc_setup() function to do so. It is
also possible to program TrustZone protection through other peripherals
that include a TrustZone controller e.g. DMC-500. The programmer's
interface is slightly different across these various peripherals.
In order to satisfy the above requirements, this patch makes the
following changes to the way security setup is done on ARM platforms.
1. arm_security.c retains the definition of arm_tzc_setup() and has been
renamed to arm_tzc400.c. This is to reflect the reliance on the
TZC-400 peripheral to perform TrustZone programming. The new file is
not automatically included in all platform ports through
arm_common.mk. Each platform must include it explicitly in a platform
specific makefile if needed.
This approach enables introduction of similar library code to program
TrustZone protection using a different peripheral. This code would be
used by the subset of ARM platforms that implement this peripheral.
2. Due to #1 above, existing platforms which implements the TZC-400 have been
updated to include the necessary files for both BL2, BL2U and BL31
images.
Change-Id: I513c58f7a19fff2e9e9c3b95721592095bcb2735
Vikram Kanigiri [Mon, 8 Feb 2016 16:29:30 +0000 (16:29 +0000)]
Support for varying BOM/SCPI protocol base addresses in ARM platforms
Current code assumes `SCP_COM_SHARED_MEM_BASE` as the base address
for BOM/SCPI protocol between AP<->SCP on all CSS platforms. To
cater for future ARM platforms this is made platform specific.
Similarly, the bit shifts of `SCP_BOOT_CONFIG_ADDR` are also made
platform specific.
Change-Id: Ie8866c167abf0229a37b3c72576917f085c142e8
Vikram Kanigiri [Thu, 12 Nov 2015 18:52:34 +0000 (18:52 +0000)]
Add API to return memory map on ARM platforms
Functions to configure the MMU in S-EL1 and EL3 on ARM platforms
expect each platform to export its memory map in the `plat_arm_mmap`
data structure. This approach does not scale well in case the memory
map cannot be determined until runtime. To cater for this possibility,
this patch introduces the plat_arm_get_mmap() API. It returns a
reference to the `plat_arm_mmap` by default but can be overridden
by a platform if required.
Change-Id: Idae6ad8fdf40cdddcd8b992abc188455fa047c74
Haojian Zhuang [Wed, 3 Feb 2016 14:35:04 +0000 (22:35 +0800)]
Document: add PLAT_PL061_MAX_GPIOS define
ARM PL061 GPIO driver requires the "PLAT_PL061_MAX_GPIOS" definition.
By default, it's defined to 32 in PL061 GPIO driver. If user wants
more PL061 controllers in platform, user should define the build
flag in platform.mk instead.
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Haojian Zhuang [Wed, 27 Jan 2016 05:22:43 +0000 (13:22 +0800)]
arm: gpio: add pl061 driver
Add PL061 GPIO driver that is depend on gpio framework.
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Haojian Zhuang [Wed, 27 Jan 2016 05:18:21 +0000 (13:18 +0800)]
gpio: add gpio framework
Define the gpio ops in gpio driver.
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Vikram Kanigiri [Thu, 12 Nov 2015 17:22:16 +0000 (17:22 +0000)]
Add support for SSC_VERSION register on CSS platforms
Each ARM Compute Subsystem based platform implements a System Security
Control (SSC) Registers Unit. The SSC_VERSION register inside it carries
information to identify the platform. This enables ARM Trusted Firmware
to compile in support for multiple ARM platforms and choose one at
runtime. This patch adds macros to enable access to this register.
Each platform is expected to export its PART_NUMBER separately.
Additionally, it also adds juno part number.
Change-Id: I2b1d5f5b65a9c7b76c6f64480cc7cf0aef019422
Vikram Kanigiri [Thu, 21 Jan 2016 14:08:15 +0000 (14:08 +0000)]
Re-factor definition of some macros on ARM platforms
This patch moves the definition of some macros used only on
ARM platforms from common headers to platform specific headers.
It also forces all ARM standard platforms to have distinct
definitions (even if they are usually the same).
1. `PLAT_ARM_TZC_BASE` and `PLAT_ARM_NSTIMER_FRAME_ID` have been
moved from `css_def.h` to `platform_def.h`.
2. `MHU_BASE` used in CSS platforms is moved from common css_def.h
to platform specific header `platform_def.h` on Juno and
renamed as `PLAT_ARM_MHU_BASE`.
3. To cater for different sizes of BL images, new macros like
`PLAT_ARM_MAX_BL31_SIZE` have been created for each BL image. All
ARM platforms need to define them for each image.
Change-Id: I9255448bddfad734b387922aa9e68d2117338c3f
danh-arm [Thu, 11 Feb 2016 13:26:17 +0000 (13:26 +0000)]
Merge pull request #517 from soby-mathew/sm/gic_set_prio_fix
Fix IPRIORITY and ITARGET accessors in GIC drivers
danh-arm [Thu, 11 Feb 2016 13:25:31 +0000 (13:25 +0000)]
Merge pull request #513 from pgeorgi/configurable-timestamp
build system: allow overriding the build's timestamp
Soby Mathew [Mon, 1 Feb 2016 17:59:22 +0000 (17:59 +0000)]
Move private APIs in gic_common.h to a private header
This patch moves the private GIC common accessors from `gic_common.h` to
a new private header file `gic_common_private.h`. This patch also adds
additional comments to GIC register accessors to highlight the fact
that some of them access register values that correspond to multiple
interrupt IDs. The convention used is that the `set`, `get` and `clr`
accessors access and modify the values corresponding to a single interrupt
ID whereas the `read` and `write` GIC register accessors access the raw
GIC registers and it could correspond to multiple interrupt IDs depending
on the register accessed.
Change-Id: I2643ecb2533f01e3d3219fcedfb5f80c120622f9
Soby Mathew [Fri, 15 Jan 2016 14:20:57 +0000 (14:20 +0000)]
Fix GIC_IPRIORITYR setting in new drivers
The code to set the interrupt priority for secure interrupts in the
new GICv2 and GICv3 drivers is incorrect. The setup code to configure
interrupt priorities of secure interrupts, one interrupt at a time, used
gicd_write_ipriorityr()/gicr_write_ipriority() function affecting
4 interrupts at a time. This bug did not manifest itself because all the
secure interrupts were configured to the highest secure priority(0) during
cold boot and the adjacent non secure interrupt priority would be configured
later by the normal world. This patch introduces new accessors,
gicd_set_ipriorityr() and gicr_set_ipriorityr(), for configuring priority
one interrupt at a time and fixes the the setup code to use the new
accessors.
Fixes ARM-software/tf-issues#344
Change-Id: I470fd74d2b7fce7058b55d83f604be05a27e1341
Soby Mathew [Fri, 15 Jan 2016 14:05:37 +0000 (14:05 +0000)]
Fix race in GIC IPRIORITY and ITARGET accessors
GICD_IPRIORITYR and GICD_ITARGETSR specifically support byte addressing
so that individual interrupt priorities can be atomically updated by
issuing a single byte write. The previous implementation of
gicd_set_ipriority() and gicd_set_itargetsr() used 32-bit register
accesses, modifying values for 4 interrupts at a time, using a
read-modify-write approach. This potentially may cause concurrent changes
by other CPUs to the adjacent interrupts to be corrupted. This patch fixes
the issue by modifying these accessors to use byte addressing.
Fixes ARM-software/tf-issues#343
Change-Id: Iec28b5f5074045b00dfb8d5f5339b685f9425915
danh-arm [Tue, 9 Feb 2016 10:58:13 +0000 (10:58 +0000)]
Merge pull request #516 from vikramkanigiri/vk/ccn-fix-dvm-entry
Bug fix: Rectify logic to enter or exit from DVM domain
danh-arm [Tue, 9 Feb 2016 10:56:53 +0000 (10:56 +0000)]
Merge pull request #515 from soby-mathew/sm/gcc_false_positive
PSCI: Resolve GCC static analysis false positive
danh-arm [Tue, 9 Feb 2016 10:56:09 +0000 (10:56 +0000)]
Merge pull request #514 from sandrine-bailleux/sb/a53-a57-disable-non-temporal-hint
Disable non-temporal hint on Cortex-A53/57
Vikram Kanigiri [Mon, 4 Jan 2016 16:23:22 +0000 (16:23 +0000)]
Bug fix: Rectify logic to enter or exit from DVM domain
Currently, `ccn_snoop_dvm_domain_common()` is responsible for providing
a bitmap of HN-F and HN-I nodes in the interconnect. There is a request
node (RN) corresponding to the master interface (e.g. cluster) that needs
to be added or removed from the snoop/DVM domain. This request node is
removed from or added to each HN-F or HN-I node present in the bitmap
depending upon the type of domain.
The above logic is incorrect when participation of a master interface in
the DVM domain has to be managed. The request node should be removed
from or added to the single Miscellaneous Node (MN) in the system
instead of each HN-I node.
This patch fixes this by removing the intermediate
`ccn_snoop_dvm_domain_common()` and instead reads the MN registers to
get the needed node Id bitmap for snoop(HN-F bitmap) and DVM(MN bitmap)
domains.
Additionally, it renames `MN_DDC_SET_OFF` to `MN_DDC_SET_OFFSET` to
be inline with other macros.
Change-Id: Id896046dd0ccc5092419e74f8ac85e31b104f7a4
Soby Mathew [Tue, 2 Feb 2016 14:23:10 +0000 (14:23 +0000)]
PSCI: Resolve GCC static analysis false positive
When BL31 is compiled at `-O3` optimization level using Linaro GCC 4.9
AArch64 toolchain, it reports the following error:
```
services/std_svc/psci/psci_common.c: In function 'psci_do_state_coordination':
services/std_svc/psci/psci_common.c:220:27: error: array subscript is above
array bounds [-Werror=array-bounds]
psci_req_local_pwr_states[pwrlvl - 1][cpu_idx] = req_pwr_state;
^
```
This error is a false positive and this patch resolves the error by asserting
the array bounds in `psci_do_state_coordination()`.
Fixes ARM-software/tf-issues#347
Change-Id: I3584ed7b2e28faf455b082cb3281d6e1d11d6495
Sandrine Bailleux [Fri, 29 Jan 2016 14:37:58 +0000 (14:37 +0000)]
Cortex-Axx: Unconditionally apply CPU reset operations
In the Cortex-A35/A53/A57 CPUs library code, some of the CPU specific
reset operations are skipped if they have already been applied in a
previous invocation of the reset handler. This precaution is not
required, as all these operations can be reapplied safely.
This patch removes the unneeded test-before-set instructions in
the reset handler for these CPUs.
Change-Id: Ib175952c814dc51f1b5125f76ed6c06a22b95167
Sandrine Bailleux [Wed, 13 Jan 2016 14:57:38 +0000 (14:57 +0000)]
Disable non-temporal hint on Cortex-A53/57
The LDNP/STNP instructions as implemented on Cortex-A53 and
Cortex-A57 do not behave in a way most programmers expect, and will
most probably result in a significant speed degradation to any code
that employs them. The ARMv8-A architecture (see Document ARM DDI
0487A.h, section D3.4.3) allows cores to ignore the non-temporal hint
and treat LDNP/STNP as LDP/STP instead.
This patch introduces 2 new build flags:
A53_DISABLE_NON_TEMPORAL_HINT and A57_DISABLE_NON_TEMPORAL_HINT
to enforce this behaviour on Cortex-A53 and Cortex-A57. They are
enabled by default.
The string printed in debug builds when a specific CPU errata
workaround is compiled in but skipped at runtime has been
generalised, so that it can be reused for the non-temporal hint use
case as well.
Change-Id: I3e354f4797fd5d3959872a678e160322b13867a1
Patrick Georgi [Thu, 28 Jan 2016 13:46:18 +0000 (14:46 +0100)]
build system: allow overriding the build's timestamp
This allows reproducible builds (same source and same compiler produce
bit-identical results) and also allows coordinating the timestamp across
multiple projects, eg. with another firmware.
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Antonio Nino Diaz [Thu, 28 Jan 2016 14:25:56 +0000 (14:25 +0000)]
Move up FVP versions in the user guide
Move up to Base FVP version 7.2 (build 0.8/7202) and Foundation FVP version
9.5 (build 9.5.41) in the user guide.
Change-Id: Ie9900596216808cadf45f042eec639d906e497b2
Antonio Nino Diaz [Wed, 3 Feb 2016 14:41:48 +0000 (14:41 +0000)]
Remove non-ASCII character from comment
Replaced a long dash in a comment by the ASCII character '-'. Support
for multibyte character in the source character set is not enforced by
the C99 standard. To maximize compatibility with C processing tools
(e.g. compilers or static code analysis tools), they should be removed.
Change-Id: Ie318e380d3b44755109f042a76ebfd2229f42ae3
danh-arm [Mon, 1 Feb 2016 19:10:02 +0000 (19:10 +0000)]
Merge pull request #511 from soby-mathew/sm/psci_on_race_v2
Fix PSCI CPU ON race when setting state to ON_PENDING
danh-arm [Mon, 1 Feb 2016 19:06:57 +0000 (19:06 +0000)]
Merge pull request #508 from soby-mathew/sm/debug_xlat
Use tf_printf() for debug logs from xlat_tables.c
danh-arm [Mon, 1 Feb 2016 19:06:03 +0000 (19:06 +0000)]
Merge pull request #504 from sandrine-bailleux/sb/fix-doc-mmap
Porting Guide: Clarify identity-mapping requirement
danh-arm [Mon, 1 Feb 2016 19:05:07 +0000 (19:05 +0000)]
Merge pull request #503 from sandrine-bailleux/sb/clarify-doc-el3-payloads
Clarify EL3 payload documentation
danh-arm [Mon, 1 Feb 2016 19:03:41 +0000 (19:03 +0000)]
Merge pull request #501 from jcastillo-arm/jc/tf-issues/300
Disable PL011 UART before configuring it
Soby Mathew [Tue, 26 Jan 2016 11:47:53 +0000 (11:47 +0000)]
Fix PSCI CPU ON race when setting state to ON_PENDING
When a CPU is powered down using PSCI CPU OFF API, it disables its caches
and updates its `aff_info_state` to OFF. The corresponding cache line is
invalidated by the CPU so that the update will be observed by other CPUs
running with caches enabled. There is a possibility that another CPU
which has been trying to turn ON this CPU via PSCI CPU ON API,
has already seen the update to `aff_info_state` and proceeds to update
the state to ON_PENDING prior to the cache invalidation. This may result
in the update of the state to ON_PENDING being discarded.
This patch fixes this issue by making sure that the update of `aff_info_state`
to ON_PENDING sticks by reading back the value after the cache flush and
retrying it if not updated. The patch also adds a dsbish() to
`psci_do_cpu_off()` to ensure ordering of the update to `aff_info_state`
prior to cache line invalidation.
Fixes ARM-software/tf-issues#349
Change-Id: I225de99957fe89871f8c57bcfc243956e805dcca
danh-arm [Mon, 1 Feb 2016 13:02:25 +0000 (13:02 +0000)]
Merge pull request #497 from mtk09422/spm-v3
update SPM/DCM/MTCMOS related code for power control logic
Juan Castillo [Fri, 4 Dec 2015 12:19:27 +0000 (12:19 +0000)]
Improve memory layout documentation
This patch adds a brief explanation of the top/bottom load approach
to the Firmware Design guide and how Trusted Firmware keeps track of
the free memory at boot time. This will help platform developers to
avoid unexpected results in the memory layout.
Fixes ARM-software/tf-issues#319
Change-Id: I04be7e24c1f3b54d28cac29701c24bf51a5c00ad