openwrt/staging/blogic.git
7 years agodrm/i915/selftests: Use mul_u32_u32() for 32b x 32b -> 64b result
Chris Wilson [Wed, 13 Sep 2017 10:51:54 +0000 (11:51 +0100)]
drm/i915/selftests: Use mul_u32_u32() for 32b x 32b -> 64b result

As realised by commit 9e3d6223d209 ("math64, timers: Fix 32bit
mul_u64_u32_shr() and friends"), GCC does not always generate ideal code
for performing a 32b x 32b multiply returning a 64b result (i.e. where
we idiomatically use u64 result = (u64)x * (u32)x).

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20170913105154.2910-2-chris@chris-wilson.co.uk
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
7 years agodrm/i915: Use mul_u32_u32() for 32b x 32b -> 64b result
Chris Wilson [Wed, 13 Sep 2017 10:51:53 +0000 (11:51 +0100)]
drm/i915: Use mul_u32_u32() for 32b x 32b -> 64b result

As realised by commit 9e3d6223d209 ("math64, timers: Fix 32bit
mul_u64_u32_shr() and friends"), GCC does not always generate ideal code
for performing a 32b x 32b multiply returning a 64b result (i.e. where
we idiomatically use u64 result = (u64)x * (u32)x). This catches a
couple of instances in the display code using (u64)x * (u32)y.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20170913105154.2910-1-chris@chris-wilson.co.uk
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
7 years agodrm/i915: Squelch smatch warning for statement with no effect
Chris Wilson [Wed, 13 Sep 2017 10:57:54 +0000 (11:57 +0100)]
drm/i915: Squelch smatch warning for statement with no effect

The sgt iterators cause an

drivers/gpu/drm/i915/i915_gpu_error.c:846 i915_error_object_create() warn: statement has no effect 7

everywhere they are used. If we change the code slightly, we can achieve
the same increment without altering the output or raising a warning.

   text    data     bss     dec     hex filename
1267906   20587    3168 1291661  13b58d before
1267906   20587    3168 1291661  13b58d after

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170913105754.4423-1-chris@chris-wilson.co.uk
7 years agodrm/i915/guc: Small improvements to guc_wq_item_append
Oscar Mateo [Tue, 12 Sep 2017 21:36:37 +0000 (14:36 -0700)]
drm/i915/guc: Small improvements to guc_wq_item_append

Spare some comments and other small style changes.

Suggested-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1505252197-27696-3-git-send-email-oscar.mateo@intel.com
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
7 years agodrm/i915/guc: Remove WQ_WORKLOAD_SHIFT define
Oscar Mateo [Tue, 12 Sep 2017 21:36:36 +0000 (14:36 -0700)]
drm/i915/guc: Remove WQ_WORKLOAD_SHIFT define

We never used it in i915 and it's going to be removed
in newer GuC firmwares anyway.

Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1505252197-27696-2-git-send-email-oscar.mateo@intel.com
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
7 years agodrm/i915/guc: Name the default GuC scheduling policy
Oscar Mateo [Tue, 12 Sep 2017 21:36:35 +0000 (14:36 -0700)]
drm/i915/guc: Name the default GuC scheduling policy

The default values for the default scheduling policy come from the
GuC firmware itself. Transform the magic numbers into defines.

Suggested-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1505252197-27696-1-git-send-email-oscar.mateo@intel.com
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
7 years agodrm/i915: Move the context descriptor to an inline helper
Chris Wilson [Tue, 12 Sep 2017 21:49:05 +0000 (22:49 +0100)]
drm/i915: Move the context descriptor to an inline helper

The context descriptor is stored inside the per-engine context state, as
we only need to compute it once and access it frequently. However,
currently only intel_lrc.c has easy access, but i915_guc_submission.c
would like to frequently read it as well, and more so only ever needs
the lower 32bits. Make it an inline as the compiler should be able to
retrieve the value in less instructions than it takes to do the function
call:

add/remove: 0/1 grow/shrink: 1/0 up/down: 8/-45 (-37)
function                                     old     new   delta
i915_guc_submit                              621     629      +8
intel_lr_context_descriptor                   45       -     -45

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20170912214905.21987-1-chris@chris-wilson.co.uk
Reviewed-by: Oscar Mateo <oscar.mateo@intel.com>
7 years agodrm/i915/dsi: Replace MIPI command error message with debug message
Mika Kahola [Fri, 1 Sep 2017 07:51:01 +0000 (10:51 +0300)]
drm/i915/dsi: Replace MIPI command error message with debug message

Error message indicating that the same MIPI command is sent
consecutively is perhaps too strongly said. Let's replace that as a
debug message instead.

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1504252261-28964-3-git-send-email-mika.kahola@intel.com
7 years agodrm/i915/cnp: set min brightness from VBT
Lee, Shawn C [Wed, 13 Sep 2017 05:19:20 +0000 (13:19 +0800)]
drm/i915/cnp: set min brightness from VBT

Min brightness value from vbt was missing for CNP platform.
This setting have to refer backlight ic spec to restrict
min backlight output. Without this restriction, driver would
allow to configure lower brightness value and violate
backlight ic requirement.

Fixes: 4c9f7086ac6d ("drm/i915/cnp: Backlight support for CNP.")
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Shawn Lee <shawn.c.lee@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1505279961-16140-1-git-send-email-shawn.c.lee@intel.com
7 years agoRevert "drm/i915/bxt: Disable device ready before shutdown command"
Uma Shankar [Tue, 5 Sep 2017 09:44:31 +0000 (15:14 +0530)]
Revert "drm/i915/bxt: Disable device ready before shutdown command"

This reverts commit bbdf0b2ff32a ("drm/i915/bxt: Disable device ready
before shutdown command").

Disable device ready before shutdown command was added previously to
avoid a split screen issue seen on dual link DSI panels. As of now, dual
link is not supported and will need some rework in the upstream
code. For single link DSI panels, the change is not required. This will
cause failure in sending SHUTDOWN packet during disable. Hence reverting
the change. Will handle the change as part of dual link enabling in
upstream.

Fixes: bbdf0b2ff32a ("drm/i915/bxt: Disable device ready before shutdown command")
Cc: <stable@vger.kernel.org> # v4.12+
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1504604671-17237-1-git-send-email-vidya.srinivas@intel.com
7 years agodrm/i915: Cleanup error paths through eb_lookup_vma()
Chris Wilson [Tue, 12 Sep 2017 15:07:52 +0000 (16:07 +0100)]
drm/i915: Cleanup error paths through eb_lookup_vma()

Following the simplification to a single lookup loop in commit
170fa29b14fa ("drm/i915: Simplify eb_lookup_vmas()") and commit
d1b48c1e7184 ("drm/i915: Replace execbuf vma ht with an idr"), we can go
one step further and reorder the error paths so that the state of the
local variable obj is always known to the compiler and doesn't need the
uninitialized_var markup to squelch a compiler warning.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170912150752.20411-1-chris@chris-wilson.co.uk
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
7 years agodrm/i915/spt+: Don't reset invalid AUX channel interrupt bits in SDEIMR
Dhinakaran Pandiyan [Sat, 9 Sep 2017 00:42:55 +0000 (17:42 -0700)]
drm/i915/spt+: Don't reset invalid AUX channel interrupt bits in SDEIMR

The SDE interrupt bits 25, 26 and 27 are either reserved or meant for
DDI E hotplug in SPT+. These bits are meant for AUX channels only in LPT
and CPT, so add the appropriate checks.

Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170909004255.14827-1-dhinakaran.pandiyan@intel.com
7 years agodrm/i915: Name the IPS_PCODE_CONTROL bit
Ville Syrjälä [Tue, 12 Sep 2017 15:34:11 +0000 (18:34 +0300)]
drm/i915: Name the IPS_PCODE_CONTROL bit

Give a name to the bit which tells pcode to control IPS.

v2: Note that IPS_CTL bits apply to DISPLAY_IPS_CONTROL as well (Chris)

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170912153411.20171-2-ville.syrjala@linux.intel.com
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
7 years agodrm/i915: Nuke some bogus tabs from the pcode defines
Ville Syrjälä [Tue, 12 Sep 2017 15:34:10 +0000 (18:34 +0300)]
drm/i915: Nuke some bogus tabs from the pcode defines

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170912153411.20171-1-ville.syrjala@linux.intel.com
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
7 years agodrm/i915: Factor out setup_private_pat()
Zhi Wang [Tue, 12 Sep 2017 07:42:24 +0000 (15:42 +0800)]
drm/i915: Factor out setup_private_pat()

Factor out setup_private_pat() for introducing the following patches.

Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
Cc: Ben Widawsky <benjamin.widawsky@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Ben Widawsky <benjamin.widawsky@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1505202148-22959-1-git-send-email-zhi.a.wang@intel.com
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
7 years agodrm/i915/bxt: set min brightness from VBT
Lee, Shawn C [Tue, 12 Sep 2017 03:36:30 +0000 (11:36 +0800)]
drm/i915/bxt: set min brightness from VBT

Min brightness value from vbt was missing for BXT platform.
This setting have to refer backlight ic spec to restrict
min backlight output. Without this restriction, driver would
allow to configure lower brightness value and violate
backlight ic requirement.

Fixes: 0fb890c01349 ("drm/i915/bxt: BLC implementation")
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Cooper Chiou <cooper.chiou@intel.com>
Cc: Gary C Wang <gary.c.wang@intel.com>
Signed-off-by: Shawn Lee <shawn.c.lee@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1505187390-7039-1-git-send-email-shawn.c.lee@intel.com
7 years agodrm/i915: Increase poll time for BDW FCLK_DONE
Marta Lofstedt [Fri, 8 Sep 2017 13:28:29 +0000 (16:28 +0300)]
drm/i915: Increase poll time for BDW FCLK_DONE

During IGT testing it has been shown that the specification
defined polling time of 1 us for FCLK_DONE, is sometimes not
enough. The issue is still reproducible while disabling
C-states through the PM QoS framework and also while disabling
preemtion. From this the most plausible explanation is that the
issue is due to a firmware flaw.
As a workaround, it is better to wait a little bit longer for
the FCLK_DONE to come around, than to leave with an DRM_ERROR
and having FCLK_DONE at a randome time after.
While spinning a list of igt tests prone to reproduce the issue
the FCLK_DONE poll failed at approximately 2% of the invocations
of the bdw_set_cdclk function. The longest poll time during this
testing was measured to ~7us. So, the suggested new poll time of
100us is on the safe side.

v2: Added more documentation about investigations done.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102243
Signed-off-by: Marta Lofstedt <marta.lofstedt@intel.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170908132829.6312-1-marta.lofstedt@intel.com
7 years agodrm/i915/psr: Add enable_source vfunc.
Rodrigo Vivi [Thu, 7 Sep 2017 23:00:41 +0000 (16:00 -0700)]
drm/i915/psr: Add enable_source vfunc.

Continue on VLV PSR split with vfunc, let's also create one
for enabling source.

Also since we are touching *_enable_source functions let's
fix a comment with wrong name for vlv's one.

v2: Fix typo on commit message (DK).

Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170907230041.22978-12-rodrigo.vivi@intel.com
7 years agodrm/i915/psr: Add enable_sink vfunc.
Rodrigo Vivi [Thu, 7 Sep 2017 23:00:40 +0000 (16:00 -0700)]
drm/i915/psr: Add enable_sink vfunc.

Continue on VLV PSR split with vfunc, let's also create one
for enabling sink.

v2: Fix typo on commit message (DK).

Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170907230041.22978-11-rodrigo.vivi@intel.com
7 years agodrm/i915/psr: Add setup VSC vfunc.
Rodrigo Vivi [Thu, 7 Sep 2017 23:00:39 +0000 (16:00 -0700)]
drm/i915/psr: Add setup VSC vfunc.

Continue on VLV PSR split with vfunc, let's also create
one for setting up VSC.

v2: Rebased on top of commit d2419ffc10e4 ("drm/i915: Plumb
    crtc_state to PSR enable/disable")

Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170907230041.22978-10-rodrigo.vivi@intel.com
7 years agodrm/i915/psr: Re-org Activate after enable
Rodrigo Vivi [Thu, 7 Sep 2017 23:00:38 +0000 (16:00 -0700)]
drm/i915/psr: Re-org Activate after enable

Let's move the activation calls together after enable is done.

No real functional change should be expected here. Just an attempt
to get it clear when we are really activating PSR after enabling it.

v2: Add braces on if/else because commit message there is too long
    as suggested by Jani.
v3: Rebased on top of commit d2419ffc10e4 ("drm/i915: Plumb
    crtc_state to PSR enable/disable")

Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170907230041.22978-9-rodrigo.vivi@intel.com
7 years agodrm/i915/psr: Move hsw_enable_source after enabling sink.
Rodrigo Vivi [Thu, 7 Sep 2017 23:00:37 +0000 (16:00 -0700)]
drm/i915/psr: Move hsw_enable_source after enabling sink.

No functional change is expected here since at this point
PSR is not allowed to go to any active state. In other
words, not really enabled.

However let's do in a separated patch so it gets clear
on what is change and specially it can helps on bisect
case if we figure something has caused changes in behaviour.

But this needs to be done before we make the vfunc to
enable source to be in parity with VLV implementation.

Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170907230041.22978-8-rodrigo.vivi@intel.com
7 years agodrm/i915/psr: Re-create a hsw_psr_enable_source.
Rodrigo Vivi [Thu, 7 Sep 2017 23:00:36 +0000 (16:00 -0700)]
drm/i915/psr: Re-create a hsw_psr_enable_source.

This sequence is part of enable source anyways, but they
only need to be executed once and not on every activation,
So let's re-create hsw_enable_source.

v2: Avoid changing order here to avoid changing behaviour
    as suggested by Jani.
v3: Rebased on top of commit d2419ffc10e4 ("drm/i915: Plumb
    crtc_state to PSR enable/disable")

Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170907230041.22978-7-rodrigo.vivi@intel.com
7 years agodrm/i915/psr: Unify VSC setup functions.
Rodrigo Vivi [Thu, 7 Sep 2017 23:00:35 +0000 (16:00 -0700)]
drm/i915/psr: Unify VSC setup functions.

VSC package is decided per eDP spec for psr1 or psr2,
and not per platform, so let's unify it and kill "skl"
func.

v2: Rebased on top of commit d2419ffc10e4 ("drm/i915: Plumb
    crtc_state to PSR enable/disable")

Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170907230041.22978-6-rodrigo.vivi@intel.com
7 years agodrm/i915/psr: Add activate vfunc.
Rodrigo Vivi [Thu, 7 Sep 2017 23:00:34 +0000 (16:00 -0700)]
drm/i915/psr: Add activate vfunc.

Continue on VLV PSR split with vfunc, let's move activate
function there.

Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170907230041.22978-5-rodrigo.vivi@intel.com
7 years agodrm/i915/psr: hsw_psr_activate.
Rodrigo Vivi [Thu, 7 Sep 2017 23:00:33 +0000 (16:00 -0700)]
drm/i915/psr: hsw_psr_activate.

On HSW+ the real activate of PSR is decided by the source
after certain amount of configured idle frames.

However for the driver perspective where we track psr.active
variable this function here is the actual activate one. So
let's rename it before moving to vfunc with that.

v2: Fix typo on commit message (DK).

Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170907230041.22978-4-rodrigo.vivi@intel.com
7 years agodrm/i915/psr: vfunc for disabling source.
Rodrigo Vivi [Thu, 7 Sep 2017 23:00:32 +0000 (16:00 -0700)]
drm/i915/psr: vfunc for disabling source.

VLV/CHV has a total different PSR implementation than the
other platforms, so let's start moving that to vfuncs.
Let's start with disable_src one.

v2: Rebased on top of commit d2419ffc10e4 ("drm/i915: Plumb
    crtc_state to PSR enable/disable")

Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170907230041.22978-3-rodrigo.vivi@intel.com
7 years agodrm/i915/psr: Avoid any PSR stuff on platforms without support.
Rodrigo Vivi [Thu, 7 Sep 2017 23:00:31 +0000 (16:00 -0700)]
drm/i915/psr: Avoid any PSR stuff on platforms without support.

We really don't want to setup vfuncs and lock mutexes on
platforms that has no support to PSR.

Also we know what platforms they are so let's do it quietly.

Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170907230041.22978-2-rodrigo.vivi@intel.com
7 years agodrm/i915: Fix an error handling in 'intel_framebuffer_init()'
Christophe JAILLET [Sun, 10 Sep 2017 08:56:42 +0000 (10:56 +0200)]
drm/i915: Fix an error handling in 'intel_framebuffer_init()'

We should go through the error handling path to decrease the
'framebuffer_references' as done everywhere else in this function.

Fixes: 2e2adb05736c ("drm/i915: Add render decompression support")
Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170910085642.13673-1-christophe.jaillet@wanadoo.fr
7 years agodrm/i915: Only initialize partially filled pagetables
Chris Wilson [Fri, 8 Sep 2017 18:16:22 +0000 (19:16 +0100)]
drm/i915: Only initialize partially filled pagetables

If we know that we will completely fill a pagetable (i.e. we are
inserting a complete set of 512 pages), we can skip prefilling that PT
with scratch entries. If we have to abort the insertion prior to writing
the real entries, we will teardown the pagetable and remove it from the
page directory (so that we will restart the allocation next time).

We could do similar tricks for the PD and PDP, but the likelihood of a
single insertion covering the entire 512 entries diminishes, as do the
cycle savings. The saving are even greater (relatively) when we are
preallocating page tables for huge pages, as then we never need to fill
the page table.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Matthew Auld <matthew.auld@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170908181622.17791-1-chris@chris-wilson.co.uk
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
7 years agodrm/i915: Make PAT macros more robust
Michal Wajdeczko [Fri, 8 Sep 2017 16:11:30 +0000 (16:11 +0000)]
drm/i915: Make PAT macros more robust

Macro params shall be wrapped into () to avoid unexpected results.

Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170908161130.22424-1-michal.wajdeczko@intel.com
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
7 years agodrm/i915: Add a default case in gen7 hwsp switch-case
Michel Thierry [Wed, 30 Aug 2017 18:01:15 +0000 (11:01 -0700)]
drm/i915: Add a default case in gen7 hwsp switch-case

Gen7 won't get any new engines, and we already added VCS2 there to just
silence gcc's not handled in switch warnings.

Use a default case instead, otherwise we will need to keep adding extra
cases if changes happen in the future.

v2: Since reaching the default case is impossible, use GEM_BUG_ON (Chris).

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Michel Thierry <michel.thierry@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170830180115.907-1-michel.thierry@intel.com
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
7 years agoMerge tag 'gvt-next-2017-09-08' of https://github.com/01org/gvt-linux into drm-intel...
Jani Nikula [Fri, 8 Sep 2017 07:22:05 +0000 (10:22 +0300)]
Merge tag 'gvt-next-2017-09-08' of https://github.com/01org/gvt-linux into drm-intel-next-queued

gvt-next-2017-09-08

- PCI config sanitize series (Changbin)
- Workload submission error handling series (Fred)

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170908063155.l54lvpivxntjm7hq@zhen-hp.sh.intel.com
7 years agodrm/i915/gvt: Add support for PCIe extended configuration space
Changbin Du [Wed, 23 Aug 2017 06:08:10 +0000 (14:08 +0800)]
drm/i915/gvt: Add support for PCIe extended configuration space

IGD is PCIe device and has extended configuration space. Checking
the binary dump, we can see we have Caps located out of PCI compatible
Configuration Space range.

0x000: 86 80 12 19 17 04 10 00 06 00 00 03 00 00 00 00
0x010: 04 00 00 10 08 00 00 00 0c 00 00 00 08 00 00 00
0x020: 00 00 00 00 00 00 00 00 00 00 00 00 28 10 b9 06
0x030: 00 f8 ff ff 40 00 00 00 00 00 00 00 0b 01 00 00
0x040: 09 70 0c 01 71 26 01 62 c8 00 04 84 00 00 00 00
0x050: c1 00 00 00 39 00 00 00 00 00 00 00 01 00 00 a2
0x060: 00 00 01 00 00 00 00 00 00 00 00 00 00 00 00 00
0x070: 10 ac 92 00 00 80 00 10 00 00 00 00 00 00 00 00
0x080: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x090: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x0a0: 00 00 00 00 00 00 00 00 00 00 00 00 05 d0 01 00
0x0b0: 18 00 e0 fe 00 00 00 00 00 00 00 00 00 00 00 00
0x0c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x0d0: 01 00 22 00 00 80 00 00 00 00 00 00 00 00 00 00
0x0e0: 00 00 00 00 00 00 00 00 00 80 00 00 00 00 00 00
0x0f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x100: 1b 00 01 20 02 14 00 00 00 00 00 00 00 00 00 00
...

Currently, we only emulate the PCI compatible Configuration Space.
This is okay if we attach vGPU to PCI bus. But when we attach to
a PCI Express bus (when Qemu emulates a Intel Q35 chipset which has
PCIe slot), it will not work. Extended Configuration Space is required
for a PCIe device.

This patch extended the virtual configuration space from 256 bytes
to 4KB bytes. So we are to be a *real* PCIe device. And for the
Extended CapList we keep same to physical GPU.

Cc: Laszlo Ersek <lersek@redhat.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Signed-off-by: Changbin Du <changbin.du@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
7 years agodrm/i915/gvt: Fix incorrect PCI BARs reporting
Changbin Du [Fri, 18 Aug 2017 09:49:58 +0000 (17:49 +0800)]
drm/i915/gvt: Fix incorrect PCI BARs reporting

Looking at our virtual PCI device, we can see surprising Region 4 and Region 5.
00:10.0 VGA compatible controller: Intel Corporation Sky Lake Integrated Graphics (rev 06) (prog-if 00 [VGA controller])
        ....
        Region 0: Memory at 140000000 (64-bit, non-prefetchable) [size=16M]
        Region 2: Memory at 180000000 (64-bit, prefetchable) [size=1G]
        Region 4: Memory at <ignored> (32-bit, non-prefetchable)
        Region 5: Memory at <ignored> (32-bit, non-prefetchable)
        Expansion ROM at febd6000 [disabled] [size=2K]

The fact is that we only implemented BAR0 and BAR2. Surprising Region 4 and
Region 5 are shown because we report their size as 0xffffffff. They should
report size 0 instead.

BTW, the physical GPU has a PIO BAR. GVTg hasn't implemented PIO access, so
we ignored this BAR for vGPU device.

v2: fix BAR size value calculation.

Link: https://bugzilla.redhat.com/show_bug.cgi?id=1458032
Signed-off-by: Changbin Du <changbin.du@intel.com>
Cc: stable@vger.kernel.org
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
7 years agodrm/i915/gvt: Refine error handling for perform_bb_shadow
fred gao [Fri, 18 Aug 2017 07:41:11 +0000 (15:41 +0800)]
drm/i915/gvt: Refine error handling for perform_bb_shadow

fix the wrong return type and return error once the unknown
command is scanned.

v2:
- separate this error handle from healthy rating code. (Zhenyu)

Signed-off-by: fred gao <fred.gao@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
7 years agodrm/i915/gvt: Refine error handling in dispatch_workload
fred gao [Fri, 18 Aug 2017 07:41:10 +0000 (15:41 +0800)]
drm/i915/gvt: Refine error handling in dispatch_workload

When an error occurs in dispatch_workload, this patch is to do the
proper cleanup and rollback to the original states before the workload
is abandoned.

v2:
- split the mixed several error paths for better review. (Zhenyu)

v3:
- original PTR_ERR(cs) is good and code cleanup. (Zhenyu)

v4:
- reuse the existing i915_add_request for error handling. (Zhenyu)

v5:
- remove the duplicate error handling release_shadow_wa_ctx and
  move the engine->context_unpin upper. (Zhenyu)

v6:
- keep the old label "out". (Zhenyu)

Signed-off-by: fred gao <fred.gao@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
7 years agodrm/i915/gvt: Refine error handling for intel_vgpu_pin_mm
fred gao [Fri, 18 Aug 2017 07:41:09 +0000 (15:41 +0800)]
drm/i915/gvt: Refine error handling for intel_vgpu_pin_mm

When it is failed in shadow_mm, the pin_count should rollback
to the original states before return.

v2:
- split the mixed several error paths for better review. (Zhenyu)

v3:
  increase the pincount after shadow success. (Zhenyu)

Signed-off-by: fred gao <fred.gao@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
7 years agodrm/i915/gvt: Refine error handling for prepare_execlist_workload
fred gao [Fri, 18 Aug 2017 07:41:08 +0000 (15:41 +0800)]
drm/i915/gvt: Refine error handling for prepare_execlist_workload

refine the error handling for prepare_execlist_workload to restore to the
original states once error occurs.

only release the shadowed batch buffer and wa ctx when the workload is
completed successfully.

v2:
- split the mixed several error paths for better review. (Zhenyu)

v3:
- handle prepare batch buffer/wa ctx pin errors and
- emulate_schedule_in null issue. (Zhenyu)

v4:
- no need to handle emulate_schedule_in null issue. (Zhenyu)

v5:
- release the shadowed batch buffer and wa ctx only for the
  successful workload. (Zhenyu)

v6:
- polish the return style. (Zhenyu)

Signed-off-by: fred gao <fred.gao@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
7 years agodrm/i915/gvt: Add error handling for intel_gvt_scan_and_shadow_workload
fred gao [Fri, 18 Aug 2017 07:41:07 +0000 (15:41 +0800)]
drm/i915/gvt: Add error handling for intel_gvt_scan_and_shadow_workload

When an error occurs after shadow_indirect_ctx, this patch is to do the
proper cleanup and rollback to the original states for shadowed indirect
context before the workload is abandoned.

v2:
- split the mixed several error paths for better review. (Zhenyu)

v3:
- no return check for clean up functions. (Changbin)

v4:
- expose and reuse the existing release_shadow_wa_ctx. (Zhenyu)

v5:
- move the release function to scheduler.c file. (Zhenyu)

v6:
- move error handling code of intel_gvt_scan_and_shadow_workload
  to here. (Zhenyu)

Signed-off-by: fred gao <fred.gao@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
7 years agodrm/i915/gvt: Separate cmd scan from request allocation
fred gao [Fri, 18 Aug 2017 07:41:06 +0000 (15:41 +0800)]
drm/i915/gvt: Separate cmd scan from request allocation

Currently i915 request structure and shadow ring buffer are allocated
before command scan, so it will have to restore to previous states once
any error happens afterwards in the long dispatch_workload path.

This patch is to introduce a reserved ring buffer created at the beginning
of vGPU initialization. Workload will be coped to this reserved buffer and
be scanned first, the i915 request and shadow ring buffer are only
allocated after the result of scan is successful.

To balance the memory usage and buffer alloc time, the coming bigger ring
buffer will be reallocated and kept until more bigger buffer is coming.

v2:
- use kmalloc for the smaller ring buffer, realloc if required. (Zhenyu)

v3:
- remove the dynamically allocated ring buffer. (Zhenyu)

v4:
- code style polish.
- kfree previous allocated buffer once kmalloc failed. (Zhenyu)

Signed-off-by: fred gao <fred.gao@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
7 years agodrm/i915/gvt: Add emulation for BAR2 (aperture) with normal file RW approach
Changbin Du [Tue, 15 Aug 2017 05:14:04 +0000 (13:14 +0800)]
drm/i915/gvt: Add emulation for BAR2 (aperture) with normal file RW approach

For vfio-pci, if the region support MMAP then it should support both
mmap and normal file access. The user-space is free to choose which is
being used. For qemu, we just need add 'x-no-mmap=on' for vfio-pci
option.

Currently GVTg only support MMAP for BAR2. So GVTg will not work when
user turn on x-no-mmap option.

This patch added file style access for BAR2, aka the GPU aperture. We
map the entire aperture partition of active vGPU to kernel space when
guest driver try to enable PCI Memory Space. Then we redirect the file
RW operation from kvmgt to this mapped area.

Link: https://bugzilla.redhat.com/show_bug.cgi?id=1458032
Signed-off-by: Changbin Du <changbin.du@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
7 years agodrm/i915/kvmgt: Sanitize PCI bar emulation
Changbin Du [Tue, 15 Aug 2017 05:20:51 +0000 (13:20 +0800)]
drm/i915/kvmgt: Sanitize PCI bar emulation

For PCI, 64bit bar consumes two BAR registers, but this doesn't mean
both of two BAR are valid. Actually the second BAR is regarded as
reserved in this case. So we shouldn't emulate the second BAR.

Signed-off-by: Changbin Du <changbin.du@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
7 years agodrm/i915: Transform WaDisablePooledEuLoadBalancingFix into a simple register write
Oscar Mateo [Thu, 7 Sep 2017 15:40:09 +0000 (08:40 -0700)]
drm/i915: Transform WaDisablePooledEuLoadBalancingFix into a simple register write

FF_SLICE_CS_CHICKEN2 does not belong to the context image.

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Reviewed-by: Michał Winiarski <michal.winiarski@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1504798809-5653-6-git-send-email-oscar.mateo@intel.com
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
7 years agodrm/i915: Transform WaDisableDynamicCreditSharing into a simple register write
Oscar Mateo [Thu, 7 Sep 2017 15:40:08 +0000 (08:40 -0700)]
drm/i915: Transform WaDisableDynamicCreditSharing into a simple register write

GAMT_CHKN_BIT_REG does not live in the context image.

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Reviewed-by: Michał Winiarski <michal.winiarski@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1504798809-5653-5-git-send-email-oscar.mateo@intel.com
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
7 years agodrm/i915: Transform WaDisableGafsUnitClkGating into a simple reg write
Oscar Mateo [Thu, 7 Sep 2017 15:40:07 +0000 (08:40 -0700)]
drm/i915: Transform WaDisableGafsUnitClkGating into a simple reg write

GEN7_UCGCTL4 does not live in the context.

v2: Missing parenthesis

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Reviewed-by: Michał Winiarski <michal.winiarski@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1504798809-5653-4-git-send-email-oscar.mateo@intel.com
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
7 years agodrm/i915: WaPushConstantDereferenceHoldDisable needs to modify a masked register
Oscar Mateo [Thu, 7 Sep 2017 15:40:06 +0000 (08:40 -0700)]
drm/i915: WaPushConstantDereferenceHoldDisable needs to modify a masked register

So do it correctly.

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Reviewed-by: Michał Winiarski <michal.winiarski@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1504798809-5653-3-git-send-email-oscar.mateo@intel.com
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
7 years agodrm/i915: Transform WaDisableI2mCycleOnWRPort into a simple reg write
Oscar Mateo [Thu, 7 Sep 2017 15:40:05 +0000 (08:40 -0700)]
drm/i915: Transform WaDisableI2mCycleOnWRPort into a simple reg write

GAMT_CHKN_BIT_REG does not live in the context.

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Reviewed-by: Michał Winiarski <michal.winiarski@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1504798809-5653-2-git-send-email-oscar.mateo@intel.com
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
7 years agodrm/i915: Transform WaInPlaceDecompressionHang into a simple reg write
Oscar Mateo [Thu, 7 Sep 2017 15:40:04 +0000 (08:40 -0700)]
drm/i915: Transform WaInPlaceDecompressionHang into a simple reg write

Afaict, GEN9_GAMT_ECO_REG_RW_IA does not live in the context, so writing
it on every context creation is overkill (and wrong).

v2: Missing end parenthesis

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Reviewed-by: Michał Winiarski <michal.winiarski@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1504798809-5653-1-git-send-email-oscar.mateo@intel.com
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
7 years agodrm/i915: Apply the GTT write flush for all !llc machines
Chris Wilson [Thu, 7 Sep 2017 18:45:20 +0000 (19:45 +0100)]
drm/i915: Apply the GTT write flush for all !llc machines

We also see the delayed GTT write issue on i915g/i915gm, so let's
presume that it is a universal problem for all !llc machines, and that we
just haven't yet noticed on g33, gen4 and gen5 machines.

v2: Use a register that exists on all platforms

Testcase: igt/gem_mmap_gtt/coherency # i915gm
References: https://bugs.freedesktop.org/show_bug.cgi?id=102577
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170907184520.5032-1-chris@chris-wilson.co.uk
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
7 years agoi915: Fix obj size vs. alignment for drm_pci_alloc()
Ville Syrjälä [Thu, 7 Sep 2017 14:32:03 +0000 (17:32 +0300)]
i915: Fix obj size vs. alignment for drm_pci_alloc()

drm_pci_alloc() refuses to cooperate if the passed alignment exceeds the
object size. So round up the obj size to the next power of two as well
to make this actually work.

Obviously things work just fine as long as the size was a power of two
to begin with. However kms_cursor_crc doesn't always use power of two
sizes so we hit a failure when we try to allocate the phys memory.

Testcase: igt/kms_cursor_crc
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170907143203.13055-1-ville.syrjala@linux.intel.com
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
7 years agodrm/i915: Disable mmio debugging during user access
Chris Wilson [Thu, 7 Sep 2017 13:44:41 +0000 (14:44 +0100)]
drm/i915: Disable mmio debugging during user access

If the user bypasses i915 and accesses mmio directly, that easily
confuses our automatic mmio debugging (any error we then detect is
likely to be as a result of the user). Since we expect userspace to open
debugfs/i915_forcewake_user if i915.ko is loaded and they want mmio
access, that makes the opportune time to disable our debugging for
duration of the bypass.

v2: Move the fiddling of uncore internals to uncore.c

References: https://bugs.freedesktop.org/show_bug.cgi?id=102543
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170907134441.12881-1-chris@chris-wilson.co.uk
7 years agodrm/i915/skl+: debugfs entry to control IPC
Kumar, Mahesh [Thu, 17 Aug 2017 13:45:29 +0000 (19:15 +0530)]
drm/i915/skl+: debugfs entry to control IPC

This patch creates an entry in debugfs to check the status of IPC.
This can also be used to enable/disable IPC in supported platforms.

Changes since V1:
 - fix use of HAS_IPC
 - use kstrtobool_from_user (Maarten)
 - drm_info log, while enabling IPC (Maarten)

Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170817134529.2839-9-mahesh1.kumar@intel.com
[mlankhorst: enableddisabled -> yesno to match ipc write]

7 years agodrm/i915/bxt+: Enable IPC support
Kumar, Mahesh [Thu, 17 Aug 2017 13:45:28 +0000 (19:15 +0530)]
drm/i915/bxt+: Enable IPC support

This patch adds IPC support. This patch also enables IPC in all supported
platforms based on has_ipc flag.
IPC (Isochronous Priority Control) is the hardware feature, which
dynamically controls the memory read priority of Display.

When IPC is enabled, plane read requests are sent at high priority until
filling above the transition watermark, then the requests are sent at
lower priority until dropping below the level 0 watermark.
The lower priority requests allow other memory clients to have better
memory access. When IPC is disabled, all plane read requests are sent at
high priority.

Changes since V1:
 - Remove commandline parameter to disable ipc
 - Address Paulo's comments
Changes since V2:
 - Address review comments
 - Set ipc_enabled flag
Changes since V3:
 - move ipc_enabled flag assignment inside intel_ipc_enable function
Changes since V4:
 - Re-enable IPC after suspend/resume
Changes since V5:
 - Enable IPC for all gen >=9 except SKL
Changes since V6:
 - fix commit msg
 - after resume program IPC based on SW state.
Changes since V7:
 - Modify IPC support check based on HAS_IPC macro (suggested by Chris)

Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170817134529.2839-8-mahesh1.kumar@intel.com
7 years agodrm/i915/gen9+: Add has_ipc flag in device info structure
Mahesh Kumar [Thu, 17 Aug 2017 13:45:27 +0000 (19:15 +0530)]
drm/i915/gen9+: Add has_ipc flag in device info structure

New Isochronous Priority Control (IPC) capability is introduced in newer
GEN platforms. This patch adds a device info flag to indicate if platform
supports IPC. Patch also sets this flag in supported platforms.

Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170817134529.2839-7-mahesh1.kumar@intel.com
7 years agodrm/i915/cnl: Extend WM workaround with IPC for CNL
Kumar, Mahesh [Thu, 17 Aug 2017 13:45:26 +0000 (19:15 +0530)]
drm/i915/cnl: Extend WM workaround with IPC for CNL

CNL:A & CNL:B have same workaround as KBL to increase wm level latency
by 4us if IPC is enabled.

Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170817134529.2839-6-mahesh1.kumar@intel.com
7 years agodrm/i915/glk: IPC linetime watermark workaround for GLK
Kumar, Mahesh [Thu, 17 Aug 2017 13:45:25 +0000 (19:15 +0530)]
drm/i915/glk: IPC linetime watermark workaround for GLK

IF IPC is enabled LINETIME_WM value should be half of calculated value
 line time = ROUNDDOWN(1/2 * Calculated Line Time)

Earlier code was rounding-up the value, But updated Bspec says we should
take the ROUNDDOWN. This patch corrects that as well.

Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170817134529.2839-5-mahesh1.kumar@intel.com
7 years agodrm/i915/gen10: Calculate and enable transition WM
Kumar, Mahesh [Thu, 17 Aug 2017 13:45:24 +0000 (19:15 +0530)]
drm/i915/gen10: Calculate and enable transition WM

GEN > 9 require transition WM to be programmed if IPC is enabled.
This patch calculates & enable transition WM for supported platforms.
If transition WM is enabled, Plane read requests are sent at high
priority until filling above the transition watermark, then the
requests are sent at lower priority until dropping below the level-0 WM.
The lower priority requests allow other memory clients to have better
memory access.

transition minimum is the minimum amount needed for trans_wm to work to
ensure  the demote does not happen before enough data has been read to
meet the level 0 watermark requirements.

transition amount is configurable value. Higher values will
tend to cause longer periods of high priority reads followed by longer
periods of lower priority reads. Tuning to lower values will tend to
cause shorter periods of high and lower priority reads.

Keeping transition amount to 10 in this patch, as suggested by HW team.

Changes since V1:
 - Address review comments from Maarten

Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
Acked-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170817134529.2839-4-mahesh1.kumar@intel.com
7 years agodrm/i915/skl+: Optimize WM calculation
Kumar, Mahesh [Thu, 17 Aug 2017 13:45:23 +0000 (19:15 +0530)]
drm/i915/skl+: Optimize WM calculation

Plane configuration parameters doesn't change for each WM-level
calculation. Currently we compute same parameters 8 times for each
wm-level.
This patch optimizes it by calculating these parameters in beginning
& reuse during each level-wm calculation.

Changes since V1:
 - rebase on top of Rodrigo's series for CNL

Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
Acked-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170817134529.2839-3-mahesh1.kumar@intel.com
7 years agodrm/i915: Fixed point fixed16 wrapper cleanup
Kumar, Mahesh [Thu, 17 Aug 2017 13:45:22 +0000 (19:15 +0530)]
drm/i915: Fixed point fixed16 wrapper cleanup

As per suggestion from Jani, cleanup the code. Cleanup includes
 - Instead of left shifting & check, compare with U32/16_MAX
 - Use typecast instead of clamp_t

Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170817134529.2839-2-mahesh1.kumar@intel.com
7 years agotools/testing/scatterlist: Test new __sg_alloc_table_from_pages
Tvrtko Ursulin [Wed, 6 Sep 2017 14:55:06 +0000 (15:55 +0100)]
tools/testing/scatterlist: Test new __sg_alloc_table_from_pages

Exercise the new __sg_alloc_table_from_pages API (and through
it also the old sg_alloc_table_from_pages), checking that the
created table has the expected number of segments depending on
the sequence of input pages and other conditions.

v2: Move to data driven for readability.
v3: Add some more testcases and -fsanitize=undefined. (Chris Wilson)

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: linux-kernel@vger.kernel.org
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20170906145506.14952-1-tvrtko.ursulin@linux.intel.com
[tursulin: whitespace fixup]

7 years agodrm/i915: Use __sg_alloc_table_from_pages for userptr allocations
Tvrtko Ursulin [Thu, 3 Aug 2017 09:14:17 +0000 (10:14 +0100)]
drm/i915: Use __sg_alloc_table_from_pages for userptr allocations

With the addition of __sg_alloc_table_from_pages we can control
the maximum coalescing size and eliminate a separate path for
allocating backing store here.

Similar to 871dfbd67d4e ("drm/i915: Allow compaction upto
SWIOTLB max segment size") this enables more compact sg lists to
be created and so has a beneficial effect on workloads with many
and/or large objects of this class.

v2:
 * Rename helper to i915_sg_segment_size and fix swiotlb override.
 * Commit message update.

v3:
 * Actually include the swiotlb override fix.

v4:
 * Regroup parameters a bit. (Chris Wilson)

v5:
 * Rebase for swiotlb_max_segment.
 * Add DMA map failure handling as in abb0deacb5a6
   ("drm/i915: Fallback to single PAGE_SIZE segments for DMA remapping").

v6: Handle swiotlb_max_segment() returning 1. (Joonas Lahtinen)

v7: Rebase.
v8: Commit spelling fix.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: linux-kernel@vger.kernel.org
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170803091417.23677-1-tvrtko.ursulin@linux.intel.com
7 years agolib/scatterlist: Introduce and export __sg_alloc_table_from_pages
Tvrtko Ursulin [Thu, 3 Aug 2017 09:13:51 +0000 (10:13 +0100)]
lib/scatterlist: Introduce and export __sg_alloc_table_from_pages

Drivers like i915 benefit from being able to control the maxium
size of the sg coalesced segment while building the scatter-
gather list.

Introduce and export the __sg_alloc_table_from_pages function
which will allow it that control.

v2: Reorder parameters. (Chris Wilson)
v3: Fix incomplete reordering in v2.
v4: max_segment needs to be page aligned.
v5: Rebase.
v6: Rebase.
v7: Fix spelling in commit and mention max segment size in
    __sg_alloc_table_from_pages kerneldoc. (Andrew Morton)

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: linux-kernel@vger.kernel.org
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Andrew Morton <akpm@linux-foundation.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20170803091351.23594-1-tvrtko.ursulin@linux.intel.com
7 years agolib/scatterlist: Avoid potential scatterlist entry overflow
Tvrtko Ursulin [Thu, 3 Aug 2017 09:13:12 +0000 (10:13 +0100)]
lib/scatterlist: Avoid potential scatterlist entry overflow

Since the scatterlist length field is an unsigned int, make
sure that sg_alloc_table_from_pages does not overflow it while
coalescing pages to a single entry.

v2: Drop reference to future use. Use UINT_MAX.
v3: max_segment must be page aligned.
v4: Do not rely on compiler to optimise out the rounddown.
    (Joonas Lahtinen)
v5: Simplified loops and use post-increments rather than
    pre-increments. Use PAGE_MASK and fix comment typo.
    (Andy Shevchenko)
v6: Commit spelling fix.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: linux-kernel@vger.kernel.org
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Andy Shevchenko <andy.shevchenko@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170803091312.22875-1-tvrtko.ursulin@linux.intel.com
7 years agolib/scatterlist: Fix offset type in sg_alloc_table_from_pages
Tvrtko Ursulin [Mon, 31 Jul 2017 18:55:08 +0000 (19:55 +0100)]
lib/scatterlist: Fix offset type in sg_alloc_table_from_pages

Scatterlist entries have an unsigned int for the offset so
correct the sg_alloc_table_from_pages function accordingly.

Since these are offsets withing a page, unsigned int is
wide enough.

Also converts callers which were using unsigned long locally
with the lower_32_bits annotation to make it explicitly
clear what is happening.

v2: Use offset_in_page. (Chris Wilson)

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Pawel Osciak <pawel@osciak.com>
Cc: Marek Szyprowski <m.szyprowski@samsung.com>
Cc: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Tomasz Stanislawski <t.stanislaws@samsung.com>
Cc: Matt Porter <mporter@kernel.crashing.org>
Cc: Alexandre Bounine <alexandre.bounine@idt.com>
Cc: linux-media@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Acked-by: Marek Szyprowski <m.szyprowski@samsung.com> (v1)
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170731185512.20010-1-tvrtko.ursulin@linux.intel.com
7 years agodrm/i915: Disable snooping (userptr, set-cache-level) on gen4
Chris Wilson [Wed, 6 Sep 2017 19:24:24 +0000 (20:24 +0100)]
drm/i915: Disable snooping (userptr, set-cache-level) on gen4

The original gen4 has an issue where writes (both render and blt) into
snoopable pages are lost. We've previously worked around this in
userspace (ddx, igt) by simply not requesting snoopable buffers, but upon
rediscovering this problem for a third time, make the kernel reject such
requests with -ENODEV.

This disables snooping on userspace buffers for i965g and i965gm (original
gen4) machines.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170906192424.26970-1-chris@chris-wilson.co.uk
7 years agodrm/i915: Update DRIVER_DATE to 20170907
Jani Nikula [Thu, 7 Sep 2017 08:28:20 +0000 (11:28 +0300)]
drm/i915: Update DRIVER_DATE to 20170907

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
7 years agodrm/i915/cnl: WaThrottleEUPerfToAvoidTDBackPressure:cnl(pre-prod)
Rodrigo Vivi [Wed, 6 Sep 2017 22:03:25 +0000 (15:03 -0700)]
drm/i915/cnl: WaThrottleEUPerfToAvoidTDBackPressure:cnl(pre-prod)

Wa for B-stepping only.

A for a hang issue that requires throttling EU performace
to 12.5% to avoid back pressure to thread dispatch

v2: Rebased. No change from v1.

Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Oscar Mateo <oscar.mateo@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170906220325.24524-1-rodrigo.vivi@intel.com
7 years agodrm/i915: Lift has-pinned-pages assert to caller of ____i915_gem_object_get_pages
Chris Wilson [Wed, 6 Sep 2017 13:52:20 +0000 (14:52 +0100)]
drm/i915: Lift has-pinned-pages assert to caller of ____i915_gem_object_get_pages

i915_gem_object_attach_phys() is trying to swap out its shmemfs pages
for a new set of physically contiguous pages, but unfortunately triggers
an assert inside get-pages.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102561
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20170906135220.13508-1-chris@chris-wilson.co.uk
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
7 years agodrm/i915: Display WA #1133 WaFbcSkipSegments:cnl, glk
Rodrigo Vivi [Tue, 5 Sep 2017 19:30:13 +0000 (12:30 -0700)]
drm/i915: Display WA #1133 WaFbcSkipSegments:cnl, glk

Skip compressing 1 segment at the end of the frame,
avoid a pixel count mismatch nuke event when last active
pixel and dummy pixel has same color for Odd Plane
Width / Height.

For both platforms Gemini Lake and Cannon Lake.

v2: Use function-like macro and also use mask to clean
    to make sure bit 11 is 0. (Suggested by Paulo).
v3: Add Display WA notation and also apply for GLK.
    Both Forgotten on v2.
    Using "GLK_" prefix since GLK came before CNL.
v4: Forgot to "|=" when moving directly macro to masked
    val. (Noticed by Paulo.)
v5: Rebased on top of 0a46ddd57c9e ("drm/i915/cnp: Wa 1181:
    Fix Backlight issue")

Cc: Imre Deak <imre.deak@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170905193013.31710-1-rodrigo.vivi@intel.com
7 years agodrm/i915/cnl: Allow the reg_read ioctl to read the RCS TIMESTAMP register
Nanley Chery [Tue, 5 Sep 2017 18:45:07 +0000 (11:45 -0700)]
drm/i915/cnl: Allow the reg_read ioctl to read the RCS TIMESTAMP register

This enables the Mesa driver to advertise support for ARB_timer_query, and
thus an OpenGL version higher than 3.2.

Suggested-by: Ben Widawsky <ben@bwidawsk.net>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170905184507.30046-1-nanley.g.chery@intel.com
7 years agodrm/i915: Move device_info.has_snoop into the static tables
Chris Wilson [Wed, 6 Sep 2017 10:56:53 +0000 (11:56 +0100)]
drm/i915: Move device_info.has_snoop into the static tables

Currently we define any !llc machine as using snoop instead. However,
some platforms run into trouble using snoop that we would like to
disable, and to do so easily we want to be able to use the static
device_info tables.

v2: Leave the old snoop = !llc as a warning for the time being to check
that all stanzas are filled as either llc or snoop.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170906105653.3665-1-chris@chris-wilson.co.uk
7 years agodrm/i915: Disable MI_STORE_DATA_IMM for i915g/i915gm
Chris Wilson [Wed, 6 Sep 2017 15:28:59 +0000 (16:28 +0100)]
drm/i915: Disable MI_STORE_DATA_IMM for i915g/i915gm

The early gen3 machines (i915g/Grantsdale and i915gm/Alviso) share a lot
of characteristics in their MI/GTT blocks with gen2, and in particular
can only use physical addresses in MI_STORE_DATA_IMM. This makes it
incompatible with our usage, so include those two machines in the
blacklist to prevent usage.

v2: Make it easy for gcc and rewrite it as a switch to save some space.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> #v1
Link: https://patchwork.freedesktop.org/patch/msgid/20170906152859.5304-1-chris@chris-wilson.co.uk
7 years agodrm/i915: Re-enable GTT following a device reset
Chris Wilson [Wed, 6 Sep 2017 11:14:05 +0000 (12:14 +0100)]
drm/i915: Re-enable GTT following a device reset

Ville Syrjälä spotted that PGETBL_CTL was losing its enable bit upon a
reset. That was causing the display to show garbage on his 945gm. On my
i915gm the effect was far more severe; re-enabling the display following
the reset without PGETBL_CTL being enabled lead to an immediate hard
hang.

We do have a routine to re-enable PGETBL_CTL which is applicable to
gen2-4, although on gen4 it is documented that a graphics reset doesn't
alter the register (no such wording is given for gen3) and should be safe
to call to punch back in the enable bit. However, that leaves the question
of whether we need to completely re-initialise the register and the
rest of the GSM. For g33/pnv/gen4+, where we do have a configurable
page table, its contents do seem to be kept, and so we should be able to
recover without having to reinitialise the GTT from scratch (as prior to
g33, that register is configured by the BIOS and we leave alone except
for the enable bit).

This appears to have been broken by commit 5fbd0418eef2 ("drm/i915:
Re-enable GGTT earlier during resume on pre-gen6 platforms"), which
moved the intel_enable_gtt() from i915_gem_init_hw() (also used by
reset) to add it earlier during hw init and resume, missing the reset
path.

v2: Find the culprit, rearrange ggtt_enable to be before gem_init_hw to
match init/resume

Reported-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Fixes: 5fbd0418eef2 ("drm/i915: Re-enable GGTT earlier during resume on pre-gen6 platforms")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101852
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Daniel Vetter <daniel@ffwll.ch>
Reviewed-by: Daniel Vetter <daniel@ffwll.ch>
Link: https://patchwork.freedesktop.org/patch/msgid/20170906111405.27110-1-chris@chris-wilson.co.uk
Tested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
7 years agodrm/i915/cnp: Wa 1181: Fix Backlight issue
Rodrigo Vivi [Thu, 31 Aug 2017 04:52:23 +0000 (21:52 -0700)]
drm/i915/cnp: Wa 1181: Fix Backlight issue

This workaround fixes a CNL PCH bug when changing
backlight from a lower frequency to a higher frequency.

During random reboot cycles, display backlight seems to
be off/ dim for 2-3 mins.

The only functional change on this patch is to
set bit 13 of 0xC2020 for CNL PCH.

The rest of patch is organizing identation around
those bits definitions and re-organizing CFL workarounds.

v2: Only add the bit that matters without touching others
    around (Jani).
    Rebase on top of clock gating functions rename.

Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Arthur J Runyan <arthur.j.runyan@intel.com>
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170831045223.3960-1-rodrigo.vivi@intel.com
7 years agodrm/i915: Annotate user relocs with __user
Ville Syrjälä [Fri, 1 Sep 2017 16:54:34 +0000 (19:54 +0300)]
drm/i915: Annotate user relocs with __user

Add the missing __user to the urelocs cast to fix the following sparse
warning:
i915_gem_execbuffer.c:1541:47: warning: cast removes address space of expression
i915_gem_execbuffer.c:1541:62: warning: incorrect type in argument 2 (different address spaces)
i915_gem_execbuffer.c:1541:62:    expected void const [noderef] <asn:1>*from
i915_gem_execbuffer.c:1541:62:    got char *

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Fixes: 2889caa92321 ("drm/i915: Eliminate lots of iterations over the execobjects array")
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170901165434.24636-1-ville.syrjala@linux.intel.com
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> #irc
7 years agodrm/i915: Constify load detect mode
Ville Syrjälä [Thu, 18 May 2017 19:38:37 +0000 (22:38 +0300)]
drm/i915: Constify load detect mode

Make the mode used for load detection const, and adjust all relevant
functions to accept a const mode.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170518193837.393-2-ville.syrjala@linux.intel.com
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
7 years agodrm/i915/perf: Remove __user from u64 in drm_i915_perf_oa_config
Chris Wilson [Fri, 1 Sep 2017 14:57:29 +0000 (15:57 +0100)]
drm/i915/perf: Remove __user from u64 in drm_i915_perf_oa_config

Sparse complains that these integers from which we form void __user *,
and so we don't need the annotation itself inside the uABI.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: Matthew Auld <matthew.auld@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170901145729.21363-2-chris@chris-wilson.co.uk
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
7 years agodrm/i915: Silence sparse by using gfp_t
Chris Wilson [Fri, 1 Sep 2017 14:57:28 +0000 (15:57 +0100)]
drm/i915: Silence sparse by using gfp_t

Sparse enforces that GFP flags are only manipulated inside gfp_t locals.

Fixes: 4d470f7359c4 ("drm/i915: Avoid undefined behaviour of "u32 >> 32"")
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170901145729.21363-1-chris@chris-wilson.co.uk
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
7 years agoMerge drm-upstream/drm-next into drm-intel-next-queued
Jani Nikula [Mon, 4 Sep 2017 18:40:34 +0000 (21:40 +0300)]
Merge drm-upstream/drm-next into drm-intel-next-queued

Catch up with upstream while it's easy.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
7 years agodrm/i915: io unmap functions want __iomem
Ville Syrjälä [Fri, 1 Sep 2017 17:12:52 +0000 (20:12 +0300)]
drm/i915: io unmap functions want __iomem

Don't cast away the __iomem from the io_mapping functions so that
sparse won't be so unhappy when we pass the pointer to the unmap
functions. Instead let's move the cast to where we actually use the
pointer.

Fixes the following sparse warnings:
i915_gem.c:1022:33: warning: incorrect type in argument 1 (different address spaces)
i915_gem.c:1022:33:    expected void [noderef] <asn:2>*vaddr
i915_gem.c:1022:33:    got void *[assigned] vaddr
i915_gem.c:1027:34: warning: incorrect type in argument 1 (different address spaces)
i915_gem.c:1027:34:    expected void [noderef] <asn:2>*vaddr
i915_gem.c:1027:34:    got void *[assigned] vaddr
i915_gem.c:1199:33: warning: incorrect type in argument 1 (different address spaces)
i915_gem.c:1199:33:    expected void [noderef] <asn:2>*vaddr
i915_gem.c:1199:33:    got void *[assigned] vaddr
i915_gem.c:1204:34: warning: incorrect type in argument 1 (different address spaces)
i915_gem.c:1204:34:    expected void [noderef] <asn:2>*vaddr
i915_gem.c:1204:34:    got void *[assigned] vaddr

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170901171252.31025-2-ville.syrjala@linux.intel.com
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
7 years agodrm/i915: Add __rcu to radix tree slot pointer
Ville Syrjälä [Fri, 1 Sep 2017 17:12:51 +0000 (20:12 +0300)]
drm/i915: Add __rcu to radix tree slot pointer

radix_tree_for_each_slot() wants an __rcu annotated pointer for the
slot. So let's add the annotation.

Fixes the following sparse warnings:
i915_gem.c:2217:9: warning: incorrect type in assignment (different address spaces)
i915_gem.c:2217:9:    expected void **slot
i915_gem.c:2217:9:    got void [noderef] <asn:4>**
i915_gem.c:2217:9: warning: incorrect type in assignment (different address spaces)
i915_gem.c:2217:9:    expected void **slot
i915_gem.c:2217:9:    got void [noderef] <asn:4>**
i915_gem.c:2217:9: warning: incorrect type in argument 1 (different address spaces)
i915_gem.c:2217:9:    expected void [noderef] <asn:4>**slot
i915_gem.c:2217:9:    got void **slot
i915_gem.c:2217:9: warning: incorrect type in assignment (different address spaces)
i915_gem.c:2217:9:    expected void **slot
i915_gem.c:2217:9:    got void [noderef] <asn:4>**

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Fixes: 96d776345277 ("drm/i915: Use a radixtree for random access to the object's backing storage")
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170901171252.31025-1-ville.syrjala@linux.intel.com
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
7 years agodrm/i915: Wake up the device for the fbdev setup
Ville Syrjälä [Fri, 1 Sep 2017 19:54:56 +0000 (22:54 +0300)]
drm/i915: Wake up the device for the fbdev setup

Our fbdev setup requires the device to be awake for access
through the GTT. If one boots without connected displays and
later plugs one in, we won't have any runtime PM references when
the fbdev setup runs. Explicitly grab a runtime PM reference during
the fbdev setup to avoid the following spew:

[   62.518435] RPM wakelock ref not held during HW access
[   62.518459] ------------[ cut here ]------------
[   62.518546] WARNING: CPU: 3 PID: 37 at ../drivers/gpu/drm/i915/intel_drv.h:1800 i915_vma_pin_iomap+0x144/0x150 [i915]
[   62.518585] Modules linked in: i915 i2c_algo_bit drm_kms_helper syscopyarea sysfillrect sysimgblt fb_sys_fops drm intel_gtt agpgart netconsole nls_iso8859_1 nls_cp437 vfat fat efi_pstore coretemp hwmon intel_rapl x86_pkg_temp_thermal e1000e efivars ptp pps_core video evdev ip_tables x_tables ipv6 autofs4
[   62.518741] CPU: 3 PID: 37 Comm: kworker/3:1 Not tainted 4.13.0-rc7-skl+ #1077
[   62.518770] Hardware name:                  /NUC7i5BNB, BIOS BNKBL357.86A.0048.2017.0704.1415 07/04/2017
[   62.518827] Workqueue: events i915_hotplug_work_func [i915]
[   62.518853] task: ffff88046c00dc00 task.stack: ffffc90000184000
[   62.518896] RIP: 0010:i915_vma_pin_iomap+0x144/0x150 [i915]
[   62.518919] RSP: 0018:ffffc90000187cc8 EFLAGS: 00010292
[   62.518942] RAX: 000000000000002a RBX: ffff880460044000 RCX: 0000000000000006
[   62.518969] RDX: 0000000000000006 RSI: ffffffff819c3e6f RDI: ffffffff819f1c0e
[   62.518996] RBP: ffffc90000187cd8 R08: ffff88046c00e4f0 R09: 0000000000000000
[   62.519022] R10: ffff8804669ca800 R11: 0000000000000000 R12: ffff880461d20000
[   62.519049] R13: ffffc90000187d48 R14: ffff880461d20000 R15: ffff880460044000
[   62.519076] FS:  0000000000000000(0000) GS:ffff88047ed80000(0000) knlGS:0000000000000000
[   62.519107] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
[   62.519130] CR2: 000056478ae213f0 CR3: 0000000002c0f000 CR4: 00000000003406e0
[   62.519156] Call Trace:
[   62.519190]  intelfb_create+0x176/0x360 [i915]
[   62.519216]  __drm_fb_helper_initial_config_and_unlock+0x1c7/0x3c0 [drm_kms_helper]
[   62.519251]  drm_fb_helper_hotplug_event.part.18+0xac/0xc0 [drm_kms_helper]
[   62.519282]  drm_fb_helper_hotplug_event+0x1a/0x20 [drm_kms_helper]
[   62.519324]  intel_fbdev_output_poll_changed+0x1a/0x20 [i915]
[   62.519352]  drm_kms_helper_hotplug_event+0x27/0x30 [drm_kms_helper]
[   62.519395]  i915_hotplug_work_func+0x24e/0x2b0 [i915]
[   62.519420]  process_one_work+0x1d3/0x6d0
[   62.519440]  worker_thread+0x4b/0x400
[   62.519458]  ? schedule+0x4a/0x90
[   62.519475]  ? preempt_count_sub+0x97/0xf0
[   62.519495]  kthread+0x114/0x150
[   62.519511]  ? process_one_work+0x6d0/0x6d0
[   62.519530]  ? kthread_create_on_node+0x40/0x40
[   62.519551]  ret_from_fork+0x27/0x40
[   62.519569] Code: c4 78 e6 e0 0f ff e9 08 ff ff ff 80 3d d5 bc 0c 00 00 0f 85 0b ff ff ff 48 c7 c7 d8 50 32 a0 c6 05 c1 bc 0c 00 01 e8 9d 78 e6 e0 <0f> ff e9 f1 fe ff ff 0f 1f 44 00 00 0f 1f 44 00 00 0f b6 87 98
[   62.519771] ---[ end trace 5fbe271f991a58ae ]---

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170901195456.6386-1-ville.syrjala@linux.intel.com
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
7 years agodrm/i915: Add interface to reserve fence registers for vGPU
Changbin Du [Mon, 4 Sep 2017 08:01:01 +0000 (16:01 +0800)]
drm/i915: Add interface to reserve fence registers for vGPU

In the past, vGPU alloc fence registers by walking through mm.fence_list
to find fence which pin_count = 0 and vma is empty. vGPU may not find
enough fence registers this way. Because a fence can be bind to vma even
though it is not in using. We have found such failure many times these
days.

An option to resolve this issue is that we can force-remove fence from
vma in this case.

This patch added two new api to the fence management code:
 - i915_reserve_fence() will try to find a free fence from fence_list
   and force-remove vma if need.
 - i915_unreserve_fence() reclaim a reserved fence after vGPU has
   finished.

With this change, the fence management is more clear to work with vGPU.
GVTg do not need remove fence from fence_list in private.

v3: (Chris)
  - Add struct_mutex lock assertion.
  - Only count for unpinned fence.

v2: (Chris)
  - Rename the new api for symmetry.
  - Add safeguard to ensure at least 1 fence remained for host display.

Signed-off-by: Changbin Du <changbin.du@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/1504512061-5892-1-git-send-email-changbin.du@intel.com
Acked-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
7 years agodrm/i915: Use correct path to trace include
Thierry Reding [Fri, 1 Sep 2017 14:49:52 +0000 (16:49 +0200)]
drm/i915: Use correct path to trace include

The header comment in include/trace/define_trace.h specifies that the
TRACE_INCLUDE_PATH needs to be relative to the define_trace.h header
rather than the trace file including it. Most instances get that wrong
and work around it by adding the $(src) directory to the include path.

While this works, it is preferable to refer to the correct path to the
trace file in the first place and avoid any workaround.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Link: https://patchwork.freedesktop.org/patch/msgid/20170901144954.19620-4-thierry.reding@gmail.com
7 years agodrm/i915: Fix the missing PPAT cache attributes on CNL
Zhi Wang [Thu, 31 Aug 2017 19:36:14 +0000 (03:36 +0800)]
drm/i915: Fix the missing PPAT cache attributes on CNL

Add back the GEN8_PPAT_WB cache attributes in cnl_setup_private_ppat(),
which are missed on CNL.

Fixes: 4e34935fcf69 ("drm/i915/cnl: Setup PAT Index.")
Cc: Ben Widawsky <benjamin.widawsky@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Suggested-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1504208177-27784-1-git-send-email-zhi.a.wang@intel.com
7 years agodrm/i915: Fix enum pipe vs. enum transcoder for the PCH transcoder
Ville Syrjälä [Fri, 1 Sep 2017 14:31:23 +0000 (17:31 +0300)]
drm/i915: Fix enum pipe vs. enum transcoder for the PCH transcoder

Use enum pipe for PCH transcoders also in the FIFO underrun code.

Fixes the following new sparse warnings:
intel_fifo_underrun.c:340:49: warning: mixing different enum types
intel_fifo_underrun.c:340:49:     int enum pipe  versus
intel_fifo_underrun.c:340:49:     int enum transcoder
intel_fifo_underrun.c:344:49: warning: mixing different enum types
intel_fifo_underrun.c:344:49:     int enum pipe  versus
intel_fifo_underrun.c:344:49:     int enum transcoder
intel_fifo_underrun.c:397:57: warning: mixing different enum types
intel_fifo_underrun.c:397:57:     int enum pipe  versus
intel_fifo_underrun.c:397:57:     int enum transcoder
intel_fifo_underrun.c:398:17: warning: mixing different enum types
intel_fifo_underrun.c:398:17:     int enum pipe  versus
intel_fifo_underrun.c:398:17:     int enum transcoder

Cc: Matthias Kaehlcke <mka@chromium.org>
Fixes: a21960339c8c ("drm/i915: Consistently use enum pipe for PCH transcoders")
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170901143123.7590-3-ville.syrjala@linux.intel.com
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
7 years agodrm/i915: Make i2c lock ops static
Ville Syrjälä [Fri, 1 Sep 2017 14:31:22 +0000 (17:31 +0300)]
drm/i915: Make i2c lock ops static

Make gmbus_lock_ops and proxy_lock_ops static to appease sparse
intel_i2c.c:652:34: warning: symbol 'gmbus_lock_ops' was not declared. Should it be static?
intel_sdvo.c:2981:34: warning: symbol 'proxy_lock_ops' was not declared. Should it be static?

Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Fixes: a85066840d29 ("drm/i915: Rework sdvo proxy i2c locking")
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170901143123.7590-2-ville.syrjala@linux.intel.com
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
7 years agodrm/i915: Make i9xx_load_ycbcr_conversion_matrix() static
Ville Syrjälä [Fri, 1 Sep 2017 14:31:21 +0000 (17:31 +0300)]
drm/i915: Make i9xx_load_ycbcr_conversion_matrix() static

Make i9xx_load_ycbcr_conversion_matrix() static to appease sparse:
intel_color.c:110:6: warning: symbol 'i9xx_load_ycbcr_conversion_matrix' was not declared. Should it be static?

Cc: Shashank Sharma <shashank.sharma@intel.com>
Fixes: 25edf91501b8 ("drm/i915: prepare csc unit for YCBCR420 output")
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170901143123.7590-1-ville.syrjala@linux.intel.com
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
7 years agodrm/i915: Eliminate crtc->state usage from intel_atomic_commit_tail and .crtc_update()
Ville Syrjälä [Wed, 23 Aug 2017 15:22:26 +0000 (18:22 +0300)]
drm/i915: Eliminate crtc->state usage from intel_atomic_commit_tail and .crtc_update()

We already have the correct new crtc state so just use that instead of
crtc->state.

Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170823152226.22938-7-ville.syrjala@linux.intel.com
7 years agodrm/i915: Eliminate crtc->state usage from intel_update_pipe_config()
Ville Syrjälä [Wed, 23 Aug 2017 15:22:25 +0000 (18:22 +0300)]
drm/i915: Eliminate crtc->state usage from intel_update_pipe_config()

Pass the correct new crtc state to intel_update_pipe_config() instead
of using crtc->state.

Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170823152226.22938-6-ville.syrjala@linux.intel.com
7 years agodrm/i915: Eliminate obj->state usage from pre/post plane update
Ville Syrjälä [Wed, 23 Aug 2017 15:22:24 +0000 (18:22 +0300)]
drm/i915: Eliminate obj->state usage from pre/post plane update

Dig up the appropriate new crtc and plane states from the top level
atomic state in intel_pre_plane_update() and intel_post_plane_update().

Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170823152226.22938-5-ville.syrjala@linux.intel.com
7 years agodrm/i915: Pass proper old/new states to intel_plane_atomic_check_with_state()
Ville Syrjälä [Wed, 23 Aug 2017 15:22:23 +0000 (18:22 +0300)]
drm/i915: Pass proper old/new states to intel_plane_atomic_check_with_state()

Eliminate plane->state and crtc->state usage from
intel_plane_atomic_check_with_state() and its callers. Instead pass the
proper states in or dig them up from the top level atomic state.

Note that intel_plane_atomic_check_with_state() itself isn't allowed to
use the top level atomic state as there is none when it gets called from
the legacy cursor short circuit path.

v2: Rename some variables for easier comprehension (Maarten)

Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170823152226.22938-4-ville.syrjala@linux.intel.com
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
7 years agodrm/i915: rework IS_*_GT* macros
Lionel Landwerlin [Wed, 30 Aug 2017 16:12:07 +0000 (17:12 +0100)]
drm/i915: rework IS_*_GT* macros

We can now make use of the intel_device_info.gt field.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20170830161208.29221-4-lionel.g.landwerlin@intel.com
7 years agodrm/i915: mark all device info struct with __initconst
Lionel Landwerlin [Wed, 30 Aug 2017 16:12:06 +0000 (17:12 +0100)]
drm/i915: mark all device info struct with __initconst

As recommended by Chris.

v2: Switch from __initdata to __initconst.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20170830161208.29221-3-lionel.g.landwerlin@intel.com
7 years agodrm/i915: add GT number to intel_device_info
Lionel Landwerlin [Wed, 30 Aug 2017 16:12:05 +0000 (17:12 +0100)]
drm/i915: add GT number to intel_device_info

Up to Coffeelake we could deduce this GT number from the device ID.
This doesn't seem to be the case anymore. This change reorders pciids
per GT and adds a gt field to intel_device_info. We set this field on
the following platforms :

   - SNB/IVB/HSW/BDW/SKL/KBL/CFL/CNL

Before & After :

$ modinfo drivers/gpu/drm/i915/i915.ko | grep ^alias | wc -l
209

v2: Add SNB & IVB (Chris)

v3: Fix compilation error in early-quirks (Lionel)

v4: Fix inconsistency between FEATURE/PLATFORM macros (Ville)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20170830161208.29221-2-lionel.g.landwerlin@intel.com
7 years agodrm/i915/edp: Increase T12 panel delay to 900 ms to fix DP AUX CH timeouts
Manasi Navare [Tue, 15 Aug 2017 18:59:51 +0000 (11:59 -0700)]
drm/i915/edp: Increase T12 panel delay to 900 ms to fix DP AUX CH timeouts

This patch fixes the DP AUX CH timeouts observed during CI runs causing
CI Failures on a specific PCI device. This issue was fixed previously
by adding a quirk but looks like we need to increase this delay even more
in order to get rid all the DP AUX CH timeouts.

Fixes: c99a259b4b5192ba ("drm/i915/edp: Add a T12 panel delay quirk to fix
DP AUX CH timeouts")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101144
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Cc: Clinton Taylor <clinton.a.taylor@intel.com>
Cc: Daniel Vetter <daniel.vetter@intel.com>
Cc: Tomi Sarvela <tomi.p.sarvela@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1502823591-25310-1-git-send-email-manasi.d.navare@intel.com
7 years agodrm/i915: Eliminate obj->state usage in g4x/vlv/chv wm computation
Ville Syrjälä [Wed, 23 Aug 2017 15:22:22 +0000 (18:22 +0300)]
drm/i915: Eliminate obj->state usage in g4x/vlv/chv wm computation

Use explicit old/new states instead of relying on obj->state.

Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170823152226.22938-4-ville.syrjala@linux.intel.com
7 years agodrm/i915: Pass the crtc state explicitly to intel_pipe_update_start/end()
Ville Syrjälä [Wed, 23 Aug 2017 15:22:21 +0000 (18:22 +0300)]
drm/i915: Pass the crtc state explicitly to intel_pipe_update_start/end()

Pass the appropriate new crtc state explicitly to
intel_pipe_update_start/end() instead of of mucking around with
crtc->state.

v2: The mmio flip stuff is gone

Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> #v1
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170823152226.22938-2-ville.syrjala@linux.intel.com
7 years agodrm/i915: Pass the new crtc state to color management code
Ville Syrjälä [Wed, 23 Aug 2017 15:22:20 +0000 (18:22 +0300)]
drm/i915: Pass the new crtc state to color management code

In an effort to eliminate the obj->state usage let's pass on the
new crtc state pointer (which we already have!) to the color management
code.

Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170823152226.22938-1-ville.syrjala@linux.intel.com