Jimmy Huang [Fri, 4 Mar 2016 16:53:25 +0000 (00:53 +0800)]
mt8173: Remove gpio driver support
We no longer need to control power signal via gpio during system off,
thus remove gpio driver support from platform code.
Change-Id: I6dfec129fa163330951f37b45b71ba5b90355c3b
Signed-off-by: Jimmy Huang <jimmy.huang@mediatek.com>
Jimmy Huang [Fri, 4 Mar 2016 12:18:58 +0000 (20:18 +0800)]
mt8173: Add #error directive to prevent RESET_TO_BL31
MT8173 platform code is incompatible with RESET_TO_BL31, add #error
directive to prevent the case.
We also move mt8173_def.h and plat_private.h to include directory, and
remove some unnecessary code.
Change-Id: I47b8d0a506820a4ea1fbe8c8fb0ec6c68d88feb5
Signed-off-by: Jimmy Huang <jimmy.huang@mediatek.com>
danh-arm [Mon, 22 Feb 2016 13:23:49 +0000 (13:23 +0000)]
Merge pull request #532 from soby-mathew/vk/configure_mmap_macros
Rationalise MMU and Page table related constants on ARM platforms
Vikram Kanigiri [Wed, 20 Jan 2016 15:57:35 +0000 (15:57 +0000)]
Rationalise MMU and Page table related constants on ARM platforms
`board_arm_def.h` contains multiple definitions of
`PLAT_ARM_MMAP_ENTRIES` and `MAX_XLAT_TABLES` that are optimised for
memory usage depending upon the chosen build configuration. To ease
maintenance of these constants, this patch replaces their multiple
definitions with a single set of definitions that will work on all ARM
platforms.
Platforms can override the defaults with optimal values by enabling the
`ARM_BOARD_OPTIMISE_MMAP` build option. An example has been provided in
the Juno ADP port.
Additionally, `PLAT_ARM_MMAP_ENTRIES` is increased by one to accomodate
future ARM platforms.
Change-Id: I5ba6490fdd1e118cc9cc2d988ad7e9c38492b6f0
danh-arm [Mon, 22 Feb 2016 10:02:29 +0000 (10:02 +0000)]
Merge pull request #518 from hzhuang1/pl061_gpio_v5
Pl061 gpio v5
danh-arm [Fri, 19 Feb 2016 18:22:08 +0000 (18:22 +0000)]
Merge pull request #525 from antonio-nino-diaz-arm/an/fix-gpio-includes
Fix gpio includes of mt8173 platform to avoid collision.
danh-arm [Fri, 19 Feb 2016 18:21:34 +0000 (18:21 +0000)]
Merge pull request #531 from soby-mathew/sm/multicluster_fvp
Allow multi cluster topology definitions for ARM platforms
Soby Mathew [Mon, 1 Feb 2016 14:04:34 +0000 (14:04 +0000)]
Allow multi cluster topology definitions for ARM platforms
The common topology description helper funtions and macros for
ARM Standard platforms assumed a dual cluster system. This is not
flexible enough to scale to multi cluster platforms. This patch does
the following changes for more flexibility in defining topology:
1. The `plat_get_power_domain_tree_desc()` definition is moved from
`arm_topology.c` to platform specific files, that is `fvp_topology.c`
and `juno_topology.c`. Similarly the common definition of the porting
macro `PLATFORM_CORE_COUNT` in `arm_def.h` is moved to platform
specific `platform_def.h` header.
2. The ARM common layer porting macros which were dual cluster specific
are now removed and a new macro PLAT_ARM_CLUSTER_COUNT is introduced
which must be defined by each ARM standard platform.
3. A new mandatory ARM common layer porting API
`plat_arm_get_cluster_core_count()` is introduced to enable the common
implementation of `arm_check_mpidr()` to validate MPIDR.
4. For the FVP platforms, a new build option `FVP_NUM_CLUSTERS` has been
introduced which allows the user to specify the cluster count to be
used to build the topology tree within Trusted Firmare. This enables
Trusted Firmware to be built for multi cluster FVP models.
Change-Id: Ie7a2e38e5661fe2fdb2c8fdf5641d2b2614c2b6b
danh-arm [Thu, 18 Feb 2016 18:36:00 +0000 (18:36 +0000)]
Merge pull request #523 from jcastillo-arm/jc/genfw-791
ARM platforms: rationalise memory attributes of shared memory
danh-arm [Thu, 18 Feb 2016 18:35:37 +0000 (18:35 +0000)]
Merge pull request #530 from antonio-nino-diaz-arm/an/p_printf
Add support for %p in tf_printf()
danh-arm [Thu, 18 Feb 2016 18:34:33 +0000 (18:34 +0000)]
Merge pull request #529 from sandrine-bailleux/sb/a57-sw-optim-ref
Cortex-A57: Add link to software optimization guide
danh-arm [Thu, 18 Feb 2016 18:34:23 +0000 (18:34 +0000)]
Merge pull request #528 from antonio-nino-diaz-arm/an/user_guide
Move up FVP versions in the user guide
danh-arm [Thu, 18 Feb 2016 18:34:11 +0000 (18:34 +0000)]
Merge pull request #527 from antonio-nino-diaz-arm/an/non_ascii
Remove non-ASCII character from comment
danh-arm [Thu, 18 Feb 2016 18:33:59 +0000 (18:33 +0000)]
Merge pull request #526 from antonio-nino-diaz-arm/an/missing_doc
Add missing build options to the User Guide
danh-arm [Thu, 18 Feb 2016 18:33:39 +0000 (18:33 +0000)]
Merge pull request #524 from jcastillo-arm/jc/tf-issues/319
Improve memory layout documentation
Sandrine Bailleux [Tue, 9 Feb 2016 17:01:37 +0000 (17:01 +0000)]
Cortex-A57: Add link to software optimization guide
This patch adds a link to the Cortex-A57 Software Optimization Guide
in the ARM CPU Specific Build Macros document to justify the default
value of the A57_DISABLE_NON_TEMPORAL_HINT build flag.
Change-Id: I9779e42a4bb118442b2b64717ce143314ec9dd16
Antonio Nino Diaz [Tue, 2 Feb 2016 12:03:38 +0000 (12:03 +0000)]
Add support for %p in tf_printf()
This patch adds support for the `%p` format specifier in tf_printf()
following the example of the printf implementation of the stdlib used
in the trusted firmware.
Fixes ARM-software/tf-issues#292
Change-Id: I0b3230c783f735d3e039be25a9405f00023420da
Juan Castillo [Wed, 13 Jan 2016 15:01:09 +0000 (15:01 +0000)]
ARM platforms: rationalise memory attributes of shared memory
The shared memory region on ARM platforms contains the mailboxes and,
on Juno, the payload area for communication with the SCP. This shared
memory may be configured as normal memory or device memory at build
time by setting the platform flag 'PLAT_ARM_SHARED_RAM_CACHED' (on
Juno, the value of this flag is defined by 'MHU_PAYLOAD_CACHED').
When set as normal memory, the platform port performs the corresponding
cache maintenance operations. From a functional point of view, this is
the equivalent of setting the shared memory as device memory, so there
is no need to maintain both options.
This patch removes the option to specify the shared memory as normal
memory on ARM platforms. Shared memory is always treated as device
memory. Cache maintenance operations are no longer needed and have
been replaced by data memory barriers to guarantee that payload and
MHU are accessed in the right order.
Change-Id: I7f958621d6a536dd4f0fa8768385eedc4295e79f
Antonio Nino Diaz [Wed, 17 Feb 2016 11:00:37 +0000 (11:00 +0000)]
Fix gpio includes of mt8173 platform to avoid collision.
All files including plat/mediatek/mt8173/drivers/gpio/gpio.h were
using system includes instead of user includes, which may cause the
wrong version of the header to be included. Said includes have been
changed to user includes to make sure that the included file is the
wanted one.
Change-Id: I29bdfe96fbd9a7900875e2357bbb43f3ea431fa5
Antonio Nino Diaz [Fri, 5 Feb 2016 11:12:24 +0000 (11:12 +0000)]
Add missing build options to the User Guide
The folowing build options were missing from the User Guide and have been
documented:
- CTX_INCLUDE_FPREGS
- DISABLE_PEDANTIC
- BUILD_STRING
- VERSION_STRING
- BUILD_MESSAGE_TIMESTAMP
Change-Id: I6a9c39ff52cad8ff04deff3ac197af84d437b8b7
danh-arm [Wed, 17 Feb 2016 10:01:03 +0000 (10:01 +0000)]
Merge pull request #522 from danh-arm/vk/rework-interconnect-drivers
Rework use of interconnect drivers
Vikram Kanigiri [Mon, 15 Feb 2016 11:54:14 +0000 (11:54 +0000)]
Rework use of interconnect drivers
ARM Trusted Firmware supports 2 different interconnect peripheral
drivers: CCI and CCN. ARM platforms are implemented using either of the
interconnect peripherals.
This patch adds a layer of abstraction to help ARM platform ports to
choose the right interconnect driver and corresponding platform support.
This is as described below:
1. A set of ARM common functions have been implemented to initialise an
interconnect and for entering/exiting a cluster from coherency. These
functions are prefixed as "plat_arm_interconnect_". Weak definitions of
these functions have been provided for each type of driver.
2.`plat_print_interconnect_regs` macro used for printing CCI registers is
moved from a common arm_macros.S to cci_macros.S.
3. The `ARM_CONFIG_HAS_CCI` flag used in `arm_config_flags` structure
is renamed to `ARM_CONFIG_HAS_INTERCONNECT`.
Change-Id: I02f31184fbf79b784175892d5ce1161b65a0066c
danh-arm [Tue, 16 Feb 2016 12:47:05 +0000 (12:47 +0000)]
Merge pull request #521 from vikramkanigiri/vk/rearchitect_security
Perform security setup separately for each ARM platform
danh-arm [Tue, 16 Feb 2016 12:46:28 +0000 (12:46 +0000)]
Merge pull request #520 from vikramkanigiri/vk/scp_flexibility
Vk/scp flexibility
danh-arm [Tue, 16 Feb 2016 12:45:59 +0000 (12:45 +0000)]
Merge pull request #519 from vikramkanigiri/vk/misc_plat_reorg
Vk/misc plat reorg
Vikram Kanigiri [Thu, 14 Jan 2016 14:26:27 +0000 (14:26 +0000)]
Make SCP_BL2(U) image loading configurable on CSS platforms
Current code mandates loading of SCP_BL2/SCP_BL2U images for all
CSS platforms. On future ARM CSS platforms, the Application
Processor (AP) might not need to load these images. So, these
items can be removed from the FIP on those platforms.
BL2 tries to load SCP_BL2/SCP_BL2U images if their base
addresses are defined causing boot error if the images are not
found in FIP.
This change adds a make flag `CSS_LOAD_SCP_IMAGES` which if set
to `1` does:
1. Adds SCP_BL2, SCP_BL2U images to FIP.
2. Defines the base addresses of these images so that AP loads
them.
And vice-versa if it is set to `0`. The default value is set to
`1`.
Change-Id: I5abfe22d5dc1e9d80d7809acefc87b42a462204a
Vikram Kanigiri [Wed, 10 Feb 2016 14:50:53 +0000 (14:50 +0000)]
Perform security setup separately for each ARM platform
Prior to this patch, it was assumed that on all ARM platforms the bare
minimal security setup required is to program TrustZone protection. This
would always be done by programming the TZC-400 which was assumed to be
present in all ARM platforms. The weak definition of
platform_arm_security_setup() in plat/arm/common/arm_security.c
reflected these assumptions.
In reality, each ARM platform either decides at runtime whether
TrustZone protection needs to be programmed (e.g. FVPs) or performs
some security setup in addition to programming TrustZone protection
(e.g. NIC setup on Juno). As a result, the weak definition of
plat_arm_security_setup() is always overridden.
When a platform needs to program TrustZone protection and implements the
TZC-400 peripheral, it uses the arm_tzc_setup() function to do so. It is
also possible to program TrustZone protection through other peripherals
that include a TrustZone controller e.g. DMC-500. The programmer's
interface is slightly different across these various peripherals.
In order to satisfy the above requirements, this patch makes the
following changes to the way security setup is done on ARM platforms.
1. arm_security.c retains the definition of arm_tzc_setup() and has been
renamed to arm_tzc400.c. This is to reflect the reliance on the
TZC-400 peripheral to perform TrustZone programming. The new file is
not automatically included in all platform ports through
arm_common.mk. Each platform must include it explicitly in a platform
specific makefile if needed.
This approach enables introduction of similar library code to program
TrustZone protection using a different peripheral. This code would be
used by the subset of ARM platforms that implement this peripheral.
2. Due to #1 above, existing platforms which implements the TZC-400 have been
updated to include the necessary files for both BL2, BL2U and BL31
images.
Change-Id: I513c58f7a19fff2e9e9c3b95721592095bcb2735
Vikram Kanigiri [Mon, 8 Feb 2016 16:29:30 +0000 (16:29 +0000)]
Support for varying BOM/SCPI protocol base addresses in ARM platforms
Current code assumes `SCP_COM_SHARED_MEM_BASE` as the base address
for BOM/SCPI protocol between AP<->SCP on all CSS platforms. To
cater for future ARM platforms this is made platform specific.
Similarly, the bit shifts of `SCP_BOOT_CONFIG_ADDR` are also made
platform specific.
Change-Id: Ie8866c167abf0229a37b3c72576917f085c142e8
Vikram Kanigiri [Thu, 12 Nov 2015 18:52:34 +0000 (18:52 +0000)]
Add API to return memory map on ARM platforms
Functions to configure the MMU in S-EL1 and EL3 on ARM platforms
expect each platform to export its memory map in the `plat_arm_mmap`
data structure. This approach does not scale well in case the memory
map cannot be determined until runtime. To cater for this possibility,
this patch introduces the plat_arm_get_mmap() API. It returns a
reference to the `plat_arm_mmap` by default but can be overridden
by a platform if required.
Change-Id: Idae6ad8fdf40cdddcd8b992abc188455fa047c74
Haojian Zhuang [Wed, 3 Feb 2016 14:35:04 +0000 (22:35 +0800)]
Document: add PLAT_PL061_MAX_GPIOS define
ARM PL061 GPIO driver requires the "PLAT_PL061_MAX_GPIOS" definition.
By default, it's defined to 32 in PL061 GPIO driver. If user wants
more PL061 controllers in platform, user should define the build
flag in platform.mk instead.
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Haojian Zhuang [Wed, 27 Jan 2016 05:22:43 +0000 (13:22 +0800)]
arm: gpio: add pl061 driver
Add PL061 GPIO driver that is depend on gpio framework.
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Haojian Zhuang [Wed, 27 Jan 2016 05:18:21 +0000 (13:18 +0800)]
gpio: add gpio framework
Define the gpio ops in gpio driver.
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Vikram Kanigiri [Thu, 12 Nov 2015 17:22:16 +0000 (17:22 +0000)]
Add support for SSC_VERSION register on CSS platforms
Each ARM Compute Subsystem based platform implements a System Security
Control (SSC) Registers Unit. The SSC_VERSION register inside it carries
information to identify the platform. This enables ARM Trusted Firmware
to compile in support for multiple ARM platforms and choose one at
runtime. This patch adds macros to enable access to this register.
Each platform is expected to export its PART_NUMBER separately.
Additionally, it also adds juno part number.
Change-Id: I2b1d5f5b65a9c7b76c6f64480cc7cf0aef019422
Vikram Kanigiri [Thu, 21 Jan 2016 14:08:15 +0000 (14:08 +0000)]
Re-factor definition of some macros on ARM platforms
This patch moves the definition of some macros used only on
ARM platforms from common headers to platform specific headers.
It also forces all ARM standard platforms to have distinct
definitions (even if they are usually the same).
1. `PLAT_ARM_TZC_BASE` and `PLAT_ARM_NSTIMER_FRAME_ID` have been
moved from `css_def.h` to `platform_def.h`.
2. `MHU_BASE` used in CSS platforms is moved from common css_def.h
to platform specific header `platform_def.h` on Juno and
renamed as `PLAT_ARM_MHU_BASE`.
3. To cater for different sizes of BL images, new macros like
`PLAT_ARM_MAX_BL31_SIZE` have been created for each BL image. All
ARM platforms need to define them for each image.
Change-Id: I9255448bddfad734b387922aa9e68d2117338c3f
danh-arm [Thu, 11 Feb 2016 13:26:17 +0000 (13:26 +0000)]
Merge pull request #517 from soby-mathew/sm/gic_set_prio_fix
Fix IPRIORITY and ITARGET accessors in GIC drivers
danh-arm [Thu, 11 Feb 2016 13:25:31 +0000 (13:25 +0000)]
Merge pull request #513 from pgeorgi/configurable-timestamp
build system: allow overriding the build's timestamp
Soby Mathew [Mon, 1 Feb 2016 17:59:22 +0000 (17:59 +0000)]
Move private APIs in gic_common.h to a private header
This patch moves the private GIC common accessors from `gic_common.h` to
a new private header file `gic_common_private.h`. This patch also adds
additional comments to GIC register accessors to highlight the fact
that some of them access register values that correspond to multiple
interrupt IDs. The convention used is that the `set`, `get` and `clr`
accessors access and modify the values corresponding to a single interrupt
ID whereas the `read` and `write` GIC register accessors access the raw
GIC registers and it could correspond to multiple interrupt IDs depending
on the register accessed.
Change-Id: I2643ecb2533f01e3d3219fcedfb5f80c120622f9
Soby Mathew [Fri, 15 Jan 2016 14:20:57 +0000 (14:20 +0000)]
Fix GIC_IPRIORITYR setting in new drivers
The code to set the interrupt priority for secure interrupts in the
new GICv2 and GICv3 drivers is incorrect. The setup code to configure
interrupt priorities of secure interrupts, one interrupt at a time, used
gicd_write_ipriorityr()/gicr_write_ipriority() function affecting
4 interrupts at a time. This bug did not manifest itself because all the
secure interrupts were configured to the highest secure priority(0) during
cold boot and the adjacent non secure interrupt priority would be configured
later by the normal world. This patch introduces new accessors,
gicd_set_ipriorityr() and gicr_set_ipriorityr(), for configuring priority
one interrupt at a time and fixes the the setup code to use the new
accessors.
Fixes ARM-software/tf-issues#344
Change-Id: I470fd74d2b7fce7058b55d83f604be05a27e1341
Soby Mathew [Fri, 15 Jan 2016 14:05:37 +0000 (14:05 +0000)]
Fix race in GIC IPRIORITY and ITARGET accessors
GICD_IPRIORITYR and GICD_ITARGETSR specifically support byte addressing
so that individual interrupt priorities can be atomically updated by
issuing a single byte write. The previous implementation of
gicd_set_ipriority() and gicd_set_itargetsr() used 32-bit register
accesses, modifying values for 4 interrupts at a time, using a
read-modify-write approach. This potentially may cause concurrent changes
by other CPUs to the adjacent interrupts to be corrupted. This patch fixes
the issue by modifying these accessors to use byte addressing.
Fixes ARM-software/tf-issues#343
Change-Id: Iec28b5f5074045b00dfb8d5f5339b685f9425915
danh-arm [Tue, 9 Feb 2016 10:58:13 +0000 (10:58 +0000)]
Merge pull request #516 from vikramkanigiri/vk/ccn-fix-dvm-entry
Bug fix: Rectify logic to enter or exit from DVM domain
danh-arm [Tue, 9 Feb 2016 10:56:53 +0000 (10:56 +0000)]
Merge pull request #515 from soby-mathew/sm/gcc_false_positive
PSCI: Resolve GCC static analysis false positive
danh-arm [Tue, 9 Feb 2016 10:56:09 +0000 (10:56 +0000)]
Merge pull request #514 from sandrine-bailleux/sb/a53-a57-disable-non-temporal-hint
Disable non-temporal hint on Cortex-A53/57
Vikram Kanigiri [Mon, 4 Jan 2016 16:23:22 +0000 (16:23 +0000)]
Bug fix: Rectify logic to enter or exit from DVM domain
Currently, `ccn_snoop_dvm_domain_common()` is responsible for providing
a bitmap of HN-F and HN-I nodes in the interconnect. There is a request
node (RN) corresponding to the master interface (e.g. cluster) that needs
to be added or removed from the snoop/DVM domain. This request node is
removed from or added to each HN-F or HN-I node present in the bitmap
depending upon the type of domain.
The above logic is incorrect when participation of a master interface in
the DVM domain has to be managed. The request node should be removed
from or added to the single Miscellaneous Node (MN) in the system
instead of each HN-I node.
This patch fixes this by removing the intermediate
`ccn_snoop_dvm_domain_common()` and instead reads the MN registers to
get the needed node Id bitmap for snoop(HN-F bitmap) and DVM(MN bitmap)
domains.
Additionally, it renames `MN_DDC_SET_OFF` to `MN_DDC_SET_OFFSET` to
be inline with other macros.
Change-Id: Id896046dd0ccc5092419e74f8ac85e31b104f7a4
Soby Mathew [Tue, 2 Feb 2016 14:23:10 +0000 (14:23 +0000)]
PSCI: Resolve GCC static analysis false positive
When BL31 is compiled at `-O3` optimization level using Linaro GCC 4.9
AArch64 toolchain, it reports the following error:
```
services/std_svc/psci/psci_common.c: In function 'psci_do_state_coordination':
services/std_svc/psci/psci_common.c:220:27: error: array subscript is above
array bounds [-Werror=array-bounds]
psci_req_local_pwr_states[pwrlvl - 1][cpu_idx] = req_pwr_state;
^
```
This error is a false positive and this patch resolves the error by asserting
the array bounds in `psci_do_state_coordination()`.
Fixes ARM-software/tf-issues#347
Change-Id: I3584ed7b2e28faf455b082cb3281d6e1d11d6495
Sandrine Bailleux [Fri, 29 Jan 2016 14:37:58 +0000 (14:37 +0000)]
Cortex-Axx: Unconditionally apply CPU reset operations
In the Cortex-A35/A53/A57 CPUs library code, some of the CPU specific
reset operations are skipped if they have already been applied in a
previous invocation of the reset handler. This precaution is not
required, as all these operations can be reapplied safely.
This patch removes the unneeded test-before-set instructions in
the reset handler for these CPUs.
Change-Id: Ib175952c814dc51f1b5125f76ed6c06a22b95167
Sandrine Bailleux [Wed, 13 Jan 2016 14:57:38 +0000 (14:57 +0000)]
Disable non-temporal hint on Cortex-A53/57
The LDNP/STNP instructions as implemented on Cortex-A53 and
Cortex-A57 do not behave in a way most programmers expect, and will
most probably result in a significant speed degradation to any code
that employs them. The ARMv8-A architecture (see Document ARM DDI
0487A.h, section D3.4.3) allows cores to ignore the non-temporal hint
and treat LDNP/STNP as LDP/STP instead.
This patch introduces 2 new build flags:
A53_DISABLE_NON_TEMPORAL_HINT and A57_DISABLE_NON_TEMPORAL_HINT
to enforce this behaviour on Cortex-A53 and Cortex-A57. They are
enabled by default.
The string printed in debug builds when a specific CPU errata
workaround is compiled in but skipped at runtime has been
generalised, so that it can be reused for the non-temporal hint use
case as well.
Change-Id: I3e354f4797fd5d3959872a678e160322b13867a1
Patrick Georgi [Thu, 28 Jan 2016 13:46:18 +0000 (14:46 +0100)]
build system: allow overriding the build's timestamp
This allows reproducible builds (same source and same compiler produce
bit-identical results) and also allows coordinating the timestamp across
multiple projects, eg. with another firmware.
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Antonio Nino Diaz [Thu, 28 Jan 2016 14:25:56 +0000 (14:25 +0000)]
Move up FVP versions in the user guide
Move up to Base FVP version 7.2 (build 0.8/7202) and Foundation FVP version
9.5 (build 9.5.41) in the user guide.
Change-Id: Ie9900596216808cadf45f042eec639d906e497b2
Antonio Nino Diaz [Wed, 3 Feb 2016 14:41:48 +0000 (14:41 +0000)]
Remove non-ASCII character from comment
Replaced a long dash in a comment by the ASCII character '-'. Support
for multibyte character in the source character set is not enforced by
the C99 standard. To maximize compatibility with C processing tools
(e.g. compilers or static code analysis tools), they should be removed.
Change-Id: Ie318e380d3b44755109f042a76ebfd2229f42ae3
danh-arm [Mon, 1 Feb 2016 19:10:02 +0000 (19:10 +0000)]
Merge pull request #511 from soby-mathew/sm/psci_on_race_v2
Fix PSCI CPU ON race when setting state to ON_PENDING
danh-arm [Mon, 1 Feb 2016 19:06:57 +0000 (19:06 +0000)]
Merge pull request #508 from soby-mathew/sm/debug_xlat
Use tf_printf() for debug logs from xlat_tables.c
danh-arm [Mon, 1 Feb 2016 19:06:03 +0000 (19:06 +0000)]
Merge pull request #504 from sandrine-bailleux/sb/fix-doc-mmap
Porting Guide: Clarify identity-mapping requirement
danh-arm [Mon, 1 Feb 2016 19:05:07 +0000 (19:05 +0000)]
Merge pull request #503 from sandrine-bailleux/sb/clarify-doc-el3-payloads
Clarify EL3 payload documentation
danh-arm [Mon, 1 Feb 2016 19:03:41 +0000 (19:03 +0000)]
Merge pull request #501 from jcastillo-arm/jc/tf-issues/300
Disable PL011 UART before configuring it
Soby Mathew [Tue, 26 Jan 2016 11:47:53 +0000 (11:47 +0000)]
Fix PSCI CPU ON race when setting state to ON_PENDING
When a CPU is powered down using PSCI CPU OFF API, it disables its caches
and updates its `aff_info_state` to OFF. The corresponding cache line is
invalidated by the CPU so that the update will be observed by other CPUs
running with caches enabled. There is a possibility that another CPU
which has been trying to turn ON this CPU via PSCI CPU ON API,
has already seen the update to `aff_info_state` and proceeds to update
the state to ON_PENDING prior to the cache invalidation. This may result
in the update of the state to ON_PENDING being discarded.
This patch fixes this issue by making sure that the update of `aff_info_state`
to ON_PENDING sticks by reading back the value after the cache flush and
retrying it if not updated. The patch also adds a dsbish() to
`psci_do_cpu_off()` to ensure ordering of the update to `aff_info_state`
prior to cache line invalidation.
Fixes ARM-software/tf-issues#349
Change-Id: I225de99957fe89871f8c57bcfc243956e805dcca
danh-arm [Mon, 1 Feb 2016 13:02:25 +0000 (13:02 +0000)]
Merge pull request #497 from mtk09422/spm-v3
update SPM/DCM/MTCMOS related code for power control logic
Juan Castillo [Fri, 4 Dec 2015 12:19:27 +0000 (12:19 +0000)]
Improve memory layout documentation
This patch adds a brief explanation of the top/bottom load approach
to the Firmware Design guide and how Trusted Firmware keeps track of
the free memory at boot time. This will help platform developers to
avoid unexpected results in the memory layout.
Fixes ARM-software/tf-issues#319
Change-Id: I04be7e24c1f3b54d28cac29701c24bf51a5c00ad
Soby Mathew [Tue, 19 Jan 2016 17:52:28 +0000 (17:52 +0000)]
Use tf_printf() for debug logs from xlat_tables.c
The debug prints used to debug translation table setup in xlat_tables.c
used the `printf()` standard library function instead of the stack
optimized `tf_printf()` API. DEBUG_XLAT_TABLE option was used to enable
debug logs within xlat_tables.c and it configured a much larger stack
size for the platform in case it was enabled. This patch modifies these
debug prints within xlat_tables.c to use tf_printf() and modifies the format
specifiers to be compatible with tf_printf(). The debug prints are now enabled
if the VERBOSE prints are enabled in Trusted Firmware via LOG_LEVEL build
option.
The much larger stack size definition when DEBUG_XLAT_TABLE is defined
is no longer required and the platform ports are modified to remove this
stack size definition.
Change-Id: I2f7d77ea12a04b827fa15e2adc3125b1175e4c23
Sandrine Bailleux [Wed, 2 Dec 2015 10:19:06 +0000 (10:19 +0000)]
Porting Guide: Clarify identity-mapping requirement
The memory translation library in Trusted Firmware supports
non-identity mappings for Physical to Virtual addresses since commit
f984ce84ba. However, the porting guide hasn't been updated
accordingly and still mandates the platform ports to use
identity-mapped page tables for all addresses.
This patch removes this out-dated information from the Porting Guide
and clarifies in which circumstances non-identity mapping may safely
be used.
Fixes ARM-software/tf-issues#258
Change-Id: I84dab9f3cabfc43794951b1828bfecb13049f706
Sandrine Bailleux [Wed, 20 Jan 2016 10:33:54 +0000 (10:33 +0000)]
Clarify EL3 payload documentation
This patch reworks the section about booting an EL3 payload in the
User Guide:
- Centralize all EL3 payload related information in the same
section.
- Mention the possibility to program the EL3 payload in flash memory
and execute it in place.
- Provide model parameters for both the Base and Foundation FVPs.
- Provide some guidance to boot an EL3 payload on Juno.
Change-Id: I975c8de6b9b54ff4de01a1154cba63271d709912
Fan Chen [Tue, 8 Dec 2015 02:46:47 +0000 (10:46 +0800)]
mt8173: Fix long latency issue of mtcmos contorl
We found sometimes mtcmos operation is too long in spm (>1ms),
so update a new version to fix it.
I verified with 5 hours power_LoadTest, every mtcmos control
can finish in 500us (average is 100~200us).
Change-Id: I47b712bf9898870f4abcecbea47e01b9786231d4
Signed-off-by: Fan Chen <fan.chen@mediatek.com>
Weiyi Lu [Fri, 20 Nov 2015 08:25:16 +0000 (16:25 +0800)]
mt8173: Improve performance by handling more interrupts during idle
1. Set more wakeup source
2. Update PCM code for control logic
Change-Id: I2ad06bd85bd1c75a22c838eab4cf5566c443b89a
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Jimmy Huang [Mon, 16 Nov 2015 06:38:40 +0000 (14:38 +0800)]
mt8173: Implement subsystem power control logic in ARM TF
1. Add SiP calls for subsystem power on/off and check support
2. Add subsystem power control related initialization in
bl31_plat_setup.c
3. Add subsystem power on/off and power ack waiting functions
4. Update PCM code for subsystem physical power control logic
Change-Id: Ia0ebb1964c8f9758159bcf17c1813d76ef52cf64
Signed-off-by: yt.lee <yt.lee@mediatek.com>
Jimmy Huang [Mon, 16 Nov 2015 06:33:35 +0000 (14:33 +0800)]
mt8173: support big/Little cluster power off for CPU idle(C2 state)
1. add power control for both big and Little cluster in MCDI
2. fix incorrect PCM_HOTPLUG_VALID_MASK in spm_hotplug.c
3. check the power status of cpus in cluster before setting the cputop
power control
Change-Id: Ifa85306a8bc218098667247904d281494c2f7bfe
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Jimmy Huang [Mon, 16 Nov 2015 06:26:14 +0000 (14:26 +0800)]
mt8173: Move SPM related PLL settings to ARM TF
Move SPM related PLL settings to spm_boot_init in ARM TF SPM driver
Change-Id: I414b896caae072570c8de33a25e06db4ae011f57
Signed-off-by: yt.lee <yt.lee@mediatek.com>
Jimmy Huang [Mon, 16 Nov 2015 06:22:32 +0000 (14:22 +0800)]
mt8173: Fix USB remote wake up problem
This patch updates SPM driver settings and PCM code to fix USB remote
wake up problem.
Change-Id: I07a81cc64b1d226d111380580d09ae25879f4285
Signed-off-by: yt.lee <yt.lee@mediatek.com>
Jimmy Huang [Mon, 16 Nov 2015 06:18:36 +0000 (14:18 +0800)]
mt8173: Enable dynamic clock management
This patch enables dynamic clock management control to reduce power
consumption in various components.
Change-Id: I8f66d9b72c8b1d70169ffe46cc361b16a0dadb77
Signed-off-by: Jimmy Huang <jimmy.huang@mediatek.com>
danh-arm [Mon, 25 Jan 2016 11:02:42 +0000 (11:02 +0000)]
Merge pull request #496 from Xilinx/attr-deprecated
cdefs.h: Use __deprecated__ instead of deprecated
danh-arm [Mon, 25 Jan 2016 11:02:13 +0000 (11:02 +0000)]
Merge pull request #495 from jcastillo-arm/jc/tf-issues/170
ARM plat: add build option to unlock access to non-secure timer
Juan Castillo [Thu, 26 Nov 2015 14:52:15 +0000 (14:52 +0000)]
Disable PL011 UART before configuring it
The PL011 TRM (ARM DDI 0183G) specifies that the UART must be
disabled before any of the control registers are programmed. The
PL011 driver included in TF does not disable the UART, so the
initialization in BL2 and BL31 is violating this requirement
(and potentially in BL1 if the UART is enabled after reset).
This patch modifies the initialization function in the PL011
console driver to disable the UART before programming the
control registers.
Register clobber list and documentation updated.
Fixes ARM-software/tf-issues#300
Change-Id: I839b2d681d48b03f821ac53663a6a78e8b30a1a1
Soren Brinkmann [Wed, 20 Jan 2016 23:32:23 +0000 (15:32 -0800)]
cdefs.h: Use __deprecated__ instead of deprecated
Use the form with underscores to define the '__deprecated' macro to avoid
collisions with potentially defined macros, as suggested in gcc docs
(https://gcc.gnu.org/onlinedocs/gcc/Attribute-Syntax.html#Attribute-Syntax).
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Juan Castillo [Fri, 6 Nov 2015 16:02:32 +0000 (16:02 +0000)]
ARM plat: add build option to unlock access to non-secure timer
Currently, Trusted Firmware on ARM platforms unlocks access to the
timer frame registers that will be used by the Non-Secure world. This
unlock operation should be done by the Non-Secure software itself,
instead of relying on secure firmware settings.
This patch adds a new ARM specific build option 'ARM_CONFIG_CNTACR'
to unlock access to the timer frame by setting the corresponding
bits in the CNTACR<N> register. The frame id <N> is defined by
'PLAT_ARM_NSTIMER_FRAME_ID'. Default value is true (unlock timer
access).
Documentation updated accordingly.
Fixes ARM-software/tf-issues#170
Change-Id: Id9d606efd781e43bc581868cd2e5f9c8905bdbf6
danh-arm [Mon, 18 Jan 2016 10:30:55 +0000 (10:30 +0000)]
Merge pull request #493 from yupluo01/yp/tf-issue-fix-doc-links
Update doc links in the porting guide
Yuping Luo [Fri, 15 Jan 2016 03:17:27 +0000 (11:17 +0800)]
Update doc links in the porting guide
GIC v2 and v3 specification references in the porting guide
should refer to publically visible links, not ARM internal links.
Change-Id: Ib47c8adda6a03581f23bcaed72d71c08c7dd9fb1
Signed-off-by: Yuping Luo <yuping.luo@arm.com>
danh-arm [Fri, 15 Jan 2016 17:55:46 +0000 (17:55 +0000)]
Merge pull request #489 from sandrine-bailleux/sb/fix-mailbox-doc
Doc: Update out-dated info about Juno's mailbox
danh-arm [Fri, 15 Jan 2016 17:55:11 +0000 (17:55 +0000)]
Merge pull request #486 from Xilinx/issues/340
Clean up __attribute__ usage
Sandrine Bailleux [Fri, 15 Jan 2016 11:14:57 +0000 (11:14 +0000)]
Doc: Update out-dated info about Juno's mailbox
Since commit
804040d106, the Juno port has moved from per-CPU mailboxes
to a single shared one. This patch updates an out-dated reference to
the former per-CPU mailboxes mechanism in the Firmware Design.
Change-Id: I355b54156b1ace1b3df4c4416e1e8625211677fc
Soren Brinkmann [Thu, 14 Jan 2016 18:11:05 +0000 (10:11 -0800)]
Remove direct usage of __attribute__((foo))
Migrate all direct usage of __attribute__ to usage of their
corresponding macros from cdefs.h.
e.g.:
- __attribute__((unused)) -> __unused
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Soren Brinkmann [Thu, 14 Jan 2016 18:02:33 +0000 (10:02 -0800)]
Migrate __warn_deprecated -> __deprecated
Use the new __deprecated macro from the generic cdefs header and remove
the deprecated __warn_deprecated.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Soren Brinkmann [Thu, 14 Jan 2016 17:56:06 +0000 (09:56 -0800)]
cdefs.h: Introduce '__deprecated' macro
Introduce a macro to mark functions as deprecated.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
danh-arm [Thu, 14 Jan 2016 12:24:17 +0000 (12:24 +0000)]
Merge pull request #487 from sandrine-bailleux/sb/cortex-a72
FVP: Compile ARM Cortex-A72 CPU support in
danh-arm [Wed, 13 Jan 2016 12:40:31 +0000 (12:40 +0000)]
Merge pull request #485 from jcastillo-arm/jc/max_mmap_reg
Add 'MAX_MMAP_REGIONS' and 'ADDR_SPACE_SIZE' to the Porting Guide
danh-arm [Wed, 13 Jan 2016 11:42:30 +0000 (11:42 +0000)]
Merge pull request #484 from jcastillo-arm/jc/tf-issues/337
cert_create: update help message
danh-arm [Wed, 13 Jan 2016 11:41:46 +0000 (11:41 +0000)]
Merge pull request #483 from soby-mathew/sm/rm_struct_padding
Rearrange fields in TF data structures to reduce padding
danh-arm [Wed, 13 Jan 2016 11:36:43 +0000 (11:36 +0000)]
Merge pull request #482 from sandrine-bailleux/sb/cortex-a35
Add support for ARM Cortex-A35 processor
danh-arm [Wed, 13 Jan 2016 11:15:07 +0000 (11:15 +0000)]
Merge pull request #481 from sandrine-bailleux/sb/fix-doc
Various documentation fixes
Juan Castillo [Thu, 7 Jan 2016 11:29:15 +0000 (11:29 +0000)]
Add 'MAX_MMAP_REGIONS' and 'ADDR_SPACE_SIZE' to the Porting Guide
This patch adds a brief description of 'MAX_MMAP_REGIONS' and
'ADDR_SPACE_SIZE' to the Porting Guide. These fields must be defined
by the platform in order to use the translation table library.
Change-Id: Ida366458fe2bc01979091a014dc38da0fae5991e
Soby Mathew [Tue, 12 Jan 2016 10:30:59 +0000 (10:30 +0000)]
Rearrange fields in TF data structures to reduce padding
This patch rearranges fields of the `image_desc_t` & `auth_img_desc_t`
data structures to reduce padding between the fields and thereby
save memory.
NOTE: Platform ports which anonymously initialize these structures
should be aware of the rearrangement and do the required
modification.
Change-Id: I428b5429632797b31d5bd306174599c07e24c060
Soby Mathew [Tue, 12 Jan 2016 10:28:42 +0000 (10:28 +0000)]
Use designated initialization in DECLARE_RT_SVC macro
This patch changes the anonymous initialization of `rt_svc_desc_t` structure
by the `DECLARE_RT_SVC` macro to designated initialization. This makes the
code more robust and less sensitive to potential changes to the
`rt_svc_desc_t` structure.
Change-Id: If6f1586730c0d29d92ef09e07eff7dd0d22857c7
Sandrine Bailleux [Wed, 13 Jan 2016 09:04:26 +0000 (09:04 +0000)]
FVP: Compile ARM Cortex-A72 CPU support in
This patch enables the ARM Cortex-A72 support in BL1 and BL31 on FVP.
This allows the same TF binaries to run on a Cortex-A72 based FVP
without recompiling them.
Change-Id: I4eb6bbad9f0e5d8704613f7c685c3bd22b45cf47
Sandrine Bailleux [Fri, 8 Jan 2016 14:12:55 +0000 (14:12 +0000)]
Documentation: Fix broken links in ToCs
Change-Id: I4fcdb8e813e0392c2cd3d0623698e8319b3b0593
Sandrine Bailleux [Thu, 7 Jan 2016 16:52:49 +0000 (16:52 +0000)]
Add support for ARM Cortex-A35 processor
This patch adds support for ARM Cortex-A35 processor in the CPU
specific framework, as described in the Cortex-A35 TRM (r0p0).
Change-Id: Ief930a0bdf6cd82f6cb1c3b106f591a71c883464
Sandrine Bailleux [Fri, 8 Jan 2016 10:05:59 +0000 (10:05 +0000)]
Fixes in CPU specific operations framework doc
This patch fixes a couple of issues in the "CPU specific operations
framework" section in the Firmware Design document.
* Fix broken link to the CPU Specific Build Macros document.
* Fix the path to the cortex_a53.S file.
* Fix power levels terminology.
Change-Id: Ib610791eaba13dab2823b7699bb63534bcd1c8fb
Juan Castillo [Tue, 15 Dec 2015 16:37:57 +0000 (16:37 +0000)]
cert_create: update help message
The help message printed by the cert_create tool using the command
line option -h (or --help) does not correctly list all the available
command line options.
This patch reworks the print_help() function to print the help
messages in a data driven approach. For each command line option
registered, an optional help message can be specified, which will
be printed by print_help().
Help messages for the TBBR options (certificates, keys and images)
are also provided.
Fix a small bug in the short options string passed to getopt_long:
the ':' was missing in the '-a' option (this option must take an
argument).
Fixes ARM-software/tf-issues#337
Change-Id: I9d08c2dfd349022808fcc884724f677eefdc1452
danh-arm [Wed, 6 Jan 2016 14:51:07 +0000 (14:51 +0000)]
Merge pull request #479 from jcastillo-arm/jc/tbbr_fip
Apply TBBR naming convention to the fip_create options
danh-arm [Wed, 6 Jan 2016 14:50:15 +0000 (14:50 +0000)]
Merge pull request #478 from sandrine-bailleux/sb/mbed-tls-pedantic
Always build with '-pedantic'
danh-arm [Wed, 6 Jan 2016 14:49:06 +0000 (14:49 +0000)]
Merge pull request #477 from mtk09422/console_uninit
Add ret to return from console_uninit() function
Juan Castillo [Tue, 5 Jan 2016 11:55:36 +0000 (11:55 +0000)]
Apply TBBR naming convention to the fip_create options
The fip_create tool specifies images in the command line using the
ARM TF naming convention (--bl2, --bl31, etc), while the cert_create
tool uses the TBBR convention (--tb-fw, --soc-fw, etc). This double
convention is confusing and should be aligned.
This patch updates the fip_create command line options to follow the
TBBR naming convention. Usage examples in the User Guide have been
also updated.
NOTE: users that build the FIP by calling the fip_create tool directly
from the command line must update the command line options in their
scripts. Users that build the FIP by invoking the main ARM TF Makefile
should not notice any difference.
Change-Id: I84d602630a2585e558d927b50dfde4dd2112496f
Sandrine Bailleux [Mon, 4 Jan 2016 15:49:23 +0000 (15:49 +0000)]
Always build with '-pedantic'
By default ARM TF is built with the '-pedantic' compiler flag, which
helps detecting violations of the C standard. However, the mbed TLS
library and its associated authentication module in TF used to fail
building with this compiler flag. As a workaround, the mbed TLS
authentication module makefile used to set the 'DISABLE_PEDANTIC'
TF build flag.
The compiler errors flagged by '-pedantic' in the mbed TLS library
have been fixed between versions 1.3.9 and 2.2.0 and the library now
properly builds with this compiler flag.
This patch fixes the remaining compiler errors in the mbed TLS
authentication module in TF and unsets the 'DISABLE_PEDANTIC' TF
build flag. This means that TF is now always built with '-pedantic'.
In particular, this patch:
* Removes the final semi-colon in REGISTER_COT() macro.
This semi-colon was causing the following error message:
drivers/auth/tbbr/tbbr_cot.c:544:23: error: ISO C does not allow
extra ';' outside of a function [-Werror=pedantic]
This has been fixed both in the mbed TLS authentication module
as well as in the certificate generation tool. Note that the latter
code didn't need fixing since it is not built with '-pedantic' but
the change has been propagated for consistency.
Also fixed the REGISTER_KEYS() and REGISTER_EXTENSIONS() macros,
which were suffering from the same issue.
* Fixes a pointer type.
It was causing the following error message:
drivers/auth/mbedtls/mbedtls_crypto.c: In function 'verify_hash':
drivers/auth/mbedtls/mbedtls_crypto.c:177:42: error: pointer of
type 'void *' used in arithmetic [-Werror=pointer-arith]
Change-Id: I7b7a04ef711efd65e17b5be26990d1a0d940257d
Jimmy Huang [Thu, 31 Dec 2015 08:52:35 +0000 (16:52 +0800)]
Add ret to return from console_uninit() function
The 'ret' was missing in console_uninit() implementation, so the
program doesn't return from console_uninit(). Instead, it keeps
executing the following instructions which is not expected.
Change-Id: I810684f37f61c41c6f95a3bb36914d0765da8571
Signed-off-by: Jimmy Huang <jimmy.huang@mediatek.com>