Caesar Wang [Wed, 25 May 2016 11:03:04 +0000 (19:03 +0800)]
rockchip: add reset or power off gpio configuration for rk3399
We add plat parameter structs to support BL2 to pass variable-length,
variable-type parameters to BL31. The parameters are structured as a
link list. During bl31 setup time, we travse the list to process each
parameter. throuth this way, we can get the reset or power off gpio
parameter, and do hardware control in BL31. This structure also can
pass other parameter to BL31 in future.
Caesar Wang [Wed, 25 May 2016 11:21:43 +0000 (19:21 +0800)]
rockchip: support rk3399 gpio driver
There are 5 groups of GPIO (GPIO0~GPIO4), totally have 122 GPIOs
on rk3399 platform.
The pull direction(pullup or pulldown) for all of GPIOs are
software-programmable.
At the moment, we add the gpio basic driver since reset or power off
the devices from gpio configuration for BL31.
Caesar Wang [Wed, 25 May 2016 10:48:45 +0000 (18:48 +0800)]
gpio: support gpio set/get pull status
On some platform gpio can set/get pull status when input, add these
function so we can set/get gpio pull status when need it. And they are
optional function.
danh-arm [Tue, 24 May 2016 15:12:08 +0000 (16:12 +0100)]
Merge pull request #625 from antonio-nino-diaz-arm/an/delay-timer-v2
Implement generic delay timer and use it on platforms
Antonio Nino Diaz [Thu, 5 May 2016 14:25:02 +0000 (15:25 +0100)]
Replace Rockchip delay timer by generic one
Use the generic delay timer instead of having a specific platform
file for configuring it.
Change-Id: Ifa68b9c97cd96ae1190cee74d22d729af95e4537
Antonio Nino Diaz [Thu, 5 May 2016 14:23:56 +0000 (15:23 +0100)]
Replace MediaTek delay timer by generic one
Use the generic delay timer instead of having a specific platform
file for configuring it.
Change-Id: If6b8f60bc04230f4b85b2bcc1b670fc65461214e
Antonio Nino Diaz [Tue, 17 May 2016 08:48:10 +0000 (09:48 +0100)]
Replace SP804 timer by generic delay timer on FVP
Added a build flag to select the generic delay timer on FVP instead
of the SP804 timer. By default, the generic one will be selected. The
user guide has been updated.
Change-Id: Ica34425c6d4ed95a187b529c612f6d3b26b78bc6
Antonio Nino Diaz [Wed, 18 May 2016 09:37:25 +0000 (10:37 +0100)]
Implement generic delay timer
Add delay timer implementation based on the system generic counter.
This either uses the platform's implementation of
`plat_get_syscnt_freq()` or explicit clock multiplier/divider values
provided by the platform.
The current implementation of udelay has been modified to avoid
unnecessary calculations while waiting on the loop and to make it
easier to check for overflows.
Change-Id: I9062e1d506dc2f68367fd9289250b93444721732
Antonio Nino Diaz [Thu, 19 May 2016 09:00:28 +0000 (10:00 +0100)]
Implement plat_get_syscnt_freq2 on platforms
Replaced plat_get_syscnt_freq by plat_get_syscnt_freq2 on all
upstream platforms.
Change-Id: I3248f3f65a16dc5e9720012a05c35b9e3ba6abbe
Antonio Nino Diaz [Wed, 18 May 2016 15:53:31 +0000 (16:53 +0100)]
Add 32 bit version of plat_get_syscnt_freq
Added plat_get_syscnt_freq2, which is a 32 bit variant of the 64 bit
plat_get_syscnt_freq. The old one has been flagged as deprecated.
Common code has been updated to use this new version. Porting guide
has been updated.
Change-Id: I9e913544926c418970972bfe7d81ee88b4da837e
danh-arm [Thu, 12 May 2016 14:04:44 +0000 (15:04 +0100)]
Merge pull request #622 from mtk09422/hw-crypt-v3
Hw crypt v3
Yi Zheng [Wed, 11 May 2016 10:45:20 +0000 (18:45 +0800)]
MT8173: Add Sip function for MTK HW crypt driver
Change-Id: Idc40cc6243e532567ec4334ae37d97c003c90bfa
Signed-off-by: Yi Zheng <yi.zheng@mediatek.com>
Jimmy Huang [Wed, 11 May 2016 10:04:09 +0000 (18:04 +0800)]
mt8173: Reorganize plat SiP functions
Due to the changes in Mediatek platform common code, we need to move
plat related SiP functions to plat folder.
Change-Id: I6b14b988235205a5858b4bf49043bc79d0512b06
Signed-off-by: Jimmy Huang <jimmy.huang@mediatek.com>
danh-arm [Wed, 11 May 2016 09:56:25 +0000 (10:56 +0100)]
Merge pull request #619 from sandrine-bailleux-arm/sb/rockchip-assertions
Rockchip: Add some debug assertions in the PMU driver
Sandrine Bailleux [Thu, 5 May 2016 09:04:15 +0000 (10:04 +0100)]
Rockchip: Add some debug assertions in the PMU driver
This patch adds some debug assertions ensuring that array indices
are within the bounds of the array.
Change-Id: I96ee81d14834c1e92cdfb7e60b49995cdacfd93a
danh-arm [Wed, 4 May 2016 16:10:31 +0000 (17:10 +0100)]
Merge pull request #618 from rockchip-linux/fixes-for-suspend/resume
rockchip: support the suspend/resume for rk3399
danh-arm [Wed, 4 May 2016 12:47:49 +0000 (13:47 +0100)]
Merge pull request #617 from leon-chen-mtk/refactor_common_1
Refactor MediaTek platform common code
Caesar Wang [Sun, 10 Apr 2016 06:11:07 +0000 (14:11 +0800)]
rockchip: support the suspend/resume for rk3399
This patch adds to support the suspend/resume for rk3399 SoCs.
Signed-off-by: Shengfei xu <xsf@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
danh-arm [Wed, 4 May 2016 09:32:41 +0000 (10:32 +0100)]
Merge pull request #614 from soby-mathew/sm/rem_fvp_ve_memmap
FVP: Remove VE memory map support and change default GIC driver
Leon Chen [Thu, 28 Apr 2016 06:07:42 +0000 (14:07 +0800)]
Refactor MediaTek platform common code
Refactor MediaTek platform common code for further mt6795 upstream.
Soby Mathew [Thu, 7 Apr 2016 16:40:04 +0000 (17:40 +0100)]
Change the default driver to GICv3 in FVP
This patch changes the default driver for FVP platform from the deprecated
GICv3 legacy to the GICv3 only driver. This means that the default build of
Trusted Firmware will not be able boot Linux kernel with GICv2 FDT blob. The
user guide is also updated to reflect this change of default GIC driver for
FVP.
Change-Id: Id6fc8c1ac16ad633dabb3cd189b690415a047764
Soby Mathew [Wed, 13 Jan 2016 17:06:00 +0000 (17:06 +0000)]
Remove support for legacy VE memory map in FVP
This patch removes support for legacy Versatile Express memory map for the
GIC peripheral in the FVP platform. The user guide is also updated for the
same.
Change-Id: Ib8cfb819083aca359e5b46b5757cb56cb0ea6533
danh-arm [Wed, 27 Apr 2016 11:31:23 +0000 (12:31 +0100)]
Merge pull request #597 from hzhuang1/emmc_v3.2
Emmc v3
Haojian Zhuang [Fri, 18 Mar 2016 14:08:26 +0000 (22:08 +0800)]
drivers: add emmc stack
In a lot of embedded platforms, eMMC device is the only one storage
device. So loading content from eMMC device is required in ATF.
Create the emmc stack that could co-work with IO block driver.
Support to read/write/erase eMMC blocks on both rpmb and normal
user area. Support to change the IO speed and bus width.
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Haojian Zhuang [Thu, 21 Apr 2016 02:52:52 +0000 (10:52 +0800)]
Document: add MAX_IO_BLOCK_DEVICES platform macro
Add MAX_IO_BLOCK_DEVICES in porting guide. It's necessary to define
this macro to support io block device. With this macro, multiple
block devices could be opened at the same time. Each block device
stores its own state.
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Haojian Zhuang [Fri, 18 Mar 2016 07:14:19 +0000 (15:14 +0800)]
IO: support block device type
FIP is accessed as memory-mapped type. eMMC is block device type.
In order to support FIP based on eMMC, add the new io_block layer.
io_block always access eMMC device as block size. And it'll only
copy the required data into buffer in io_block driver. So preparing
an temporary buffer is required.
When use io_block device, MAX_IO_BLOCK_DEVICES should be declared
in platform_def.h. It's used to support multiple block devices.
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
danh-arm [Wed, 27 Apr 2016 08:58:56 +0000 (09:58 +0100)]
Merge pull request #612 from sandrine-bailleux-arm/sb/fix-xlat-lib-path
Doc: Fix the path to the xlat lib
danh-arm [Wed, 27 Apr 2016 08:40:05 +0000 (09:40 +0100)]
Merge pull request #610 from bjackman/bj/fip-create-exit-code
fip_create: Fix exit status for missing output filename (2)
danh-arm [Wed, 27 Apr 2016 08:38:40 +0000 (09:38 +0100)]
Merge pull request #611 from sandrine-bailleux-arm/sb/fix-init_xlation_table_inner
Fix computation of L1 bitmask in the translation table lib
Sandrine Bailleux [Tue, 26 Apr 2016 13:49:57 +0000 (14:49 +0100)]
Doc: Fix the path to the xlat lib
The translation table library code has moved from lib/aarch64/ to
lib/xlat_tables/ since commit
3ca9928df but the Porting Guide still
points to the old location. This patch fixes this issue.
Change-Id: I983a9a100d70eacf6bac71725ffbb4bb5f3732b0
Brendan Jackman [Mon, 25 Apr 2016 07:35:35 +0000 (15:35 +0800)]
fip_create: Fix exit status for missing output filename
Change-Id: I0d298eea9eaf47121c87637c7395e5d9868aa272
Sandrine Bailleux [Fri, 22 Apr 2016 09:47:33 +0000 (10:47 +0100)]
Fix computation of L1 bitmask in the translation table lib
This patch fixes the computation of the bitmask used to isolate
the level 1 field of a virtual address. The whole computation needs
to work on 64-bit values to produce the correct bitmask value.
XLAT_TABLE_ENTRIES_MASK being a C constant, it is a 32-bit value
so it needs to be extended to a 64-bit value before it takes part
in any other computation.
This patch fixes this bug by casting XLAT_TABLE_ENTRIES_MASK as
an unsigned long long.
Note that this bug doesn't manifest itself in practice because
address spaces larger than 39 bits are not yet supported in the
Trusted Firmware.
Change-Id: I955fd263ecb691ca94b29b9c9f576008ce1d87ee
danh-arm [Tue, 26 Apr 2016 13:58:57 +0000 (14:58 +0100)]
Merge pull request #605 from yatharth-arm/yk/sys_counter_fix
Conditionally compile `plat_get_syscnt_freq()` in ARM standard platforms
Yatharth Kochar [Tue, 26 Apr 2016 09:36:29 +0000 (10:36 +0100)]
Conditionally compile `plat_get_syscnt_freq()` in ARM standard platforms
This patch puts the definition of `plat_get_syscnt_freq()`
under `#ifdef ARM_SYS_CNTCTL_BASE` in arm_common.c file.
This is the fix for compilation error introduced by commit-id
`
749ade4`, for platforms that use arm_common.c but do not
provide a memory mapped interface to the generic counter.
Fixes ARM-software/tf-issues#395
Change-Id: I2f2b10bd9500fa15308541ccb15829306a76a745
danh-arm [Mon, 25 Apr 2016 13:52:14 +0000 (14:52 +0100)]
Merge pull request #604 from sandrine-bailleux-arm/sb/validate-psci_cpu_on_start-args
Validate psci_cpu_on_start() arguments
danh-arm [Mon, 25 Apr 2016 13:50:46 +0000 (14:50 +0100)]
Merge pull request #602 from rockchip-linux/fixes-for-coreboot_v1
rockchip: fixes for the required
danh-arm [Mon, 25 Apr 2016 13:50:27 +0000 (14:50 +0100)]
Merge pull request #603 from yatharth-arm/yk/sys_counter
Move `plat_get_syscnt_freq()` to arm_common.c
Sandrine Bailleux [Mon, 25 Apr 2016 08:28:43 +0000 (09:28 +0100)]
Remove unused argument in psci_cpu_on_start()
The "end power level" value passed as the 3rd argument to the
psci_cpu_on_start() function is not used so this patch removes it.
Change-Id: Icaa68b8c4ecd94507287970455fbff354faaa41e
Sandrine Bailleux [Fri, 22 Apr 2016 12:00:19 +0000 (13:00 +0100)]
Validate psci_cpu_on_start() arguments
This patch introduces some debug assertions in the function
psci_cpu_on_start() to check the arguments it receives are
valid.
Change-Id: If4d23c9f668fb46f2d18c5e2ed1929498cc6736b
Caesar Wang [Tue, 19 Apr 2016 12:42:17 +0000 (20:42 +0800)]
rockchip: fixes for the required
This patch has the following change for rk3399.
* Set the uart to 115200 since the loader decide to set
uart baud to 115200Hz. So the ATF also should set uart baud to 115200.
* We need ensure the bl31 base is greater than 4KB since there are have
the shared mem for coreboot.(Note: the previous vesion was tested with uboot)
Otherwise, we will happen the exception crash since the ddr area won't
to work from the shared ram address in some cases.
For example, the exception crash:
CBFS: Found @ offset 19c80 size 24074
exception _sync_sp_el0
ELR = 0x0000000000008000
ESR = 0x0000000002000000
SPSR = 0x600003cc
FAR = 0xffffffff00000000
SP = 0x00000000ff8ed230
...
X29 = 0x00000000ff8c1fc0
X30 = 0x000000000030e3b0
exception death
Change-Id: I8bc557c6bcaf6804d2a313b38667d3e2517881d7
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
danh-arm [Fri, 22 Apr 2016 09:13:16 +0000 (10:13 +0100)]
Merge pull request #601 from sandrine-bailleux-arm/sb/a57-errata-workarounds
Cortex-A57 errata workarounds
danh-arm [Fri, 22 Apr 2016 09:04:58 +0000 (10:04 +0100)]
Merge pull request #598 from antonio-nino-diaz-arm/an/xlat-overlap
Limit support for region overlaps in xlat_tables
Yatharth Kochar [Thu, 14 Apr 2016 13:49:37 +0000 (14:49 +0100)]
Move `plat_get_syscnt_freq()` to arm_common.c
This patch moves the definition for `plat_get_syscnt_freq()`
from arm_bl31_setup.c to arm_common.c. This could be useful
in case a delay timer needs to be installed based on the
generic timer in other BLs.
This patch also modifies the return type for this function
from `uint64_t` to `unsigned long long` within ARM and other
platform files.
Change-Id: Iccdfa811948e660d4fdcaae60ad1d700e4eda80d
Sandrine Bailleux [Thu, 21 Apr 2016 10:30:41 +0000 (11:30 +0100)]
Doc: Add links to the A53/A57 Errata Notice documents
This patch adds links to the Cortex-A53 and Cortex-A57 MPCores
Software Developers Errata Notice documents in the ARM CPU Specific
Build Macros document.
Change-Id: I0aa26d7f373026097ed012a02bc61ee2c5b9d6fc
Sandrine Bailleux [Thu, 21 Apr 2016 10:10:52 +0000 (11:10 +0100)]
Add support for Cortex-A57 erratum 833471 workaround
Change-Id: I86ac81ffd7cd094ce68c4cceb01c16563671a063
Sandrine Bailleux [Thu, 14 Apr 2016 13:24:13 +0000 (14:24 +0100)]
Add support for Cortex-A57 erratum 826977 workaround
Change-Id: Icaacd19c4cef9c10d02adcc2f84a4d7c97d4bcfa
Sandrine Bailleux [Thu, 14 Apr 2016 13:18:07 +0000 (14:18 +0100)]
Add support for Cortex-A57 erratum 829520 workaround
Change-Id: Ia2ce8aa752efb090cfc734c1895c8f2539e82439
Sandrine Bailleux [Thu, 14 Apr 2016 13:04:48 +0000 (14:04 +0100)]
Add support for Cortex-A57 erratum 828024 workaround
Change-Id: I632a8c5bb517ff89c69268e865be33101059be7d
danh-arm [Thu, 21 Apr 2016 11:51:27 +0000 (12:51 +0100)]
Merge pull request #594 from jcastillo-arm/jc/user-guide
Update User Guide and move up to Linaro 16.02
Sandrine Bailleux [Thu, 14 Apr 2016 12:32:31 +0000 (13:32 +0100)]
Add support for Cortex-A57 erratum 826974 workaround
Change-Id: I45641551474f4c58c638aff8c42c0ab9a8ec78b4
Sandrine Bailleux [Thu, 14 Apr 2016 11:59:42 +0000 (12:59 +0100)]
Fix wording in cpu-ops.mk comments
The CPU errata build flags don't enable errata, they enable errata
workarounds.
Change-Id: Ica65689d1205fc54eee9081a73442144b973400f
danh-arm [Mon, 18 Apr 2016 11:04:22 +0000 (12:04 +0100)]
Merge pull request #595 from sandrine-bailleux-arm/sb/unoptimised-build
Add support for unoptimised (-O0) build
Antonio Nino Diaz [Wed, 30 Mar 2016 14:45:57 +0000 (15:45 +0100)]
Limit support for region overlaps in xlat_tables
The only case in which regions can now overlap is if they are
identity mapped or they have the same virtual to physical address
offset (identity mapping is just a particular case of the latter).
They must overlap completely (i.e. one of them must be completely
inside the other one) and not cover the same area.
This allow future enhancements to the xlat_tables library without
having to support unnecessarily complex edge cases.
Outer regions are now sorted by mmap_add_region() before inner
regions with the same base virtual address for consistency: all
regions contained inside another one must be placed after the outer
one in the list.
If an inner region has the same attributes as the outer ones it will
be merged when creating the tables with init_xlation_table(). This
cannot be done as regions are added because there may be cases where
adding a region makes previously mergeable regions no longer
mergeable.
If the attributes of an inner region are different than the outer
region, new pages will be generated regardless of how "restrictive"
they are. For example, RO memory is more restrictive than RW. The
old implementation would give priority to RO if there is an overlap,
the new one doesn't.
NOTE: THIS IS THEORETICALLY A COMPATABILITY BREAK FOR PLATFORMS THAT
USE THE XLAT_TABLES LIBRARY IN AN UNEXPECTED WAY. PLEASE RAISE A
TF-ISSUE IF YOUR PLATFORM IS AFFECTED.
Change-Id: I75fba5cf6db627c2ead70da3feb3cc648c4fe2af
danh-arm [Thu, 14 Apr 2016 18:15:36 +0000 (19:15 +0100)]
Merge pull request #549 from ljerry/tf_issue_373
Allow to dump platform-defined regs in crash log
Gerald Lejeune [Thu, 26 Nov 2015 14:47:53 +0000 (15:47 +0100)]
Dump platform-defined regs in crash reporting
It is up to the platform to implement the new plat_crash_print_regs macro to
report all relevant platform registers helpful for troubleshooting.
plat_crash_print_regs merges or calls previously defined plat_print_gic_regs
and plat_print_interconnect_regs macros for each existing platforms.
NOTE: THIS COMMIT REQUIRES ALL PLATFORMS THAT ENABLE THE `CRASH_REPORTING`
BUILD FLAG TO MIGRATE TO USE THE NEW `plat_crash_print_regs()` MACRO. BY
DEFAULT, `CRASH_REPORTING` IS ENABLED IN DEBUG BUILDS FOR ALL PLATFORMS.
Fixes: arm-software/tf-issues#373
Signed-off-by: Gerald Lejeune <gerald.lejeune@st.com>
Sandrine Bailleux [Mon, 11 Apr 2016 12:17:50 +0000 (13:17 +0100)]
Fix build error with optimizations disabled (-O0)
If Trusted Firmware is built with optimizations disabled (-O0), the
linker throws the following error:
undefined reference to 'xxx'
Where 'xxx' is a raw inline function defined in a header file. The
reason is that, with optimizations disabled, GCC may decide to skip
the inlining. If that is the case, an external definition to the
compilation unit must be provided. Because no external definition
is present, the linker throws the error.
This patch fixes the problem by declaring the following inline
functions static, so the internal definition is used:
- cm_set_next_context()
- bakery_lock_init()
Note that building the TF with optimizations disabled when Trusted
Board Boot is enabled is currently unsupported, as this makes the BL2
image too big to fit in memory without any adjustment of its base
address. Similarly, disabling optimizations for debug builds on FVP
is unsupported at the moment.
Change-Id: I284a9f84cc8df96a0c1a52dfe05c9e8544c0cefe
Sandrine Bailleux [Mon, 11 Apr 2016 12:01:17 +0000 (13:01 +0100)]
Give user's compiler flags precedence over default ones
The user can provide additional CFLAGS to use when building TF.
However, these custom CFLAGS are currently prepended to the
standard CFLAGS that are hardcoded in the TF build system. This
is an issue because when providing conflicting compiler flags
(e.g. different optimisations levels like -O1 and -O0), the last
one on the command line usually takes precedence. This means that
the user flags get overriden.
To address this problem, this patch separates the TF CFLAGS from
the user CFLAGS. The former are now stored in the TF_CFLAGS make
variable, whereas the CFLAGS make variable is untouched and reserved
for the user. The order of the 2 sets of flags is enforced when
invoking the compiler.
Fixes ARM-Software/tf-issues#350
Change-Id: Ib189f44555b885f1dffbec6015092f381600e560
Juan Castillo [Wed, 17 Feb 2016 16:54:39 +0000 (16:54 +0000)]
Update User Guide and move up to Linaro 16.02
This patch updates the TF User Guide, simplifying some of the steps
to build and run TF and trying to avoid duplicated information that
is already available on the ARM Connected Community or the Linaro
website.
The recommended Linaro release is now 16.02.
Change-Id: I21db486d56a07bb10f5ee9a33014ccc59ca12986
danh-arm [Thu, 14 Apr 2016 11:17:44 +0000 (12:17 +0100)]
Merge pull request #593 from mtk09422/mtcmos-fix
mt8173: Fix timing issue of mfg mtcmos power off
danh-arm [Thu, 14 Apr 2016 10:39:46 +0000 (11:39 +0100)]
Merge pull request #591 from soby-mathew/sm/xlat_common
Refactor the xlat_tables library
Fan Chen [Fri, 1 Apr 2016 10:35:43 +0000 (18:35 +0800)]
mt8173: Fix timing issue of mfg mtcmos power off
In mt8173, there are totally 10 non-cpu mtcmos, so we cannot tell
if SPM finished the power control flow by 10 status bits of PASR_PDP_3.
So, extend PASR_PDP_3 status bits from 10 to 20 so that we can
make sure if the control action has been done precisely.
Change-Id: Ifd4faaa4173c6e0543aa8471149adb9fe7fadedc
Signed-off-by: Fan Chen <fan.chen@mediatek.com>
Soby Mathew [Fri, 8 Apr 2016 15:42:58 +0000 (16:42 +0100)]
Migrate platform ports to the new xlat_tables library
This patch modifies the upstream platform port makefiles to use the new
xlat_tables library files. This patch also makes mmap region setup common
between AArch64 and AArch32 for FVP platform port. The file `fvp_common.c`
is moved from the `plat/arm/board/fvp/aarch64` folder to the parent folder
as it is not specific to AArch64.
Change-Id: Id2e9aac45e46227b6f83cccfd1e915404018ea0b
Soby Mathew [Tue, 22 Mar 2016 15:51:08 +0000 (15:51 +0000)]
Refactor the xlat_tables library code
The AArch32 long descriptor format and the AArch64 descriptor format
correspond to each other which allows possible sharing of xlat_tables
library code between AArch64 and AArch32. This patch refactors the
xlat_tables library code to seperate the common functionality from
architecture specific code. Prior to this patch, all of the xlat_tables
library code were in `lib/aarch64/xlat_tables.c` file. The refactored code
is now in `lib/xlat_tables/` directory. The AArch64 specific programming
for xlat_tables is in `lib/xlat_tables/aarch64/xlat_tables.c` and the rest
of the code common to AArch64 and AArch32 is in
`lib/xlat_tables/xlat_tables_common.c`. Also the data types used in
xlat_tables library APIs are reworked to make it compatible between AArch64
and AArch32.
The `lib/aarch64/xlat_tables.c` file now includes the new xlat_tables
library files to retain compatibility for existing platform ports.
The macros related to xlat_tables library are also moved from
`include/lib/aarch64/arch.h` to the header `include/lib/xlat_tables.h`.
NOTE: THE `lib/aarch64/xlat_tables.c` FILE IS DEPRECATED AND PLATFORM PORTS
ARE EXPECTED TO INCLUDE THE NEW XLAT_TABLES LIBRARY FILES IN THEIR MAKEFILES.
Change-Id: I3d17217d24aaf3a05a4685d642a31d4d56255a0f
danh-arm [Wed, 13 Apr 2016 09:03:00 +0000 (10:03 +0100)]
Merge pull request #590 from yatharth-arm/yk/tzc400
Use unsigned long long instead of uintptr_t in TZC400/DMC500 drivers
Yatharth Kochar [Fri, 8 Apr 2016 13:40:44 +0000 (14:40 +0100)]
Use unsigned long long instead of uintptr_t in TZC400/DMC500 drivers
Currently the `tzc400_configure_region` and `tzc_dmc500_configure_region`
functions uses uintptr_t as the data type for `region_top` and `region_base`
variables, which will be converted to 32/64 bits for AArch32/AArch64
respectively. But the expectation is to keep these addresses at least 64 bit.
This patch modifies the data types to make it at least 64 bit by using
unsigned long long instead of uintptr_t for the `region_top` and
`region_base` variables. It also modifies the associated macros
`_tzc##fn_name##_write_region_xxx` accordingly.
Change-Id: I4e3c6a8a39ad04205cf0f3bda336c3970b15a28b
danh-arm [Tue, 12 Apr 2016 13:47:54 +0000 (14:47 +0100)]
Merge pull request #589 from soby-mathew/sm/fix_rk_build_err
Fix build error in Rockchip platform
Soby Mathew [Tue, 12 Apr 2016 13:04:29 +0000 (14:04 +0100)]
Fix build error in Rockchip platform
This patch fixes the compilation error in Rockchip rk3368 platform port when
it is built in release mode.
Fixes ARM-software/tf-issues#389
Change-Id: I1a3508ac3a620289cf700e79db8f08569331ac53
danh-arm [Mon, 11 Apr 2016 09:23:47 +0000 (10:23 +0100)]
Merge pull request #579 from ashutoshksingh/master
pass r0-r6 as part of smc param
danh-arm [Fri, 8 Apr 2016 13:31:58 +0000 (14:31 +0100)]
Merge pull request #569 from Xilinx/zynqmp-v1
Support for Xilinx Zynq UltraScale+ MPSoC
danh-arm [Fri, 8 Apr 2016 12:51:46 +0000 (13:51 +0100)]
Merge pull request #588 from antonio-nino-diaz-arm/an/ignore-check-md
Fix style check and remove markdown files from it
Antonio Nino Diaz [Fri, 8 Apr 2016 10:51:19 +0000 (11:51 +0100)]
Remove markdown files from coding style check
All markdown (.md) files in the root directory of the repository and
all the files inside the 'docs' directory have been removed from
ROOT_DIRS_TO_CHECK in the Makefile in order not to perform the coding
style check on them.
Change-Id: Iac397b44f95cbcdb9a52cc20bf69998c394ac00a
Antonio Nino Diaz [Fri, 8 Apr 2016 10:49:10 +0000 (11:49 +0100)]
Fix list of paths to perform coding style check on
Removed an extra parentheses that produced an invalid list of files
and directories to check by checkpatch.pl.
Change-Id: Iefe2c1f8be6e7b7b58f6ffe3e16fe6336b9a8689
danh-arm [Fri, 8 Apr 2016 09:43:46 +0000 (10:43 +0100)]
Merge pull request #587 from antonio-nino-diaz-arm/an/rename-bl33-base
Rename BL33_BASE and make it work with RESET_TO_BL31
danh-arm [Fri, 8 Apr 2016 09:40:39 +0000 (10:40 +0100)]
Merge pull request #586 from antonio-nino-diaz-arm/an/spd-bl32
Remove BL32_BASE when building without SPD for FVP
danh-arm [Fri, 8 Apr 2016 09:36:11 +0000 (10:36 +0100)]
Merge pull request #585 from soby-mathew/sm/tf_printf_ll_changes
Differentiate `long` and `long long` formats in tf_printf
Antonio Nino Diaz [Wed, 6 Apr 2016 16:31:57 +0000 (17:31 +0100)]
Rename BL33_BASE option to PRELOADED_BL33_BASE
To avoid confusion the build option BL33_BASE has been renamed to
PRELOADED_BL33_BASE, which is more descriptive of what it does and
doesn't get mistaken by similar names like BL32_BASE that work in a
completely different way.
NOTE: PLATFORMS USING BUILD OPTION `BL33_BASE` MUST CHANGE TO THE NEW
BUILD OPTION `PRELOADED_BL33_BASE`.
Change-Id: I658925ebe95406edf0325f15aa1752e1782aa45b
Antonio Nino Diaz [Wed, 6 Apr 2016 14:05:54 +0000 (15:05 +0100)]
Fix BL33_BASE option to work with RESET_TO_BL31
The BL33 address is now set in arm_bl31_early_platform_setup() so
that the preloaded BL33 boot option is available when RESET_TO_BL31
is also used.
Change-Id: Iab93e3916f9199c3387886b055c7cd2315efed29
Antonio Nino Diaz [Tue, 5 Apr 2016 10:38:49 +0000 (11:38 +0100)]
Remove BL32_BASE when building without SPD for FVP
Previously, when building TF without SPD support, BL2 tried to load a
BL32 image from the FIP and fails to find one, which resulted on
warning messages on the console. Even if there is a BL32 image in the
FIP it shouldn't be loaded because there is no way to transfer
control to the Secure Payload without SPD support.
The Makefile has been modified to pass a define of the form
SPD_${SPD} to the source code the same way it's done for PLAT. The
define SPD_none is then used to undefine BL32_BASE when BL32 is not
used to prevent BL2 from trying to load a BL32 image and failing,
thus removing the warning messages mentioned above.
Fixes ARM-software/tf-issues#287
Change-Id: Ifeb6f1c26935efb76afd353fea88e87ba09e9658
Soby Mathew [Tue, 22 Mar 2016 17:38:00 +0000 (17:38 +0000)]
Differentiate `long` and `long long` formats in tf_printf
This patch adds support to differentiate between `long` and `long long`
format specifiers in tf_printf(). In AArch64, they are the same which is
a 64-bit word. But, in AArch32 they are different and tf_printf() needs
to handle these format specifiers separately. This patch also fixes the
type of variables used to generic C types.
Change-Id: If3bbb0245cd0183acbe13bc1fe0d9743f417578f
danh-arm [Thu, 7 Apr 2016 16:17:25 +0000 (17:17 +0100)]
Merge pull request #584 from soby-mathew/sm/enable_scr_sif
Enable SCR_EL3.SIF bit
danh-arm [Thu, 7 Apr 2016 16:16:51 +0000 (17:16 +0100)]
Merge pull request #583 from mtk09422/fix-build-error
mt8173: fix spm driver build errors
danh-arm [Thu, 7 Apr 2016 16:16:27 +0000 (17:16 +0100)]
Merge pull request #582 from jcastillo-arm/jc/fip_extract
fip_create: add support for image unpacking
danh-arm [Thu, 7 Apr 2016 16:11:45 +0000 (17:11 +0100)]
Merge pull request #578 from EvanLloyd/ejll/woa_make2
Make improvements for host environment portability
danh-arm [Thu, 7 Apr 2016 16:11:20 +0000 (17:11 +0100)]
Merge pull request #575 from soby-mathew/sm/new_tzc_driver
Refactor the TZC driver and add DMC-500 driver
danh-arm [Thu, 7 Apr 2016 16:10:44 +0000 (17:10 +0100)]
Merge pull request #572 from jcastillo-arm/jc/tbb_nvcounter
TBB NVcounter support
danh-arm [Thu, 7 Apr 2016 16:09:48 +0000 (17:09 +0100)]
Merge pull request #563 from sbranden/tf_issue_380
Add support for %z in tf_print()
Soby Mathew [Mon, 4 Apr 2016 11:34:24 +0000 (12:34 +0100)]
Enable SCR_EL3.SIF bit
This patch enables the SCR_EL3.SIF (Secure Instruction Fetch) bit in BL1 and
BL31 common architectural setup code. When in secure state, this disables
instruction fetches from Non-secure memory.
NOTE: THIS COULD BREAK PLATFORMS THAT HAVE SECURE WORLD CODE EXECUTING FROM
NON-SECURE MEMORY, BUT THIS IS CONSIDERED UNLIKELY AND IS A SERIOUS SECURITY
RISK.
Fixes ARM-Software/tf-issues#372
Change-Id: I684e84b8d523c3b246e9a5fabfa085b6405df319
yt.lee [Thu, 7 Apr 2016 05:28:57 +0000 (13:28 +0800)]
mt8173: fix spm driver build errors
To fix build errors in following build conditions,
DEBUG=1 LOG_LEVEL<40
DEBUG=0 LOG_LEVEL>=40
Change-Id: Ib34aed07b2ae0abd8a3a46948adc9fbeaae715aa
Signed-off-by: yt.lee <yt.lee@mediatek.com>
Soren Brinkmann [Wed, 9 Mar 2016 08:58:23 +0000 (00:58 -0800)]
Add Xilinx to acknowledgements file
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Soren Brinkmann [Mon, 7 Mar 2016 04:16:27 +0000 (20:16 -0800)]
Add support for Xilinx Zynq UltraScale+ MPSOC
The Xilinx Zynq UltraScale+ MPSOC containes a quad A53 cluster. This
patch adds the platform port for that SoC.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Juan Castillo [Mon, 15 Feb 2016 17:21:10 +0000 (17:21 +0000)]
fip_create: add support for image unpacking
This patch adds support for image unpacking to the FIP packaging
tool. Command line option '-u,--unpack' may be used to unpack the
contents of an existing FIP file into the working directory. The
tool uses default hardcoded filenames for the unpacked images. If
the files already exist, they can be overwritten by specifying the
option '-f,--force'.
Change-Id: I360b11d9c5403e8c0a7a9cac32c1d90ebb228063
danh-arm [Wed, 6 Apr 2016 11:43:33 +0000 (12:43 +0100)]
Merge pull request #581 from rockchip-linux/rockchip-atf-
20160405
Support for Rockchip's family SoCs
Tony Xie [Fri, 15 Jan 2016 09:17:32 +0000 (17:17 +0800)]
Support for Rockchip's family SoCs
This patch adds to support the RK3368 and RK3399 SoCs.
RK3368/RK3399 is one of the Rockchip family SoCs, which is an
multi-cores ARM SoCs.
This patch adds support to boot the Trusted Firmware on RK3368/RK3399
SoCs, and adds support to boot secondary CPUs, enter/exit core
power states for all CPUs in the slow/fast clusters.
This is the initial version for rockchip SoCs.(RK3368/RK3399 and next SoCs)
* Support arm gicv2 & gicv3.
* Boot up multi-cores CPU.
* Add generic CPU helper functions.
* Support suspend/resume.
* Add system_off & system_reset implementation.
* Add delay timer platform implementation.
* Support the new porting interface for the PSCI implementation.
Change-Id: I704bb3532d65e8c70dbd99b512c5e6e440ea6f43
Signed-off-by: Tony Xie <tony.xie@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Shengfei xu <xsf@rock-chips.com>
danh-arm [Mon, 4 Apr 2016 12:39:32 +0000 (13:39 +0100)]
Merge pull request #580 from soby-mathew/sm/ret_type_plat_ns_ep
Modify return type of plat_get_ns_image_entrypoint()
Soren Brinkmann [Mon, 7 Mar 2016 04:23:39 +0000 (20:23 -0800)]
arm: common: Make timer configuration conditional
Make the timer configuration conditional on the optional interface being
available.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Soren Brinkmann [Mon, 7 Mar 2016 04:14:51 +0000 (20:14 -0800)]
drivers: Add Cadence UART driver
Add a driver for the Cadence UART which is found in Xilinx Zynq SOCs.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Soby Mathew [Wed, 23 Mar 2016 10:11:10 +0000 (10:11 +0000)]
Modify return type of plat_get_ns_image_entrypoint()
This patch modifies the return type of the platform API
`plat_get_ns_image_entrypoint()` from `unsigned long` to
`uintptr_t` in accordance with the coding guidelines.
Change-Id: Icb4510ca98b706aa4d535fe27e203394184fb4ca
danh-arm [Fri, 1 Apr 2016 16:41:10 +0000 (17:41 +0100)]
Merge pull request #577 from antonio-nino-diaz-arm/an/remove-xlat-helpers
Remove xlat_helpers.c
danh-arm [Fri, 1 Apr 2016 16:40:54 +0000 (17:40 +0100)]
Merge pull request #576 from mtk09422/bl31-security
mt8173: Protect BL31 memory from non-secure access
Ashutosh Singh [Thu, 31 Mar 2016 16:18:34 +0000 (17:18 +0100)]
pass r0-r6 as part of smc param
In new communication protocol between optee os and linux driver,
r0-r6 registers are used. opteed need to copy these registers
as well when optee context registers are initialized.
Change-Id: Ifb47b73f847c61746cb58ea78411c1c71f208030
Signed-off-by: Ashutosh Singh <ashutosh.singh@arm.com>