Hadi Asyrafi [Wed, 14 Aug 2019 05:49:00 +0000 (13:49 +0800)]
intel: agilex: Fix reliance on hard coded clock information
Extract clock information for UART, MMC & Watchdog from the clock manager
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I42d3d4ceeaf45788d457472f6ddcd3fe099f0133
Sandrine Bailleux [Wed, 7 Aug 2019 14:20:01 +0000 (14:20 +0000)]
Merge changes from topic "intel-plat-refactor" into integration
* changes:
intel: Platform common code refactor
intel: Platform common code refactor
Hadi Asyrafi [Thu, 1 Aug 2019 06:48:39 +0000 (14:48 +0800)]
intel: Platform common code refactor
Pull out common code from aarch64 and include
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I4d0f5e1bb01bcdacbedf8e6c359de594239b645f
Sandrine Bailleux [Tue, 6 Aug 2019 14:54:35 +0000 (14:54 +0000)]
Merge changes from topic "qemu_sbsa" into integration
* changes:
plat/qemu: add gicv3 support for qemu
plat/qemu: move gicv2 codes to separate file
Sandrine Bailleux [Tue, 6 Aug 2019 11:04:10 +0000 (11:04 +0000)]
Merge "meson: gxl: Fix CPU hotplug" into integration
Alexei Fedorov [Fri, 2 Aug 2019 12:50:31 +0000 (12:50 +0000)]
Merge "intel: stratix10: Fix BL31 memory mapping" into integration
Alexei Fedorov [Fri, 2 Aug 2019 12:50:04 +0000 (12:50 +0000)]
Merge "meson: gxl: Fix reset and power off" into integration
Hadi Asyrafi [Thu, 1 Aug 2019 03:29:48 +0000 (11:29 +0800)]
intel: stratix10: Fix BL31 memory mapping
Previous config blocks ATF runtime service communications with SDM mailbox
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Ia857facd0bd0790056df94ed1e016bcf619a161e
Remi Pommarel [Tue, 30 Jul 2019 16:04:38 +0000 (18:04 +0200)]
meson: gxl: Fix CPU hotplug
The CPU[1-3] are reset to initial/cold boot state (with their reset
address set to 0x0). In this state the cpus are waiting for another
one to set the reset address to bl31_warm_entrypoint and wake them up.
The CPU0 needs a bit of a workaround as changing the reset address
either through PSCI mailbox or the mmio mapped RVBAR (at 0xda834650)
does not seem to have any effect. Thus the workaround consists in
emulating the other CPUs' behavior with a WFE loop and manually jumping
to bl31_warm_entrypoint when woken back up by another one.
Change-Id: I11265620b5fd0619285e3993253a3f9a3ff6a7a4
Signed-off-by: Remi Pommarel <repk@triplefau.lt>
Remi Pommarel [Thu, 4 Apr 2019 21:12:56 +0000 (23:12 +0200)]
meson: gxl: Fix reset and power off
Before CPU enters standby state (wfi), the AP needs to signal the SCP
through PSCI mailbox.
Also at boot time the AP has to wait for the SCP to be ready before
sending the first scpi commands or it can crash.
Change-Id: Iacc99f5bec745ad71922c5ea07ca5b87088133b6
Signed-off-by: Remi Pommarel <repk@triplefau.lt>
Alexei Fedorov [Fri, 2 Aug 2019 10:21:53 +0000 (10:21 +0000)]
Merge "Switch AARCH32/AARCH64 to __aarch64__" into integration
Alexei Fedorov [Fri, 2 Aug 2019 08:57:02 +0000 (08:57 +0000)]
Merge "Replace __ASSEMBLY__ with compiler-builtin __ASSEMBLER__" into integration
Julius Werner [Tue, 9 Jul 2019 21:02:43 +0000 (14:02 -0700)]
Switch AARCH32/AARCH64 to __aarch64__
NOTE: AARCH32/AARCH64 macros are now deprecated in favor of __aarch64__.
All common C compilers pre-define the same macros to signal which
architecture the code is being compiled for: __arm__ for AArch32 (or
earlier versions) and __aarch64__ for AArch64. There's no need for TF-A
to define its own custom macros for this. In order to unify code with
the export headers (which use __aarch64__ to avoid another dependency),
let's deprecate the AARCH32 and AARCH64 macros and switch the code base
over to the pre-defined standard macro. (Since it is somewhat
unintuitive that __arm__ only means AArch32, let's standardize on only
using __aarch64__.)
Change-Id: Ic77de4b052297d77f38fc95f95f65a8ee70cf200
Signed-off-by: Julius Werner <jwerner@chromium.org>
Julius Werner [Tue, 9 Jul 2019 20:49:11 +0000 (13:49 -0700)]
Replace __ASSEMBLY__ with compiler-builtin __ASSEMBLER__
NOTE: __ASSEMBLY__ macro is now deprecated in favor of __ASSEMBLER__.
All common C compilers predefine a macro called __ASSEMBLER__ when
preprocessing a .S file. There is no reason for TF-A to define it's own
__ASSEMBLY__ macro for this purpose instead. To unify code with the
export headers (which use __ASSEMBLER__ to avoid one extra dependency),
let's deprecate __ASSEMBLY__ and switch the code base over to the
predefined standard.
Change-Id: Id7d0ec8cf330195da80499c68562b65cb5ab7417
Signed-off-by: Julius Werner <jwerner@chromium.org>
Alexei Fedorov [Thu, 1 Aug 2019 10:41:59 +0000 (10:41 +0000)]
Merge "doc: Suggest to use the latest version 8.3 of GCC" into integration
Louis Mayencourt [Mon, 15 Jul 2019 09:23:58 +0000 (10:23 +0100)]
doc: Suggest to use the latest version 8.3 of GCC
At the time of writting, GCC 8.3-2019.03 is the latest version available
on developer.arm.com.
Switch to bare-metal toolchain (arm-eabi-) for AArch32. This allows to
have a finer control on the use of floating-point and SIMD instructions.
Change-Id: I4438401405eae1e5f6d531b0162e8fa06f69135e
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
Hadi Asyrafi [Thu, 1 Aug 2019 07:21:20 +0000 (15:21 +0800)]
intel: Platform common code refactor
Pull out common code from agilex and stratix10
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Iddc0a9e6eccb30823d7b15615d5ce9c6bedb2abc
Alexei Fedorov [Wed, 31 Jul 2019 16:21:46 +0000 (16:21 +0000)]
Merge "intel: agilex: Fix BL31 memory mapping" into integration
Alexei Fedorov [Wed, 31 Jul 2019 16:15:44 +0000 (16:15 +0000)]
Merge "Enable AMU for Cortex-Hercules" into integration
Balint Dobszay [Mon, 15 Jul 2019 09:46:20 +0000 (11:46 +0200)]
Enable AMU for Cortex-Hercules
Change-Id: Ie0a94783d0c8e111ae19fd592304e6485f04ca29
Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>
Alexei Fedorov [Wed, 31 Jul 2019 14:28:26 +0000 (14:28 +0000)]
Merge "uniphier: fix typo and coding style" into integration
Alexei Fedorov [Wed, 31 Jul 2019 14:28:21 +0000 (14:28 +0000)]
Merge "uniphier: replace DIV_ROUND_UP() with div_round_up() from utils_def.h" into integration
Alexei Fedorov [Wed, 31 Jul 2019 14:16:45 +0000 (14:16 +0000)]
Merge "rockchip: px30: Use new bl31_params_parse functions" into integration
Masahiro Yamada [Fri, 26 Jul 2019 11:04:28 +0000 (20:04 +0900)]
uniphier: fix typo and coding style
Fix the typo "warn" -> "warm".
Also fix the following checkpatch.pl warnings:
CHECK: Prefer using the BIT macro
CHECK: No space is necessary after a cast
CHECK: Alignment should match open parenthesis
CHECK: Unnecessary parentheses around uniphier_io_policies[image_id].dev_handle
Change-Id: Ic11eea2668c4bf2d1e8f089e6338ba7b7156d80b
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada [Fri, 26 Jul 2019 11:07:08 +0000 (20:07 +0900)]
uniphier: replace DIV_ROUND_UP() with div_round_up() from utils_def.h
Use the helper in utils_def.h instead of the own macro.
Change-Id: I527f9e75914d60f66354e365006b960ba5e8cbae
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Hadi Asyrafi [Tue, 30 Jul 2019 02:56:38 +0000 (10:56 +0800)]
intel: agilex: Fix BL31 memory mapping
Previous config blocks ATF runtime service communications with SDM mailbox
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Ic97aa381d3ceb96395595ec192132859d626b8d1
Ambroise Vincent [Mon, 29 Jul 2019 13:52:20 +0000 (14:52 +0100)]
rockchip: px30: Use new bl31_params_parse functions
This change is needed for the platform to compile following the changes
made in commits
cbdc72b559ab and
3e02c7436cf4.
Change-Id: I3468dd27f3b4f3095fb82f445d51cd8714311eb7
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
Soby Mathew [Fri, 26 Jul 2019 17:06:14 +0000 (17:06 +0000)]
Merge "sgm775: Fix build fail for TSP support on sgm775" into integration
Hongbo Zhang [Thu, 19 Apr 2018 06:42:23 +0000 (14:42 +0800)]
plat/qemu: add gicv3 support for qemu
This patch adds gicv3 support for qemu, in order not to break any legacy
use case, gicv2 is still set by default, gicv3 can be selected by
compiling parameter QEMU_USE_GIC_DRIVER=QEMU_GICV3.
Signed-off-by: Hongbo Zhang <hongbo.zhang@linaro.org>
Reviewed-by: Radoslaw Biernacki <radoslaw.biernacki@linaro.org>
Tested-by: Radoslaw Biernacki <radoslaw.biernacki@linaro.org>
Change-Id: Ic63f38abf16ed3c36aa60e80d50103cf05cf797b
Hongbo Zhang [Thu, 19 Apr 2018 05:06:07 +0000 (13:06 +0800)]
plat/qemu: move gicv2 codes to separate file
This file moves gicv2 codes to a new separate files, target is to add
gicv3 support later.
Signed-off-by: Hongbo Zhang <hongbo.zhang@linaro.org>
Reviewed-by: Radoslaw Biernacki <radoslaw.biernacki@linaro.org>
Tested-by: Radoslaw Biernacki <radoslaw.biernacki@linaro.org>
Change-Id: I30eb1fda5ea5c2b35d79360c52f46601cbca1bcc
Soby Mathew [Fri, 26 Jul 2019 10:26:37 +0000 (10:26 +0000)]
Merge "rockchip: px30: Fix build error" into integration
Soby Mathew [Fri, 26 Jul 2019 09:26:14 +0000 (09:26 +0000)]
Merge changes from topic "advk-serror" into integration
* changes:
marvell/a3700: Prevent SError accessing PCIe link while it is down
marvell: Switch to xlat_tables_v2
Soby Mathew [Fri, 26 Jul 2019 09:25:54 +0000 (09:25 +0000)]
Merge changes from topic "jun-add-imx7-pico" into integration
* changes:
plat: imx7: Add PicoPi iMX7D basic support
plat: imx7: refactor code for reuse
Soby Mathew [Thu, 25 Jul 2019 15:38:10 +0000 (15:38 +0000)]
Merge changes from topic "gby/cryptocell-multi-vers" into integration
* changes:
cryptocell: add product version awareness support
cryptocell: move Cryptocell specific API into driver
Ambroise Vincent [Thu, 25 Jul 2019 15:06:50 +0000 (16:06 +0100)]
rockchip: px30: Fix build error
"result of '1 << 31' requires 33 bits to represent, but 'int' only has
32 bits [-Werror=shift-overflow=]"
This is treated as an error since commit
93c690eba8ca ("Enable
-Wshift-overflow=2 to check for undefined shift behavior")
Only the actual errors are being tackled by this patch. It is up to the
platform to choose whether there needs to be further modifications to
the code.
Change-Id: I70860ae5f2a34d7c684bd491b76da50aa04f778e
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
Madhukar Pappireddy [Mon, 22 Jul 2019 22:39:51 +0000 (17:39 -0500)]
sgm775: Fix build fail for TSP support on sgm775
Fixed the path to a source file specified in tsp makefile
Created a platform specific tsp makefile
Change-Id: I89565127c67eff510e48e21fd450af4c3088c2d4
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
Soby Mathew [Thu, 25 Jul 2019 12:54:59 +0000 (12:54 +0000)]
Merge "Romlib makefile refactoring and script rewriting" into integration
Gilad Ben-Yossef [Tue, 14 May 2019 11:47:36 +0000 (14:47 +0300)]
cryptocell: add product version awareness support
Add support for multiple Cryptocell revisions which
use different APIs.
This commit only refactors the existing code in preperation to the addition
of another Cryptocell revisions later on.
Signed-off-by: Gilad Ben-Yossef <gilad.benyossef@arm.com>
Change-Id: I16d80b31afb6edd56dc645fee5ea619cc74f09b6
Gilad Ben-Yossef [Tue, 14 May 2019 07:48:18 +0000 (10:48 +0300)]
cryptocell: move Cryptocell specific API into driver
Code using Cryptocell specific APIs was used as part of the
arm common board ROT support, instead of being abstracted
in Cryptocell specific driver code, creating two problems:
- Any none arm board that uses Cryptocell wuld need to
copy and paste the same code.
- Inability to cleanly support multiple versions of Cryptocell
API and products.
Move over Cryptocell specific API calls into the Cryptocell
driver, creating abstraction API where needed.
Signed-off-by: Gilad Ben-Yossef <gilad.benyossef@arm.com>
Change-Id: I9e03ddce90fcc47cfdc747098bece86dbd11c58e
Soby Mathew [Thu, 25 Jul 2019 09:13:49 +0000 (09:13 +0000)]
Merge changes from topic "jts/spsr" into integration
* changes:
Refactor SPSR initialisation code
SSBS: init SPSR register with default SSBS value
Soby Mathew [Thu, 25 Jul 2019 09:04:21 +0000 (09:04 +0000)]
Merge changes I0d17ba6c,I540741d2,I9e6475ad,Ifd769320,I12c04a85, ... into integration
* changes:
plat/mediatek/mt81*: Use new bl31_params_parse() helper
plat/rockchip: Use new bl31_params_parse_helper()
Add helper to parse BL31 parameters (both versions)
Factor out cross-BL API into export headers suitable for 3rd party code
Use explicit-width data types in AAPCS parameter structs
plat/rockchip: Switch to use new common BL aux parameter library
Introduce lightweight BL platform parameter library
Julius Werner [Fri, 31 May 2019 00:34:08 +0000 (17:34 -0700)]
plat/mediatek/mt81*: Use new bl31_params_parse() helper
The Mediatek MT8173/MT8183 SoCs are prime candidates for switching to
the new bl31_params_parse() helper, so switch them over. This will allow
BL2 implementations on these platforms to transparently switch over to
the version 2 parameter structure.
Change-Id: I0d17ba6c455102d325a06503d2078a76d12b5deb
Signed-off-by: Julius Werner <jwerner@chromium.org>
Julius Werner [Thu, 30 May 2019 23:57:15 +0000 (16:57 -0700)]
plat/rockchip: Use new bl31_params_parse_helper()
The Rockchip platform is a prime candidate for switching to the new
bl31_params_parse_helper(), so switch it over. This will allow BL2
implementations on this platform to transparently switch over to the
version 2 parameter structure.
Change-Id: I540741d2425c93f66c8697ce749a351eb2b3a7e8
Signed-off-by: Julius Werner <jwerner@chromium.org>
Soby Mathew [Wed, 24 Jul 2019 16:18:01 +0000 (16:18 +0000)]
Merge "plat: imx8m: Add basic rdc module init driver" into integration
Soby Mathew [Wed, 24 Jul 2019 12:02:13 +0000 (12:02 +0000)]
Merge "rockchip: px30: support px30" into integration
John Tsichritzis [Mon, 1 Jul 2019 13:27:33 +0000 (14:27 +0100)]
Refactor SPSR initialisation code
Change-Id: Ic3b30de13e314efca30fc71370227d3e76f1148b
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
John Tsichritzis [Tue, 23 Jul 2019 10:12:41 +0000 (11:12 +0100)]
SSBS: init SPSR register with default SSBS value
This patch introduces an additional precautionary step to further
enhance protection against variant 4. During the context initialisation
before we enter the various BL stages, the SPSR.SSBS bit is explicitly
set to zero. As such, speculative loads/stores are by default disabled
for all BL stages when they start executing. Subsequently, each BL
stage, can choose to enable speculative loads/stores or keep them
disabled.
This change doesn't affect the initial execution context of BL33 which
is totally platform dependent and, thus, it is intentionally left up to
each platform to initialise.
For Arm platforms, SPSR.SSBS is set to zero for BL33 too. This means
that, for Arm platforms, all BL stages start with speculative
loads/stores disabled.
Change-Id: Ie47d39c391d3f20fc2852fc59dbd336f8cacdd6c
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
Soby Mathew [Wed, 24 Jul 2019 11:02:17 +0000 (11:02 +0000)]
Merge "intel: agilex: Fix build error" into integration
Ambroise Vincent [Tue, 23 Jul 2019 10:10:27 +0000 (11:10 +0100)]
intel: agilex: Fix build error
"result of '1 << 31' requires 33 bits to represent, but 'int' only has
32 bits [-Werror=shift-overflow=]"
This is treated as an error since commit
93c690eba8ca ("Enable
-Wshift-overflow=2 to check for undefined shift behavior")
Change-Id: I141827a6711ab7759bfd6357e4ed9c1176da7c7b
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
Julius Werner [Thu, 30 May 2019 00:01:46 +0000 (17:01 -0700)]
Add helper to parse BL31 parameters (both versions)
BL31 used to take a single bl31_params_t parameter structure with entry
point information in arg0. In commit
726002263 (Add new version of image
loading.) this API was changed to a more flexible linked list approach,
and the old parameter structure was copied into all platforms that still
used the old format. This duplicated code unnecessarily among all these
platforms.
This patch adds a helper function that platforms can optionally link to
outsource the task of interpreting arg0. Many platforms are just
interested in the BL32 and BL33 entry point information anyway. Since
some platforms still need to support the old version 1 parameters, the
helper will support both formats when ERROR_DEPRECATED == 0. This allows
those platforms to drop a bunch of boilerplate code and asynchronously
update their BL2 implementation to the newer format.
Change-Id: I9e6475adb1a7d4bccea666118bd1c54962e9fc38
Signed-off-by: Julius Werner <jwerner@chromium.org>
Julius Werner [Wed, 29 May 2019 04:03:58 +0000 (21:03 -0700)]
Factor out cross-BL API into export headers suitable for 3rd party code
This patch adds a new include/export/ directory meant for inclusion in
third-party code. This is useful for cases where third-party code needs
to interact with TF-A interfaces and data structures (such as a custom
BL2-implementation like coreboot handing off to BL31). Directly
including headers from the TF-A repository avoids having to duplicate
all these definitions (and risk them going stale), but with the current
header structure this is not possible because handoff API definitions
are too deeply intertwined with other TF code/headers and chain-include
other headers that will not be available in the other environment.
The new approach aims to solve this by separating only the parts that
are really needed into these special headers that are self-contained and
will not chain-include other (non-export) headers. TF-A code should
never include them directly but should instead always include the
respective wrapper header, which will include the required prerequisites
(like <stdint.h>) before including the export header. Third-party code
can include the export headers via its own wrappers that make sure the
necessary definitions are available in whatever way that environment can
provide them.
Change-Id: Ifd769320ba51371439a8e5dd5b79c2516c3b43ab
Signed-off-by: Julius Werner <jwerner@chromium.org>
Julius Werner [Wed, 24 Jul 2019 03:00:13 +0000 (20:00 -0700)]
Use explicit-width data types in AAPCS parameter structs
It's not a good idea to use u_register_t for the members of
aapcs64_params_t and aapcs32_params_t, since the width of that type
always depends on the current execution environment. This would cause
problems if e.g. we used this structure to set up the entry point of an
AArch32 program from within an AArch64 program. (It doesn't seem like
any code is doing that today, but it's probably still a good idea to
write this defensively. Also, it helps with my next patch.)
Change-Id: I12c04a85611f2b6702589f3362bea3e6a7c9f776
Signed-off-by: Julius Werner <jwerner@chromium.org>
Julius Werner [Sat, 25 May 2019 03:37:58 +0000 (20:37 -0700)]
plat/rockchip: Switch to use new common BL aux parameter library
This patch changes all Rockchip platforms to use the new common BL aux
parameter helpers. Since the parameter space is now cleanly split in
generic and vendor-specific parameters and the COREBOOT_TABLE
parameter is now generic, the parameter type number for that parameter
has to change. Since it only affects coreboot which always builds TF as
a submodule and includes its headers directly to get these constants,
this should not cause any issues. In general, after this point, we
should avoid changing already assigned parameter type numbers whenever
possible.
Change-Id: Ic99ddd1e91ff5e5fe212fa30c793a0b8394c9dad
Signed-off-by: Julius Werner <jwerner@chromium.org>
Jacky Bai [Thu, 18 Jul 2019 05:43:17 +0000 (13:43 +0800)]
plat: imx8m: Add basic rdc module init driver
Add the basic support for RDC init/config driver,
this module driver can be enhanced more if necessary.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I290dc378d0d85671435f9de46d5aa790b4e006c8
Soby Mathew [Tue, 23 Jul 2019 15:18:58 +0000 (15:18 +0000)]
Merge "n1sdp: fix DMC ECC enablement sequence in N1SDP platform" into integration
Soby Mathew [Tue, 23 Jul 2019 12:37:25 +0000 (12:37 +0000)]
Merge "arm: Shorten the Firmware Update (FWU) process" into integration
Soby Mathew [Tue, 23 Jul 2019 12:34:55 +0000 (12:34 +0000)]
Merge "Fix BL31 crash reporting on AArch64 only machines" into integration
Manoj Kumar [Mon, 22 Jul 2019 15:10:12 +0000 (16:10 +0100)]
n1sdp: fix DMC ECC enablement sequence in N1SDP platform
The DMC-620 memory controllers in N1SDP platform has to be put
into CONFIG state before writing to ERR0CTLR0 register to enable
ECC.
This patch fixes the sequence so that DMCs are set to CONFIG
state before writing to ERR0CTLR0 register and moved back to
READY state after writing.
Change-Id: I1252f3ae0991603bb29234029cddb5fbf869c1b2
Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>
Ambroise Vincent [Thu, 4 Jul 2019 13:58:45 +0000 (14:58 +0100)]
arm: Shorten the Firmware Update (FWU) process
The watchdog is configured with a default value of 256 seconds in order
to implement the Trusted Board Boot Requirements.
For the FVP and Juno platforms, the FWU process relies on a watchdog
reset. In order to automate the test of FWU, the length of this process
needs to be as short as possible. Instead of waiting for those 4 minutes
to have a reset by the watchdog, tell it to reset immediately.
There are no side effects as the value of the watchdog's load register
resets to 0xFFFFFFFF.
Tested on Juno.
Change-Id: Ib1aea80ceddc18ff1e0813a5b98dd141ba8a3ff2
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
Soby Mathew [Tue, 23 Jul 2019 09:33:15 +0000 (09:33 +0000)]
Merge "Cortex_hercules: Introduce preliminary cpu support" into integration
Soby Mathew [Tue, 23 Jul 2019 08:55:10 +0000 (08:55 +0000)]
Merge "Enable MTE support unilaterally for Normal World" into integration
Imre Kis [Tue, 9 Jul 2019 16:30:58 +0000 (18:30 +0200)]
Romlib makefile refactoring and script rewriting
The features of the previously existing gentbl, genvar and genwrappers
scripts were reimplemented in the romlib_generator.py Python script.
This resulted in more readable and maintainable code and the script
introduces additional features that help dependency handling in
makefiles. The assembly templates were separated from the script logic
and were collected in the 'templates' directory.
The targets and their dependencies were reorganized in the makefile and
the dependency handling of included index files is possible now.
Incremental build is available in case of modifying the index files.
Signed-off-by: Imre Kis <imre.kis@arm.com>
Change-Id: I79f65fab9dc5c70d1f6fc8f57b2a3009bf842dc5
Imre Kis [Mon, 22 Jul 2019 09:56:45 +0000 (11:56 +0200)]
Fix BL31 crash reporting on AArch64 only machines
The AArch32 system registers are not listed if the platform supports
AArch64 only.
Change-Id: I087a10ae6e7cad1bb52775a344635dbac1f12679
Signed-off-by: Imre Kis <imre.kis@arm.com>
Soby Mathew [Fri, 19 Jul 2019 09:09:12 +0000 (09:09 +0000)]
Merge "intel: Adds support for Agilex platform" into integration
Soby Mathew [Fri, 19 Jul 2019 08:31:03 +0000 (08:31 +0000)]
Merge "doc: Complete the storage abstraction layer doc" into integration
Julius Werner [Sat, 25 May 2019 03:31:15 +0000 (20:31 -0700)]
Introduce lightweight BL platform parameter library
This patch adds some common helper code to support a lightweight
platform parameter passing framework between BLs that has already been
used on Rockchip platforms but is more widely useful to others as well.
It can be used as an implementation for the SoC firmware configuration
file mentioned in the docs, and is primarily intended for platforms
that only require a handful of values to be passed and want to get by
without a libfdt dependency. Parameters are stored in a linked list and
the parameter space is split in generic and vendor-specific parameter
types. Generic types will be handled by this code whereas
vendor-specific types have to be handled by a vendor-specific handler
function that gets passed in.
Change-Id: If3413d44e86b99d417294ce8d33eb2fc77a6183f
Signed-off-by: Julius Werner <jwerner@chromium.org>
Louis Mayencourt [Mon, 15 Jul 2019 12:56:03 +0000 (13:56 +0100)]
doc: Complete the storage abstraction layer doc
Add uml sequence and class diagram to illustrate the behavior of the
storage abstraction layer.
Change-Id: I338262729f8034cc3d3eea1d0ce19cca973a91bb
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
Hadi Asyrafi [Thu, 27 Jun 2019 03:34:03 +0000 (11:34 +0800)]
intel: Adds support for Agilex platform
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Ib2ad2068abdf0b204c5cb021ea919581adaca4ef
Soby Mathew [Wed, 17 Jul 2019 10:49:26 +0000 (10:49 +0000)]
Merge "backtrace: Strip PAC field when PAUTH is enabled" into integration
Louis Mayencourt [Tue, 9 Jul 2019 10:40:55 +0000 (11:40 +0100)]
backtrace: Strip PAC field when PAUTH is enabled
When pointer authentication is enabled, the LR value saved on the stack
contains a Pointer Authentication Code (PAC). It must be stripped to
retrieve the return address.
The PAC field is stored on the high bits of the address and defined as:
- PAC field = Xn[54:bottom_PAC_bit], when address tagging is used.
- PAC field = Xn[63:56, 54:bottom_PAC_bit], without address tagging.
With bottom_PAC_bit = 64 - TCR_ELx.TnSZ
Change-Id: I21d804e58200dfeca1da4c2554690bed5d191936
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
Soby Mathew [Wed, 17 Jul 2019 09:38:51 +0000 (09:38 +0000)]
Merge "plat/arm: Introduce A5 DesignStart platform." into integration
Soby Mathew [Wed, 17 Jul 2019 08:51:38 +0000 (08:51 +0000)]
Merge "doc: Generate PlantUML diagrams automatically" into integration
Soby Mathew [Wed, 17 Jul 2019 08:51:27 +0000 (08:51 +0000)]
Merge "console: update skeleton" into integration
Soby Mathew [Wed, 17 Jul 2019 08:51:10 +0000 (08:51 +0000)]
Merge changes I68941876,Ib7961812,I758661d3,I4f3e3812,I9b26b838, ... into integration
* changes:
rcar_gen3: drivers: ddr-a: Fix E3 DDR init coding style
rcar_gen3: drivers: ddr-a: Pass ddrBackup around
rcar_gen3: drivers: ddr-a: Inline ddr_init_e3.h
rcar_gen3: drivers: ddr-a: Fix V3M DDR init coding style
rcar_gen3: drivers: ddr-a: Fix D3 DDR init coding style
rcar_gen3: drivers: ddr-a: Replace {Read,Write}Reg_32() with mmio_{read,write}_32()
rcar_gen3: drivers: ddr-a: Unify register definitions
Soby Mathew [Wed, 17 Jul 2019 08:50:58 +0000 (08:50 +0000)]
Merge "rcar_gen3: drivers: ddr: Replace BITn with BIT(n) macro" into integration
Jun Nie [Thu, 13 Jun 2019 03:47:09 +0000 (11:47 +0800)]
plat: imx7: Add PicoPi iMX7D basic support
The PicoPi iMX7D is a 2 board development board consisting of
a System-on-Module and a carrier baseboard and optimized for
the Internet-of-Things (IoT).
This patch add basic support to this board.
Signed-off-by: Jun Nie <jun.nie@linaro.org>
Reviewed-by: Louis Mayencourt <louis.mayencourt@arm.com>
Change-Id: I009d85819c4f73b7063aab73d0f6ee74e6ef3fc4
Jun Nie [Thu, 13 Jun 2019 03:38:24 +0000 (11:38 +0800)]
plat: imx7: refactor code for reuse
For the iMX7 SOCs, part of the code for platform
setup implementation can be reused and made
common for all these SoCs. This patch extracts
the common part for reuse.
Signed-off-by: Jun Nie <jun.nie@linaro.org>
Change-Id: I42fd4167e6903416df96a0159a046abf3896e878
Louis Mayencourt [Tue, 14 May 2019 10:00:45 +0000 (11:00 +0100)]
Cortex_hercules: Introduce preliminary cpu support
Change-Id: Iab767e9937f5c6c8150953fcdc3b37e8ee83fa63
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
Remi Pommarel [Sun, 14 Jul 2019 18:49:12 +0000 (20:49 +0200)]
marvell/a3700: Prevent SError accessing PCIe link while it is down
When the link goes down (e.g. during a retrain), accessing the device
configuration space can trigger an ARM64 SError interrupt. Such
conditions cannot be predicted, so to avoid a crash the SError is
ignored.
Signed-off-by: Remi Pommarel <repk@triplefau.lt>
Change-Id: I2b1fd3296cc1c88b9ca1fe21c0924cb324eed58d
Remi Pommarel [Sun, 14 Jul 2019 18:34:28 +0000 (20:34 +0200)]
marvell: Switch to xlat_tables_v2
Use v2 xlat tables library instead of v1 for marvell platforms.
Signed-off-by: Remi Pommarel <repk@triplefau.lt>
Change-Id: I838a6a878a8353e84eea9529721761b478943f0a
Usama Arif [Tue, 18 Jun 2019 15:46:05 +0000 (16:46 +0100)]
plat/arm: Introduce A5 DesignStart platform.
This patch adds support for Cortex-A5 FVP for the
DesignStart program. DesignStart aims at providing
low cost and fast access to Arm IP.
Currently with this patch only the primary CPU is booted
and the rest of them wait for an interrupt.
Signed-off-by: Usama Arif <usama.arif@arm.com>
Change-Id: I3a2281ce6de2402dda4610a89939ed53aa045fab
Ambroise Vincent [Fri, 31 May 2019 15:21:59 +0000 (16:21 +0100)]
console: update skeleton
Update the skeleton implementation of the console interface.
The 32 bit version was outdated and has been copied from the 64 bit
version.
Change-Id: Ib3e4eb09402ffccb1a30c703a53829a7bf064dfe
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
Soby Mathew [Tue, 16 Jul 2019 10:11:27 +0000 (10:11 +0000)]
Merge changes from topic "jc/shift-overflow" into integration
* changes:
Enable -Wshift-overflow=2 to check for undefined shift behavior
Update base code to not rely on undefined overflow behaviour
Update hisilicon drivers to not rely on undefined overflow behaviour
Update synopsys drivers to not rely on undefined overflow behaviour
Update imx platform to not rely on undefined overflow behaviour
Update mediatek platform to not rely on undefined overflow behaviour
Update layerscape platform to not rely on undefined overflow behaviour
Update intel platform to not rely on undefined overflow behaviour
Update rockchip platform to not rely on undefined overflow behaviour
Update renesas platform to not rely on undefined overflow behaviour
Update meson platform to not rely on undefined overflow behaviour
Update marvell platform to not rely on undefined overflow behaviour
Soby Mathew [Mon, 15 Jul 2019 15:01:11 +0000 (15:01 +0000)]
Merge "synquacer: Fix compilation fail for SPM support build config" into integration
Marek Vasut [Sun, 14 Jul 2019 09:26:03 +0000 (11:26 +0200)]
rcar_gen3: drivers: ddr-a: Fix E3 DDR init coding style
Coding style cleanup, no functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I689418768e87a8c1b6eeeb9f1a48dfb333908017
Marek Vasut [Sun, 14 Jul 2019 10:09:56 +0000 (12:09 +0200)]
rcar_gen3: drivers: ddr-a: Pass ddrBackup around
Pass the ddrBackup variable around instead of making it a global variable.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: Ib796181247712e464b77f5f8be5f851745727d74
---
NOTE: The camelcase is fixed in later patch.
Marek Vasut [Sun, 14 Jul 2019 09:19:18 +0000 (11:19 +0200)]
rcar_gen3: drivers: ddr-a: Inline ddr_init_e3.h
Partly inline ddr_init_e3.h into ddr_init_e3.c . Drop duplicate
INITDRAM_* macros, which are defined in boot_init_dram.h .
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I758661d337a86b6a07f82cd4067fbc149cbaed1e
Marek Vasut [Sun, 14 Jul 2019 09:03:21 +0000 (11:03 +0200)]
rcar_gen3: drivers: ddr-a: Fix V3M DDR init coding style
Coding style cleanup, no functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I4f3e3812ffaa24fec50857756539b563eff33cdd
Marek Vasut [Sun, 14 Jul 2019 07:28:59 +0000 (09:28 +0200)]
rcar_gen3: drivers: ddr-a: Fix D3 DDR init coding style
Coding style cleanup, no functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I9b26b838e8c45d9b4f53c67663ec94002dd9edfe
Marek Vasut [Sun, 14 Jul 2019 07:22:57 +0000 (09:22 +0200)]
rcar_gen3: drivers: ddr-a: Replace {Read,Write}Reg_32() with mmio_{read,write}_32()
Replace ad-hoc register accessors with generic ones, remove the ad-hoc
implementation. No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I21446a00a38c6a39d6a48652c34f59814074e831
Marek Vasut [Sun, 14 Jul 2019 07:10:34 +0000 (09:10 +0200)]
rcar_gen3: drivers: ddr-a: Unify register definitions
Unify boot_init_dram_regdef_*.h into boot_init_dram_regdef.h and
clean up it's coding style a bit.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: Iae3375969c05f80209ebf7b1ebc3633a7f6317ff
Marek Vasut [Sun, 14 Jul 2019 06:55:27 +0000 (08:55 +0200)]
rcar_gen3: drivers: ddr: Replace BITn with BIT(n) macro
Remove the ad-hoc BITn macros and replace them with generic BIT(n) macro.
No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I5d0b44d6cba5a69895fed505f6ff780d3574907f
Madhukar Pappireddy [Mon, 8 Jul 2019 23:05:24 +0000 (18:05 -0500)]
synquacer: Fix compilation fail for SPM support build config
Fix the header file path
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
Change-Id: I73a92a3f0049ecbda7eade452405927c04048e01
Paul Beesley [Fri, 12 Jul 2019 10:56:58 +0000 (11:56 +0100)]
doc: Generate PlantUML diagrams automatically
Currently we have some pre-rendered versions of certain diagrams
in SVG format. These diagrams have corresponding PlantUML source
that can be rendered automatically as part of the documentation
build, removing the need for any intermediate files.
This patch adds the Sphinx "plantuml" extension, replaces
references to the pre-rendered SVG files within the documents,
and finally removes the SVG files and helper script.
New requirements for building the docs are the
"sphinxcontrib-plantuml" Python module (added to the pip
requirements.txt file) and the Graphviz package (provides the
"dot" binary) which is in the Ubuntu package repositories.
Change-Id: I24b52ee40ff79676212ed7cff350294945f1b50d
Signed-off-by: Paul Beesley <paul.beesley@arm.com>
Sandrine Bailleux [Fri, 12 Jul 2019 12:00:08 +0000 (12:00 +0000)]
Merge changes I94acd1bb,I0ece5226,I82d0a213,Ia4fc9456,Ic9fb7ed1 into integration
* changes:
rcar_gen3: plat: Update IPL and Secure Monitor Rev2.0.4
rcar_gen3: drivers: rpc: Modify PFC code
rcar_gen3: drivers: rpc: Change RPC PHY calibration setting
rcar_gen3: drivers: ddr-b: Update DDR setting for H3, M3, M3N
rcar_gen3: drivers: ddr-a: Update E3 DDR setting
Sandrine Bailleux [Fri, 12 Jul 2019 11:26:04 +0000 (11:26 +0000)]
Merge "Re-apply GIT_COMMIT_ID check for checkpatch" into integration
Toshiyuki Ogasahara [Mon, 20 May 2019 02:39:53 +0000 (11:39 +0900)]
rcar_gen3: plat: Update IPL and Secure Monitor Rev2.0.4
Update the revision number in the revision management file.
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I94acd1bb53d9d2453e550e2a13b6391b9088ff8d
Toshiyuki Ogasahara [Mon, 20 May 2019 02:25:41 +0000 (11:25 +0900)]
rcar_gen3: drivers: rpc: Modify PFC code
Modify PFC code and rename macro of MFIS according to Errata of
Hardware User's Manual
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I0ece522647319286350843bbbe8b8ba8b0ae9bac
Toshiyuki Ogasahara [Mon, 20 May 2019 02:23:48 +0000 (11:23 +0900)]
rcar_gen3: drivers: rpc: Change RPC PHY calibration setting
Modify RPC code according to Errata of Hardware User's Manual
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I82d0a2136c7f18870842f84c49343977708eef1e
Chiaki Fujii [Fri, 17 May 2019 01:45:02 +0000 (10:45 +0900)]
rcar_gen3: drivers: ddr-b: Update DDR setting for H3, M3, M3N
[IPL/DDR]
- Update H3, M3, M3N DDR setting rev.0.36.
Signed-off-by: Chiaki Fujii <chiaki.fujii.wj@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: Ia4fc9456876a14a9cf3ced93163477974f6cc8bf