danh-arm [Tue, 29 Aug 2017 10:51:32 +0000 (11:51 +0100)]
Merge pull request #1068 from jenswi-linaro/optee_arm_plat
Optee arm platform common
danh-arm [Tue, 29 Aug 2017 10:49:59 +0000 (11:49 +0100)]
Merge pull request #1056 from geesun/qx/interrupt-diags
update the interrupt diagrams
davidcunado-arm [Fri, 25 Aug 2017 16:26:22 +0000 (17:26 +0100)]
Merge pull request #1064 from islmit01/im/shifted_afinity
FVP: Always assume shifted affinity with MT bit
davidcunado-arm [Fri, 25 Aug 2017 16:25:39 +0000 (17:25 +0100)]
Merge pull request #1059 from kenkuang/intergration
fix a typo abort sctlr_el2
davidcunado-arm [Fri, 25 Aug 2017 12:37:45 +0000 (13:37 +0100)]
Merge pull request #1067 from jeenu-arm/rst-fix
firmware-design.rst: Fix formatting
davidcunado-arm [Fri, 25 Aug 2017 12:37:30 +0000 (13:37 +0100)]
Merge pull request #1061 from robertovargas-arm/norflash
nor-flash
davidcunado-arm [Fri, 25 Aug 2017 10:38:56 +0000 (11:38 +0100)]
Merge pull request #1065 from jenswi-linaro/optee_qemu
qemu: Add OP-TEE extra image parsing support
davidcunado-arm [Fri, 25 Aug 2017 09:52:44 +0000 (10:52 +0100)]
Merge pull request #1058 from alistair23/alistair/master
psci_common: Resolve GCC static analysis false positive
Jens Wiklander [Fri, 25 Aug 2017 08:07:20 +0000 (10:07 +0200)]
FVP: bl2: optionally map ARM_OPTEE_PAGEABLE_LOAD_MEM
If SPD_opteed is defined map ARM_OPTEE_PAGEABLE_LOAD_MEM in bl2 to
allow loading of OP-TEE paged part.
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Jens Wiklander [Thu, 24 Aug 2017 13:39:09 +0000 (15:39 +0200)]
ARM plat: change OP-TEE pageable load base
Changes ARM_OPTEE_PAGEABLE_LOAD_BASE to end of ARM_AP_TZC_DRAM1.
ARM_OPTEE_PAGEABLE_LOAD_SIZE is also increased to 4MB to optimize
translation table usage.
This change makes loading of paged part easier inside OP-TEE OS as the
previous location of ARM_OPTEE_PAGEABLE_LOAD_BASE normally isn't mapped
if paging is enabled.
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Jeenu Viswambharan [Thu, 24 Aug 2017 14:43:44 +0000 (15:43 +0100)]
firmware-design.rst: Fix formatting
The format conversion wrongly formatted a couple of sections. These were
also missing from the Table of Contents.
Change-Id: I324216c27e7b4711e6cc5e25782f4b53842140cc
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
Jens Wiklander [Thu, 24 Aug 2017 11:16:26 +0000 (13:16 +0200)]
qemu: Add OP-TEE extra image parsing support
OP-TEE may have extra images to be loaded. Load them one by one and do
the parsing. In this patch, ARM TF need to load up to 3 images for
OP-TEE: header, pager and pages images. Header image is the info about
optee os and images. Pager image include pager code and data. Paged
image include the paging parts using virtual memory.
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Jens Wiklander [Thu, 24 Aug 2017 11:16:22 +0000 (13:16 +0200)]
opteed: pass device tree pointer in x2
Pass device tree pointer to OP-TEE in x2. bl2 is expected to fill in the
device tree pointer in args.arg3. Passing 0 means that device tree is
unavailable.
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Jens Wiklander [Thu, 24 Aug 2017 11:16:20 +0000 (13:16 +0200)]
qemu: replace deprecated plat_psci_common.c
Change to compile with new plat/common/plat_psci_common.c instead of the old
deprecated plat/common/aarch64/plat_psci_common.c
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Jens Wiklander [Thu, 24 Aug 2017 11:16:16 +0000 (13:16 +0200)]
qemu: replace deprecated ADDR_SPACE_SIZE
Replaces the deprecated ADDR_SPACE_SIZE with PLAT_PHY_ADDR_SPACE_SIZE
and PLAT_VIRT_ADDR_SPACE_SIZE.
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Alistair Francis [Wed, 23 Aug 2017 20:55:21 +0000 (13:55 -0700)]
psci_common: Resolve GCC static analysis false positive
Previously commit
555ebb34db8f3424c1b394df2f10ecf9c1f70901 attmpted to fix this
GCC issue:
services/std_svc/psci/psci_common.c: In function 'psci_do_state_coordination':
services/std_svc/psci/psci_common.c:220:27: error: array subscript is above
array bounds [-Werror=array-bounds]
psci_req_local_pwr_states[pwrlvl - 1][cpu_idx] = req_pwr_state;
This fix doesn't work as asserts aren't built in non-debug build flows.
Let's use GCCs #pragma option (documented here:
https://gcc.gnu.org/onlinedocs/gcc/Diagnostic-Pragmas.html) to avoid
this false positive instead.
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
Isla Mitchell [Thu, 17 Aug 2017 11:25:34 +0000 (12:25 +0100)]
FVP: Always assume shifted affinity with MT bit
At present, the MPIDR validation on FVP relies on MT bit set along
with shifted affinities. This currently is additionally dependent
on the FVP model being of variant C. This however should be based
on the presence of MT bit alone.
This patch makes the change to always assume that the affinities
are shifted in the FVP model when MT bit is present.
Change-Id: I09fcb0126e1b38d29124bdeaf3450a60b95d485d
Signed-off-by: Isla Mitchell <isla.mitchell@arm.com>
davidcunado-arm [Wed, 23 Aug 2017 16:23:15 +0000 (17:23 +0100)]
Merge pull request #1017 from etienne-lms/minor-docs
Minor docs
Etienne Carriere [Wed, 23 Aug 2017 13:44:01 +0000 (15:44 +0200)]
Makefile: correct path for CHECKPATCH warnings
Change-Id: I08c9789d3fd2b034b08de663d151023ca005f77f
Reported-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Etienne Carriere [Wed, 23 Aug 2017 13:43:33 +0000 (15:43 +0200)]
doc: minor typo fix
Change-Id: I00fae047dea0eaf7e60037598af020817c66f659
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Roberto Vargas [Fri, 28 Jul 2017 09:43:28 +0000 (10:43 +0100)]
norflash: Add full status check
The nor_XXXXX functions may fail due to different reasons, and it
is convenient to do a full check to detect any failure. It is also
a good idea to have a specific function to do a full status check,
because new checks can be added to this function and they will be
incorporated automatically to any function calling it.
Change-Id: I54fed913e37ef574c1608e94139a519426348d12
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
Ken Kuang [Wed, 23 Aug 2017 08:03:29 +0000 (16:03 +0800)]
fix a typo about sctlr_el2
which will cause write_sctlr_el2 use all sctlr_el1 value except the EE bit
The code doesn't "Use SCTLR_EL1.EE value to initialise sctlr_el2"
but, read out SCTLR_EL1 and clear EE bit, then set to sctlr_el2
Signed-off-by: Ken Kuang <ken.kuang@spreadtrum.com>
davidcunado-arm [Tue, 22 Aug 2017 17:25:55 +0000 (18:25 +0100)]
Merge pull request #1054 from jwerner-chromium/JW_crash_x30
Fix x30 reporting for unhandled exceptions
davidcunado-arm [Tue, 22 Aug 2017 16:44:11 +0000 (17:44 +0100)]
Merge pull request #1053 from jwerner-chromium/JW_func_align
Add new alignment parameter to func assembler macro
Roberto Vargas [Fri, 28 Jul 2017 09:38:24 +0000 (10:38 +0100)]
norflash: Add nor_erase() to NOR driver
NOR memory only supports setting bits to 1. To clear a bit, set to zero,
the NOR memory needs to be erased.
Change-Id: Ia82eb15a5af9a6d4fc7e5ea2b58e6db87226b351
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
Roberto Vargas [Wed, 26 Jul 2017 14:17:24 +0000 (15:17 +0100)]
norflash: Clear status register before sending commands
The status register bits remain until explicitly cleared, which means
that a command can be incorrectly considered to have generated an error -
for example, after reset the status register contents may be unknown or
if a previous command had failed.
This patch clears the status register before beginning any command to
be sure that the status register only represents information about the
current operation.
Change-Id: I9e98110ee24179937215461c00b6543a3467b350
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
Roberto Vargas [Wed, 26 Jul 2017 13:37:56 +0000 (14:37 +0100)]
norflash: Wait for WSM bit in lock/unlock
lock/unlock operation must wait until WSM bit
is set. Since we do not allow to loop forever then these functions
must return an error if WSM bit isn't enabled after a number of tries.
Change-Id: I21c9e292b514b28786ff4a225128bcd8c1bfa999
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
Roberto Vargas [Wed, 26 Jul 2017 13:15:07 +0000 (14:15 +0100)]
norflash: clean-up norflash.c
- Add comments to all the functions
- Simplify nor_poll_dws
- Simplify nor_word_program
Change-Id: I29c0199d2908a4fceb1ac3430fcfdd699be22bb3
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
Julius Werner [Thu, 27 Jul 2017 21:59:34 +0000 (14:59 -0700)]
Fix x30 reporting for unhandled exceptions
Some error paths that lead to a crash dump will overwrite the value in
the x30 register by calling functions with the no_ret macro, which
resolves to a BL instruction. This is not very useful and not what the
reader would expect, since a crash dump should usually show all
registers in the state they were in when the exception happened. This
patch replaces the offending function calls with a B instruction to
preserve the value in x30.
Change-Id: I2a3636f2943f79bab0cd911f89d070012e697c2a
Signed-off-by: Julius Werner <jwerner@chromium.org>
danh-arm [Thu, 17 Aug 2017 12:54:55 +0000 (13:54 +0100)]
Merge pull request #1051 from Kevin-WangTao/fix_suspend_issue
Hikey960: fix PSCI suspend stuck issue
danh-arm [Thu, 17 Aug 2017 12:54:32 +0000 (13:54 +0100)]
Merge pull request #977 from etienne-lms/sp-min-fiq
bl32: add secure interrupt handling in AArch32 sp_min
Qixiang Xu [Tue, 11 Jul 2017 12:33:12 +0000 (20:33 +0800)]
update the interrupt diagrams
- Redraw the interrupt diagrams with dia tool
- Change TSP_HANDLED_S_EL1_FIQ to TSP_HANDLED_S_EL1_INTR in sec-int-handling.png
- Use the makefile generate the image to avoid unnessary generate
- Add dia source code
Change-Id: I016022ca964720e8497c27c88a3f371459abc284
Signed-off-by: Qixiang Xu <qixiang.xu@arm.com>
Tao Wang [Thu, 3 Aug 2017 09:34:09 +0000 (17:34 +0800)]
Hikey960: fix PSCI suspend stuck issue
Clear the cpuidle flag when resuming from idle. This flag is set
when entering idle, and if it remains set when resuming, it can
prevent the cluster from powering off during the next system
suspend operation. During system suspend, all CPUs are plugged
out except the last CPU, which is suspended. If any of the
cpuidle flags are set at this point, the last CPU will be stuck
in a WFI loop and will not be powered off.
This problem only occurs during system suspend.
Signed-off-by: Tao Wang <kevin.wangtao@linaro.org>
danh-arm [Wed, 16 Aug 2017 16:50:17 +0000 (17:50 +0100)]
Merge pull request #1042 from tekkamanninja/qemu_load_image_v2_upstream
qemu: Add LOAD_IMAGE_V2 support
Fu Wei [Sat, 27 May 2017 13:21:42 +0000 (21:21 +0800)]
qemu: Add LOAD_IMAGE_V2 support
The generic LOAD_IMAGE_V2 framework has been merged and enable for almost
all the arm platform. Because qemu platform doesn't share those common
files with arm, QEMU haven't got this support yet.
This patch add all the necessary code the files for adding LOAD_IMAGE_V2
support on QEMU and enable it as default.
Fixes ARM-software/tf-issues#507
Signed-off-by: Fu Wei <fu.wei@linaro.org>
Julius Werner [Tue, 1 Aug 2017 22:16:36 +0000 (15:16 -0700)]
Add new alignment parameter to func assembler macro
Assembler programmers are used to being able to define functions with a
specific aligment with a pattern like this:
.align X
myfunction:
However, this pattern is subtly broken when instead of a direct label
like 'myfunction:', you use the 'func myfunction' macro that's standard
in Trusted Firmware. Since the func macro declares a new section for the
function, the .align directive written above it actually applies to the
*previous* section in the assembly file, and the function it was
supposed to apply to is linked with default alignment.
An extreme case can be seen in Rockchip's plat_helpers.S which contains
this code:
[...]
endfunc plat_crash_console_putc
.align 16
func platform_cpu_warmboot
[...]
This assembles into the following plat_helpers.o:
Sections:
Idx Name Size [...] Algn
9 .text.plat_crash_console_putc
00010000 [...] 2**16
10 .text.platform_cpu_warmboot
00000080 [...] 2**3
As can be seen, the *previous* function actually got the alignment
constraint, and it is also 64KB big even though it contains only two
instructions, because the .align directive at the end of its section
forces the assembler to insert a giant sled of NOPs. The function we
actually wanted to align has the default constraint. This code only
works at all because the linker just happens to put the two functions
right behind each other when linking the final image, and since the end
of plat_crash_console_putc is aligned the start of platform_cpu_warmboot
will also be. But it still wastes almost 64KB of image space
unnecessarily, and it will break under certain circumstances (e.g. if
the plat_crash_console_putc function becomes unused and its section gets
garbage-collected out).
There's no real way to fix this with the existing func macro. Code like
func myfunc
.align X
happens to do the right thing, but is still not really correct code
(because the function label is inserted before the .align directive, so
the assembler is technically allowed to insert padding at the beginning
of the function which would then get executed as instructions if the
function was called). Therefore, this patch adds a new parameter with a
default value to the func macro that allows overriding its alignment.
Also fix up all existing instances of this dangerous antipattern.
Change-Id: I5696a07e2fde896f21e0e83644c95b7b6ac79a10
Signed-off-by: Julius Werner <jwerner@chromium.org>
danh-arm [Mon, 14 Aug 2017 15:35:12 +0000 (16:35 +0100)]
Merge pull request #1040 from sliai/support-opteed-header
Support opteed header
danh-arm [Mon, 14 Aug 2017 15:03:35 +0000 (16:03 +0100)]
Merge pull request #1049 from sandrine-bailleux-arm/sb/xlat-lib-v2-doc
Add documentation of the xlat tables library V2
danh-arm [Mon, 14 Aug 2017 15:02:53 +0000 (16:02 +0100)]
Merge pull request #1048 from douglas-raillard-arm/dr/fix_bl2u_entrypoint
Fix BL2U entrypoint possible parameter corruption
danh-arm [Mon, 14 Aug 2017 14:32:27 +0000 (15:32 +0100)]
Merge pull request #1046 from jeenu-arm/revc
Support for RevC FVP model
danh-arm [Mon, 14 Aug 2017 14:26:53 +0000 (15:26 +0100)]
Merge pull request #1043 from tekkamanninja/qemu_xlat_tables_v2_upstream
qemu: use translation tables library v2 as default.
Etienne Carriere [Wed, 9 Aug 2017 13:48:53 +0000 (15:48 +0200)]
bl32: add secure interrupt handling in AArch32 sp_min
Add support for a minimal secure interrupt service in sp_min for
the AArch32 implementation. Hard code that only FIQs are handled.
Introduce bolean build directive SP_MIN_WITH_SECURE_FIQ to enable
FIQ handling from SP_MIN.
Configure SCR[FIQ] and SCR[FW] from generic code for both cold and
warm boots to handle FIQ in secure state from monitor.
Since SP_MIN architecture, FIQ are always trapped when system executes
in non secure state. Hence discard relay of the secure/non-secure
state in the FIQ handler.
Change-Id: I1f7d1dc7b21f6f90011b7f3fcd921e455592f5e7
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Edison Ai [Tue, 18 Jul 2017 08:52:26 +0000 (16:52 +0800)]
Support paging function for OPTEE.
ARM TF need transfer information about pageable image load address
and memory limit to OPTEE. OPTEE will relocate the pageable image
to where it's needed.
The legacy OP-TEE images that do not include header information
are not affected.
Change-Id: Id057efbbc894de7c36b2209b391febea4729c455
Signed-off-by: Edison Ai <edison.ai@arm.com>
Summer Qin [Mon, 24 Apr 2017 15:49:28 +0000 (16:49 +0100)]
Add Trusted OS extra image parsing support for ARM standard platforms
Trusted OS may have extra images to be loaded. Load them one by one
and do the parsing. In this patch, ARM TF need to load up to 3 images
for optee os: header, pager and paged images. Header image is the info
about optee os and images. Pager image include pager code and data.
Paged image include the paging parts using virtual memory.
Change-Id: Ia3bcfa6d8a3ed7850deb5729654daca7b00be394
Signed-off-by: Summer Qin <summer.qin@arm.com>
Summer Qin [Thu, 20 Apr 2017 15:28:39 +0000 (16:28 +0100)]
Support Trusted OS firmware extra images in TF tools
Since Trusted OS firmware may have extra images, need to
assign new uuid and image id for them.
The TBBR chain of trust has been extended to add support
for the new images within the existing Trusted OS firmware
content certificate.
Change-Id: I678dac7ba1137e85c5779b05e0c4331134c10e06
Signed-off-by: Summer Qin <summer.qin@arm.com>
Antonio Nino Diaz [Tue, 23 May 2017 10:49:22 +0000 (11:49 +0100)]
Add documentation of the xlat tables library V2
The documentation describes the design of the translation tables
library version 2 used by the ARM Trusted Firmware.
The diagram file has been created with Dia version 0.97.2. This tool
can be obtained from: https://wiki.gnome.org/Apps/Dia/Download
Inkscape has been used to generate the *.png file from the *.dia file
to work around a bug in the generation of *.png files in some versions
of Dia.
Change-Id: Ie67d9998d4ae881b2c060200a318ad3ac2fa5e91
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
davidcunado-arm [Fri, 4 Aug 2017 13:09:27 +0000 (14:09 +0100)]
Merge pull request #1050 from davidcunado-arm/dc/update_changelog
Fix to change.log
David Cunado [Wed, 19 Jul 2017 11:31:11 +0000 (12:31 +0100)]
Fix to change.log
With the migration to .rst from .md, the Issues Resolved and
Known Issues sections for v1.4 were using Header 1 format.
This patch changes to using Header 2 for these sections.
Change-Id: Ic3127d84eb169a65039fd4cc8284c6429302732d
Signed-off-by: David Cunado <david.cunado@arm.com>
davidcunado-arm [Thu, 3 Aug 2017 09:30:04 +0000 (10:30 +0100)]
Merge pull request #1044 from islmit01/im/fix_includes
Fix order of #includes
Douglas Raillard [Wed, 26 Jul 2017 18:23:16 +0000 (19:23 +0100)]
Fix BL2U entrypoint possible parameter corruption
Replace the use of r12 by r10 to save the value of a parameter of
bl2u_entrypoint to pass it to bl2u_early_platform_setup at the end of
the function. r10 is a callee saved register so it will not become
corrupted by C code, whereas r12 is the The Intra-Procedure-call scratch
register potentially used by veneers. See the ARM AAPCS document (ARM
IHI 0042F).
Change-Id: I4f37e54a6b550719edb40bb24cd8f498827e2749
Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>
Jeenu Viswambharan [Tue, 18 Jul 2017 14:42:50 +0000 (15:42 +0100)]
FVP: Support Base FVP RevC
Revision C of the Base FVP has the same memory map as earlier revisions,
but has the following differences:
- Implements CCI550 instead of CCI400,
- Has a single instantiation of SMMUv3,
- CPU MPIDs are shifted left by one level, and has MT bit set in them.
The correct interconnect to program is chosen at run time based on the
FVP revision. Therefore, this patch implements FVP functions for
interconnect programming, rather than depending on ARM generic ones. The
macros used have been renamed to reflect this change.
Additionally, this patch initializes SMMUv3 as part of FVP early
platform setup.
New ARM config flags are introduced for feature queries at run time.
Change-Id: Ic7b7f080953a51fceaf62ce7daa6de0573801f09
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
Jeenu Viswambharan [Fri, 26 May 2017 13:15:40 +0000 (14:15 +0100)]
Add SMMUv3 driver
The driver has only one API: to initialize an SMMUv3 device. This
operates on a device that implements secure state, by invalidating
secure caches and TLBs.
Change-Id: Ief32800419ddf0f1fe38c8f0da8f5ba75c72c826
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
Jeenu Viswambharan [Wed, 19 Jul 2017 16:07:00 +0000 (17:07 +0100)]
CCI: Adapt for specific product at run time
The current build system and driver requires the CCI product to be
specified at build time. The device constraints can be determined at run
time from its ID registers, obviating the need for specifying them
ahead.
This patch adds changes to identify and validate CCI at run time. Some
global variables are renamed to be in line with the rest of the code
base.
The build option ARM_CCI_PRODUCT_ID is now removed, and user guide is
updated.
Change-Id: Ibb765e349d3bc95ff3eb9a64bde1207ab710a93d
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
Jeenu Viswambharan [Wed, 19 Jul 2017 15:06:27 +0000 (16:06 +0100)]
FVP: Remove CCI registers from crash dump
The CCI crash dump macros assumes CCI base at build time. Since this
can't be the case for CCI on FVP, choose not to register dump CCI
registers for FVP.
Change-Id: I7374a037e7fd0a85b138e84b3cf0aa044262da97
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
Jeenu Viswambharan [Wed, 19 Jul 2017 16:27:49 +0000 (17:27 +0100)]
Add Linux DTS for FVP with threaded CPUs
In contrast with the non-multi-threading DTS, this enumerates MPIDR
values shifted by one affinity level to the left. The newly added DTS
reflects CPUs with a single thread in them.
Since both DTS files are the same apart from MPIDR contents, the common
bits have been moved to a separate file that's then included from the
top-level DTS files. The multi-threading version only updates the MPIDR
contents.
Change-Id: Id225cd93574f764171df8962ac76f42fcb6bba4b
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
Jeenu Viswambharan [Tue, 15 Nov 2016 13:53:57 +0000 (13:53 +0000)]
FVP: Add support for multi-threaded CPUs
ARM CPUs with multi-threading implementation has more than one
Processing Element in a single physical CPU. Such an implementation will
reflect the following changes in the MPIDR register:
- The MT bit set;
- Affinity levels pertaining to cluster and CPUs occupy one level
higher than in a single-threaded implementation, and the lowest
affinity level pertains to hardware threads. MPIDR affinity level
fields essentially appear shifted to left than otherwise.
The FVP port henceforth assumes that both properties above to be
concomitant on a given FVP platform.
To accommodate for varied MPIDR formats at run time, this patch
re-implements the FVP platform-specific functions that translates MPIDR
values to a linear indices, along with required validation. The same
treatment is applied for GICv3 MPIDR hashing function as well.
An FVP-specific build option FVP_MAX_PE_PER_CPU is introduced which
specifies the maximum number of threads implemented per CPU. For
backwards compatibility, its value defaults to 1.
Change-Id: I729b00d3e121d16ce9a03de4f9db36dfac580e3f
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
Jeenu Viswambharan [Thu, 20 Jul 2017 15:42:50 +0000 (16:42 +0100)]
FVP: Fix AArch32 stack functions to be ABI-compliant
plat_get_my_stack is called from C, so it can't expect argument
registers to be preserved. Stash registers temporarily onto the stack
instead.
plat_set_my_stack is called during early init, when there exists no
stack. Use any register other than argument registers to stash temporary
values.
Change-Id: I98052e20671d0933201d45ec7a5affccd71ce08c
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
davidcunado-arm [Tue, 1 Aug 2017 11:38:19 +0000 (12:38 +0100)]
Merge pull request #1041 from masahir0y/fiptool
fiptool: remove local directory from the header search path
davidcunado-arm [Tue, 1 Aug 2017 11:36:42 +0000 (12:36 +0100)]
Merge pull request #1021 from vwadekar/psci-early-suspend-handler
lib: psci: early suspend handler for platforms
davidcunado-arm [Tue, 1 Aug 2017 09:54:12 +0000 (10:54 +0100)]
Merge pull request #1038 from Leo-Yan/fix_vbus_det_irq
hikey: Disable VBUS_DET interrupt for PMIC
davidcunado-arm [Tue, 1 Aug 2017 09:44:38 +0000 (10:44 +0100)]
Merge pull request #1045 from sandrine-bailleux-arm/sb/xlat-lib-ctx
Fix sign of variable in xlat_tables_print()
Sandrine Bailleux [Tue, 1 Aug 2017 08:16:38 +0000 (09:16 +0100)]
xlat lib v2: Fix sign of debug loop variable
This patch changes the sign of the loop variable used in
xlat_tables_print(). It needs to be unsigned because it is compared
against another unsigned int.
Change-Id: I2b3cee7990dd75e8ebd2701de3860ead7cad8dc8
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Varun Wadekar [Thu, 6 Jul 2017 00:44:12 +0000 (17:44 -0700)]
Tegra: implement the early suspend handler
This patch implements the early suspend handler for Tegra SoCs. This
handler is empty for now and the actual support for a particular platform
would be added later.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Varun Wadekar [Mon, 10 Jul 2017 23:02:05 +0000 (16:02 -0700)]
lib: psci: early suspend handler for platforms
This patch adds an early suspend handler, that executes with
SMP and data cache enabled. This handler allows platforms to
perform any early actions during the CPU suspend entry sequence.
This handler is optional and platforms can choose to implement it
depending on their needs. The `pwr_domain_suspend` handler still
exists and platforms can keep on using it without any side effects.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
davidcunado-arm [Mon, 31 Jul 2017 13:30:27 +0000 (14:30 +0100)]
Merge pull request #1037 from douglas-raillard-arm/dr/doc_fix_errata_a53
Add doc for some Cortex A53 errata workarounds
davidcunado-arm [Mon, 31 Jul 2017 13:29:54 +0000 (14:29 +0100)]
Merge pull request #1035 from sandrine-bailleux-arm/sb/xlat-lib-ctx
Translation table library v2 improvements
davidcunado-arm [Mon, 31 Jul 2017 13:27:19 +0000 (14:27 +0100)]
Merge pull request #1036 from jeenu-arm/fix-ordering
Fix alphabetic ordering
Isla Mitchell [Fri, 14 Jul 2017 09:46:32 +0000 (10:46 +0100)]
Fix order of #includes
This fix modifies the order of system includes to meet the ARM TF coding
standard whilst retaining header groupings.
Change-Id: Ib91968f8e2cac9e96033d73d3ad9d0a2ae228b13
Signed-off-by: Isla Mitchell <isla.mitchell@arm.com>
Fu Wei [Mon, 31 Jul 2017 10:28:32 +0000 (18:28 +0800)]
qemu: use translation tables library v2 as default.
Almost all the arm platform has switch to translation tables library v2 as
default. Because qemu platform doesn't use arm_common.mk like other arm
platforms, QEMU haven't switched to v2 yet.
This patch adds all the necessary code for adding translation tables
library v2 support on QEMU and use it as default.
Fixes ARM-software/tf-issues#508
Signed-off-by: Fu Wei <fu.wei@linaro.org>
davidcunado-arm [Mon, 31 Jul 2017 07:45:57 +0000 (08:45 +0100)]
Merge pull request #1034 from dp-arm/dp/uart-clock
Fix CSS UART clock value
davidcunado-arm [Mon, 31 Jul 2017 07:45:44 +0000 (08:45 +0100)]
Merge pull request #1033 from davidcunado-arm/dc/psci_flush
Address edge case for stale PSCI CPU data in cache
Masahiro Yamada [Wed, 26 Jul 2017 09:21:59 +0000 (18:21 +0900)]
fiptool: remove unneeded -I. include path
All local headers in tools/fiptool are included by #include "..."
notation instead of #include <...>, so there is no need to add the
local directory to to the header search path.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
davidcunado-arm [Wed, 26 Jul 2017 11:31:41 +0000 (12:31 +0100)]
Merge pull request #1032 from soby-mathew/sm/css_scp_reorg
Reorganise CSS SCP bootloader layer
davidcunado-arm [Wed, 26 Jul 2017 11:31:18 +0000 (12:31 +0100)]
Merge pull request #1031 from robertovargas-arm/assert_format
Use standard UNIX file:line format in assert
David Cunado [Wed, 19 Jul 2017 11:14:07 +0000 (12:14 +0100)]
Address edge case for stale PSCI CPU data in cache
There is a theoretical edge case during CPU_ON where the cache
may contain stale data for the target CPU data - this can occur
under the following conditions:
- the target CPU is in another cluster from the current
- the target CPU was the last CPU to shutdown on its cluster
- the cluster was removed from coherency as part of the CPU shutdown
In this case the cache maintenace that was performed as part of the
target CPUs shutdown was not seen by the current CPU's cluster. And
so the cache may contain stale data for the target CPU.
This patch adds a cache maintenance operation (flush) for the
cache-line containing the target CPU data - this ensures that the
target CPU data is read from main memory.
Change-Id: If8cfd42639b03174f60669429b7f7a757027d0fb
Signed-off-by: David Cunado <david.cunado@arm.com>
Sandrine Bailleux [Thu, 20 Jul 2017 15:11:01 +0000 (16:11 +0100)]
Emphasize that TF only supports 4 KB granule size
At the moment, various parts of the Trusted Firmware code assume
that the granule size used is 4 KB. For example, the linker scripts
enforce 4 KB alignment restrictions on some sections.
However, the ARMv8-A architecture allows 16 KB and 64 KB granule
sizes as well. Some other parts of the TF code, particularly the
architectural code and definitions, have been implemented with
this in mind and cater for all 3 cases.
This discrepancy creates some confusion as to what is effectively
supported in TF. This patch adds some code comments and clarification
in the documentation to make this limitation clearer.
Change-Id: I1f202369b240d8bed9d43d57ecd2a548c86c8598
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Sandrine Bailleux [Wed, 19 Jul 2017 09:11:13 +0000 (10:11 +0100)]
xlat lib: Fix some types
Fix the type length and signedness of some of the constants and
variables used in the translation table library.
This patch supersedes Pull Request #1018:
https://github.com/ARM-software/arm-trusted-firmware/pull/1018
Change-Id: Ibd45faf7a4fb428a0bf71c752551d35800212fb2
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Sandrine Bailleux [Wed, 19 Jul 2017 13:05:47 +0000 (14:05 +0100)]
Import ctzdi2.c from LLVM compiler-rt
When using __builtin_ctzll() in AArch32 code, the compiler may translate
that into a call to the __ctzdi2() function. In this case, the linking
phase fails because TF doesn't provide an implementation for it.
This patch imports the implementation of the __ctzdi2() function from
LLVM's compiler-rt project and hooks it into TF's build system. The
ctzdi2.c file is an unmodified copy from the master branch as of
July 19 2017 (SVN revision: 308480).
Change-Id: I96766a025ba28e1afc6ef6a5c4ef91d85fc8f32b
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Sandrine Bailleux [Tue, 11 Jul 2017 14:11:10 +0000 (15:11 +0100)]
xlat lib v2: Remove hard-coded virtual address space size
Previous patches have made it possible to specify the physical and
virtual address spaces sizes for each translation context. However,
there are still some places in the code where the physical (resp.
virtual) address space size is assumed to be PLAT_PHY_ADDR_SPACE_SIZE
(resp. PLAT_VIRT_ADDR_SPACE_SIZE).
This patch removes them and reads the relevant address space size
from the translation context itself instead. This information is now
passed in argument to the enable_mmu_arch() function, which needs it
to configure the TCR_ELx.T0SZ field (in AArch64) or the TTBCR.T0SZ
field (in AArch32) appropriately.
Change-Id: I20b0e68b03a143e998695d42911d9954328a06aa
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Sandrine Bailleux [Wed, 31 May 2017 12:38:51 +0000 (13:38 +0100)]
xlat lib v2: Refactor the functions enabling the MMU
This patch refactors both the AArch32 and AArch64 versions of the
function enable_mmu_arch().
In both versions, the code now computes the VMSA-related system
registers upfront then program them in one go (rather than interleaving
the 2).
In the AArch64 version, this allows to reduce the amount of code
generated by the C preprocessor and limits it to the actual differences
between EL1 and EL3.
In the AArch32 version, this patch also removes the function
enable_mmu_internal_secure() and moves its code directly inside
enable_mmu_arch(), as it was its only caller.
Change-Id: I35c09b6db4404916cbb2e2fd3fda2ad59f935954
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Sandrine Bailleux [Wed, 31 May 2017 12:31:48 +0000 (13:31 +0100)]
xlat lib v2: Remove init_xlat_tables_arch() function
In both the AArch32 and AArch64 versions, this function used to check
the sanity of the PLAT_PHY_ADDR_SPACE_SIZE in regard to the
architectural maximum value. Instead, export the
xlat_arch_get_max_supported_pa() function and move the debug
assertion in AArch-agnostic code.
The AArch64 used to also precalculate the TCR.PS field value, based
on the size of the physical address space. This is now done directly
by enable_mmu_arch(), which now receives the physical address space size
in argument.
Change-Id: Ie77ea92eb06db586f28784fdb479c6e27dd1acc1
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Sandrine Bailleux [Tue, 18 Jul 2017 12:26:36 +0000 (13:26 +0100)]
xlat lib v2: Expose *_ctx() APIs
In a previous patch, the xlat_ctx_t type has been made public.
This patch now makes the *_ctx() APIs public.
Each API now has a *_ctx() variant. Most of them were already implemented
and this patch just makes them public. However, some of them were missing
so this patch introduces them.
Now that all these APIs are public, there's no good reason for splitting
them accross 2 files (xlat_tables_internal.c and xlat_tables_common.c).
Therefore, this patch moves all code into xlat_tables_internal.c and
removes xlat_tables_common.c. It removes it from the library's makefile
as well.
This last change introduces a compatibility break for platform ports
that specifically include the xlat_tables_common.c file instead of
including the library's Makefile. The UniPhier platform makefile has
been updated to now omit this file from the list of source files.
The prototype of mmap_add_region_ctx() has been slightly changed. The
mmap_region_t passed in argument needs to be constant because it gets
called from map_add(), which receives a constant region. The former
implementation of mmap_add() used to cast the const qualifier away,
which is not a good practice.
Also remove init_xlation_table(), which was a sub-function of
init_xlat_tables(). Now there's just init_xlat_tables() (and
init_xlat_tables_ctx()). Both names were too similar, which was
confusing. Besides, now that all the code is in a single file,
it's no longer needed to have 2 functions for that.
Change-Id: I4ed88c68e44561c3902fbebb89cb197279c5293b
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Leo Yan [Wed, 26 Jul 2017 06:36:01 +0000 (14:36 +0800)]
hikey: Disable VBUS_DET interrupt for PMIC
After disconnect Jumper pin 1-2 in J15 header, the signal VBUS_DET is to
be pulled down to low level. This will assert the interrupt signal in
PMIC and trigger IRQ in GIC; the asserted signal from VBUS_DET is level
triggered and kernel reports the warning for unhooked interrupt handling;
and VBUS_DET stays with low level, this triggers IRQ storm in kernel.
This patch is to disable interrupt for VBUS_DET in PMIC, this can
dismiss the verbose log and IRQ storm after kernel booting.
[ 40.835279] irq 57: nobody cared (try booting with the "irqpoll" option)
[ 40.842075] CPU: 0 PID: 980 Comm: irq/57-hi655x-p Not tainted
4.4.77-568944-g576a0114dec8-dirty #667
[ 40.851303] Hardware name: HiKey Development Board (DT)
[ 40.856580] Call trace:
[ 40.859060] [<
ffffff800808c4cc>] dump_backtrace+0x0/0x1e0
[ 40.864516] [<
ffffff800808c8ac>] show_stack+0x20/0x28
[ 40.869622] [<
ffffff80084b9688>] dump_stack+0xa8/0xe0
[ 40.874729] [<
ffffff800812dd5c>] __report_bad_irq+0x40/0xec
[ 40.880360] [<
ffffff800812e0bc>] note_interrupt+0x1e4/0x2d8
[ 40.885992] [<
ffffff800812b11c>] handle_irq_event_percpu+0xd8/0x268
[ 40.892324] [<
ffffff800812b2f8>] handle_irq_event+0x4c/0x7c
[ 40.897955] [<
ffffff800812ecbc>] handle_level_irq+0xcc/0x178
[ 40.903672] [<
ffffff800812a778>] generic_handle_irq+0x34/0x4c
[ 40.909481] [<
ffffff80085074c8>] pl061_irq_handler+0xa8/0x124
[ 40.915286] [<
ffffff800812a778>] generic_handle_irq+0x34/0x4c
[ 40.921092] [<
ffffff800812a820>] __handle_domain_irq+0x90/0xf8
[ 40.926985] [<
ffffff8008082620>] gic_handle_irq+0x58/0xa8
Signed-off-by: Dmitry Shmidt <dimitrysh@google.com>
Signed-off-by: Leo Yan <leo.yan@linaro.org>
davidcunado-arm [Tue, 25 Jul 2017 20:05:47 +0000 (21:05 +0100)]
Merge pull request #1030 from danh-arm/dh/readme-lic-tweak
Clarify third party license info in readme
Sandrine Bailleux [Mon, 10 Jul 2017 12:37:48 +0000 (13:37 +0100)]
xlat lib v2: Export translation context as an opaque type
At the moment, the translation context type (xlat_ctx_t) is a private
type reserved for the internal usage of the translation table library.
All exported APIs (implemented in xlat_tables_common.c) are wrappers
over the internal implementations that use such a translation context.
These wrappers unconditionally pass the current translation context
representing the memory mappings of the executing BL image. This means
that the caller has no control over which translation context the
library functions act on.
As a first step to make this code more flexible, this patch exports
the 'xlat_ctx_t' type. Note that, although the declaration of this type
is now public, its definition stays private. A macro is introduced to
statically allocate and initialize such a translation context.
The library now internally uses this macro to allocate the default
translation context for the running BL image.
Change-Id: Icece1cde4813fac19452c782b682c758142b1489
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Sandrine Bailleux [Fri, 19 May 2017 08:59:37 +0000 (09:59 +0100)]
xlat lib: Reorganize architectural defs
Move the header files that provide translation tables architectural
definitions from the library v2 source files to the library include
directory. This allows to share these definitions between both
versions (v1 and v2) of the library.
Create a new header file that includes the AArch32 or AArch64
definitions based on the AARCH32 build flag, so that the library user
doesn't have to worry about handling it on their side.
Also repurpose some of the definitions the header files provide to
concentrate on the things that differ between AArch32 and AArch64.
As a result they now contain the following information:
- the first table level that allows block descriptors;
- the architectural limits of the virtual address space;
- the initial lookup level to cover the entire address space.
Additionally, move the XLAT_TABLE_LEVEL_MIN macro from
xlat_tables_defs.h to the AArch32/AArch64 architectural definitions.
This new organisation eliminates duplicated information in the AArch32
and AArch64 versions. It also decouples these architectural files from
any platform-specific information. Previously, they were dependent on
the address space size, which is platform-specific.
Finally, for the v2 of the library, move the compatibility code for
ADDR_SPACE_SIZE into a C file as it is not needed outside of this
file. For v1, this code hasn't been changed and stays in a header
file because it's needed by several files.
Change-Id: If746c684acd80eebf918abd3ab6e8481d004ac68
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Sandrine Bailleux [Fri, 26 May 2017 14:48:10 +0000 (15:48 +0100)]
FVP: Do not map DEVICE2 memory range when TBB is disabled
The DEVICE2 memory range is needed to access the Root of Trust Public
Key registers. This is not needed when Trusted Board Boot is disabled
so it's safer to not map it in this case. This also saves one level-2
page table in each of BL1 and BL2 images.
Also add some comments.
Change-Id: I67456b44f3fd5e145f6510a8499b7fdf720a7273
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Sandrine Bailleux [Fri, 26 May 2017 14:47:08 +0000 (15:47 +0100)]
xlat lib v2: Print some debug statistics
This patch adds some debug prints to display some statistics about page
tables usage. They are printed only if the LOG_LEVEL is at least 50
(i.e. VERBOSE).
Sample output for BL1:
VERBOSE: Translation tables state:
VERBOSE: Max allowed PA: 0xffffffff
VERBOSE: Max allowed VA: 0xffffffff
VERBOSE: Max mapped PA: 0x7fffffff
VERBOSE: Max mapped VA: 0x7fffffff
VERBOSE: Initial lookup level: 1
VERBOSE: Entries @initial lookup level: 4
VERBOSE: Used 4 sub-tables out of 5 (spare: 1)
Change-Id: If38956902e9616cdcd6065ecd140fe21482597ea
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Dimitris Papastamos [Tue, 25 Jul 2017 09:49:26 +0000 (10:49 +0100)]
Fix CSS UART clock value
Fixes ARM-software/tf-issues#479
Change-Id: Iadbde2595ad6a0ac3988d17e614c698986959277
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
Douglas Raillard [Mon, 17 Jul 2017 13:14:52 +0000 (14:14 +0100)]
Add doc for some Cortex A53 errata workarounds
Add documentation for errata 835769 and 843419 workarounds introduced in
commit
a94cc374ab57b80d86974f8771565d65b38403ef
Fixes ARM-software/tf-issues#504
Change-Id: I7f3db53dfc5f3827b32663f483d3302bc9679b19
Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>
Jeenu Viswambharan [Wed, 19 Jul 2017 12:52:12 +0000 (13:52 +0100)]
Fix alphabetic ordering
Commit
d832aee90, which added SPE support, got the alphabetical ordering
wrong for documentation and Makefile addition. This patch fixes that.
Change-Id: I061ecfba4db363902c9d7d577d2ce6c612cb9e1d
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
davidcunado-arm [Thu, 20 Jul 2017 21:01:00 +0000 (22:01 +0100)]
Merge pull request #1029 from islmit01/im/fix_includes
Fix order of includes
Soby Mathew [Tue, 13 Jun 2017 17:00:53 +0000 (18:00 +0100)]
CSS: Prevent SCP_BL2/2U from overwriting BL1 RW data
On ARM CSS platforms, the SCP_BL2/2U image is loaded below
BL1 read-write data. This same memory is used to load BL31
later on. But sufficient checks were not done to ensure that the
SCP_BL2 would not overwrite BL1 rw data. This patch adds the
required CASSERT checks to prevent overwrite into BL1 or BL2
memory by load of SCP_BL2/2U. Also the size of BL31 is increased
and SCP_BL2/2U size is decreased to accomodate it within the
allocated region.
Change-Id: I23b28b5e1589e91150852a06452bd52b273216ee
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
Soby Mathew [Wed, 3 May 2017 11:58:41 +0000 (12:58 +0100)]
CSS: Reorganize the SCP Image transfer functionality
The SCP_BL2 is transferred to SCP during BL2 image load and authenticate
sequence. The Boot-Over-MHU (BOM) protocol is used as transport for this. After
the SCP boots using the transferred image, the AP CPU waits till the `READY`
message is received from SCP. This patch separates the API for transport of
image from the wait for `READY` message and also moves the related files to
the `css/drivers` folder. The previous API `scp_bootloader_transfer` is
renamed to `css_scp_boot_image_xfer` to reflect the css naming convention.
This reorganisation also allows easier switch to a different transport
(eg: Shared Data Structure based transfer) in future
Change-Id: I8a96f9c4616ffde6dbfdf7c18f6f6f8bfa40bbf0
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
Soby Mathew [Tue, 13 Jun 2017 16:59:17 +0000 (17:59 +0100)]
Resize the BL2 size limit for Juno
Recent patches to reduce the memory footprint of BL images have
resulted in saving several pages of memory. This patch reduces
the BL2 size limit by 20KB for Juno when ARM_BOARD_OPTIMISE_MEM=1
so that more free space can be freed up for Trusted OS (BL32). Also
SCP_BL2/SCP_BL2U size is now restricted to 80K.
Change-Id: I1573d7a34e24d15e4abce8a14da40dbb5dc81e37
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
Roberto Vargas [Tue, 18 Jul 2017 15:02:50 +0000 (16:02 +0100)]
Use standard UNIX file:line format in assert
This format is understood by almost all the UNIX tools (vi, emacs, acme, ...),
and it allows these tools to jump directly to the line where the assert
failed.
Change-Id: I648fa93c7cc65f911a17dcad5e1a775ac1ae5ed4
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
Dan Handley [Mon, 17 Jul 2017 14:19:37 +0000 (15:19 +0100)]
Clarify third party license info in readme
Clarify the license information for imported third party code in
the readme.rst file.
Change-Id: I96e26fda687a290a6dffb475aca20b169d85784d
Signed-off-by: Dan Handley <dan.handley@arm.com>
davidcunado-arm [Fri, 14 Jul 2017 15:37:31 +0000 (16:37 +0100)]
Merge pull request #1005 from ldts/v1
Poplar: Initial commit for Poplar E-96Boards
davidcunado-arm [Fri, 14 Jul 2017 15:37:02 +0000 (16:37 +0100)]
Merge pull request #1028 from vchong/bl32_optee_support_v2
hikey: Add BL32 (OP-TEE) support v2
Jorge Ramirez-Ortiz [Wed, 28 Jun 2017 08:11:31 +0000 (10:11 +0200)]
Poplar: Initial commit for Poplar E-96Boards
The board features the Hi3798C V200 with an integrated quad-core
64-bit ARM Cortex A53 processor and high performance Mali T720 GPU,
making it capable of running any commercial set-top solution based on
Linux or Android. Its high performance specification also supports a
premium user experience with up to H.265 HEVC decoding of 4K video at
60 frames per second.
SOC Hisilicon Hi3798CV200
CPU Quad-core ARM Cortex-A53 64 bit
DRAM DDR3/3L/4 SDRAM interface, maximum 32-bit data width 2 GB
USB Two USB 2.0 ports One USB 3.0 ports
CONSOLE USB-micro port for console support
ETHERNET 1 GBe Ethernet
PCIE One PCIe 2.0 interfaces
JTAG 8-Pin JTAG
EXPANSION INTERFACE Linaro 96Boards Low Speed Expansion slot
DIMENSION Standard 160×120 mm 96Boards Enterprice Edition form factor
WIFI 802.11AC 2*2 with Bluetooth
CONNECTORS One connector for Smart Card One connector for TSI
The platform boot sequence is as follows:
l-loader --> arm_trusted_firmware --> u-boot
Repositories:
- https://github.com/Linaro/poplar-l-loader.git
- https://github.com/Linaro/poplar-u-boot.git
U-Boot is also upstream in the project's master branch.
Make sure you are using the correct branch on each one of these
repositories. The definition of "correct" might change over time (at
this moment in time this would be the "latest" branch).
Build Line:
make CROSS_COMPILE=aarch64-linux-gnu- all fip SPD=none DEBUG=1
PLAT=poplar BL33=/path/to/u-boot.bin
Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Signed-off-by: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Alex Elder <elder@linaro.org>
Tested-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Tested-by: Leo Yan <leo.yan@linaro.org>
Tested-by: Alex Elder <elder@linaro.org>