Sandrine Bailleux [Wed, 6 Aug 2014 10:27:23 +0000 (11:27 +0100)]
Miscellaneous documentation fixes
This patch gathers miscellaneous minor fixes to the documentation, and comments
in the source code.
Change-Id: I631e3dda5abafa2d90f464edaee069a1e58b751b
Co-Authored-By: Soby Mathew <soby.mathew@arm.com>
Co-Authored-By: Dan Handley <dan.handley@arm.com>
danh-arm [Wed, 27 Aug 2014 17:27:19 +0000 (18:27 +0100)]
Merge pull request #202 from achingupta/ag/fw-design-juno-update
Add information about Juno in firmware-design.md
Juan Castillo [Tue, 26 Aug 2014 16:28:03 +0000 (17:28 +0100)]
Add information about Juno in firmware-design.md
This patch reorganizes the firmware design guide to add information about the
port of the ARM Trusted Firmware to the Juno ARM development platform.
Change-Id: I0b80e2e7a35ccad1af2e971506cfb7fe505f8b84
danh-arm [Wed, 27 Aug 2014 16:26:30 +0000 (17:26 +0100)]
Merge pull request #200 from danh-arm/dh/fix-reset-to-bl31-part2
Fix reset to BL3-1 instructions in user guide, part 2
danh-arm [Wed, 27 Aug 2014 16:25:50 +0000 (17:25 +0100)]
Merge pull request #201 from danh-arm/jc/juno-user-guide
Add Juno instructions to user guide
Juan Castillo [Tue, 19 Aug 2014 09:53:33 +0000 (10:53 +0100)]
Add Juno instructions to user guide
This patch makes the Trusted Firmware build instructions in the
user guide platform independent.
FVP specific instructions have been grouped together under a new
section dedicated to FVP.
Juno specific instructions to build and run the Trusted Firmware,
UEFI and Linux have been added.
Change-Id: I9bfb1b9d732b1f73abbe29f68ac931e1773a4fd5
Dan Handley [Tue, 26 Aug 2014 15:02:19 +0000 (16:02 +0100)]
Fix reset to BL3-1 instructions in user guide, part 2
Fix the instructions for resetting to the BL3-1 entrypoint in the
user guide. The BL3-1 and BL3-2 image locations changed in the fix
to ARM-software/tf-issues#100 (commit
186c1d4). This is distinct
from the similar issue fixed in commit
bfb1dd5.
Also clarify the dependence on the FVP_SHARED_DATA_LOCATION and
FVP_TSP_RAM_LOCATION build options, and tidy up the "Notes
regarding Base FVP configuration options" section.
Change-Id: I6b03452a71f0c69efa169852712bcb184242696e
danh-arm [Thu, 21 Aug 2014 17:30:31 +0000 (18:30 +0100)]
Merge pull request #198 from danh-arm/dh/move-up-dependencies
Move up dependency versions in user guide
danh-arm [Thu, 21 Aug 2014 15:44:40 +0000 (16:44 +0100)]
Merge pull request #197 from soby-mathew/rationalize_uarts
Rationalize UART usage among different BL stages
Soby Mathew [Thu, 21 Aug 2014 14:20:27 +0000 (15:20 +0100)]
Rationalize UART usage among different BL stages
This patch changes the UART port assignment for various BL stages
so as to make it consistent on the platform ports. The BL1, BL2 and
BL3-1 now uses UART0 on the FVP port and SoC UART0 on the Juno port.
The BL3-2 uses UART2 on the FVP port and FPGA UART0 on the Juno
port.
This provides an interim fix to ARM-software/tf-issues#220 until
support is added for changing the UART port for a BL image between
cold boot and runtime.
Change-Id: Iae5faea90be3d59e41e597b34a902f93e737505a
Dan Handley [Thu, 14 Aug 2014 08:14:52 +0000 (09:14 +0100)]
Move up dependency versions in user guide
Move up the version numbers of the following Trusted Firmware
dependencies in the user guide:
* Foundation and Base FVPs (latest publically available
versions).
* EDK2 implementation. The guide now uses the latest version from
https://github.com/ARM-software/edk2.git. This requires the
`iasl` package to also be installed.
* Linux kernel. The guide now uses the latest version from
https://github.com/ARM-software/linux.git.
* Linaro OpenEmbedded file system.
* ARM Development Studio 5.
Change-Id: I95bb863a61e47b9ef8be3d110f7087375ee78add
danh-arm [Thu, 21 Aug 2014 14:15:49 +0000 (15:15 +0100)]
Merge pull request #196 from soby-mathew/sm/tf_juno_support
Add support for Juno in Trusted Firmware
Juan Castillo [Tue, 12 Aug 2014 16:24:30 +0000 (17:24 +0100)]
Juno: Read primary CPU MPID from SCC GPR_1
This patch removes the PRIMARY_CPU definition hardcoded in the
Juno port. Instead, the primary CPU is obtained at runtime by
reading the SCC General Purpose Register 1 (GPR_1), whose value
is copied by the SCP into shared memory during the boot process.
Change-Id: I3981daa92eb7142250712274cf7f655b219837f5
Juan Castillo [Tue, 12 Aug 2014 07:42:28 +0000 (08:42 +0100)]
Juno: Implement PSCI SYSTEM_OFF and SYSTEM_RESET APIs
This patch adds the Juno platform specific handlers for PSCI
SYSTEM_OFF and SYSTEM_RESET operations.
Change-Id: Ie389adead533ec2314af44d721b4d0f306147c7d
Sandrine Bailleux [Thu, 17 Jul 2014 08:56:29 +0000 (09:56 +0100)]
Juno: Add support for Test Secure-EL1 Payload
This patch implements the TSP on Juno. It executes from on-chip Trusted
SRAM.
Also, the other bootloader images (i.e. BL1 R/W, BL2 and BL3-1) have
been moved around. The reason is, although there was enough space
overall to store the TSP in SRAM, there was no contiguous free chunk
of SRAM big enough to hold it.
This patch keeps the overall memory layout (i.e. keeping BL1 R/W at
the bottom, BL2 at the top and BL3-1 in between) but moves the base
addresses of all the bootloader images in such a way that:
- memory fragmentation is reduced enough to fit BL3-2 in;
- new base addresses are suitable for release builds as well as debug
ones;
- each image has a few extra kilobytes for future growth.
BL3-1 and BL3-2 are the images which received the biggest allocations
since they will most probably grow the most.
This patch also adds instruction synchronization barriers around the code which
handles the timer interrupt in the TSP. This ensures that the interrupt is not
acknowledged after or EOIed before it is deactivated at the peripheral.
Change-Id: I1c5b51858700027ee283ac85d18e06863a27c72e
Achin Gupta [Mon, 18 Aug 2014 13:40:27 +0000 (14:40 +0100)]
Juno: Implement PSCI CPU_OFF and CPU_SUSPEND APIs
This patch adds support for PSCI CPU_OFF and CPU_SUSPEND APIs to the Juno port
of the ARM Trusted Firmware. The maximum affinity level that can be suspended is
the cluster level (affinity level 1). Support for suspending the system level is
not present.
Change-Id: Ie2c9da0acd7d1b0d5ac64940cdf40347153e52c8
Sandrine Bailleux [Thu, 17 Jul 2014 15:06:39 +0000 (16:06 +0100)]
Juno: Implement initial platform port
This patch adds the initial port of the ARM Trusted Firmware on the Juno
development platform. This port does not support a BL3-2 image or any PSCI APIs
apart from PSCI_VERSION and PSCI_CPU_ON. It enables workarounds for selected
Cortex-A57 (#806969 & #813420) errata and implements the workaround for a Juno
platform errata (Defect id 831273).
Change-Id: Ib3d92df3af53820cfbb2977582ed0d7abf6ef893
danh-arm [Wed, 20 Aug 2014 19:15:16 +0000 (20:15 +0100)]
Merge pull request #195 from achingupta/ag/fvp_dt_updates
FVP: Update device trees to match cpuidle driver
danh-arm [Wed, 20 Aug 2014 19:14:59 +0000 (20:14 +0100)]
Merge pull request #194 from danh-arm/sm/tf-issues#98
Implement the CPU Specific operations framework v3
Achin Gupta [Wed, 20 Aug 2014 16:33:09 +0000 (17:33 +0100)]
FVP: Update device trees to match cpuidle driver
This patch updates the representation of idle tables and cpu/cluster topology in
the device tree source files for the FVP to what the latest cpuidle driver in
Linux expects. The device tree binaries have also been updated.
Change-Id: If0668b96234f65aa0435fba52f288c9378bd8824
Soby Mathew [Mon, 18 Aug 2014 15:57:56 +0000 (16:57 +0100)]
Add documentation for CPU specific abstraction and Errata workarounds
This patch adds documentation for CPU specific abstraction in the firmware-
design.md and adds a new document cpu-errata-workarounds.md to describe
the cpu errata workaround build flags.
Change-Id: Ia08c2fec0b868a0a107d0264e87a60182797a1bd
Soby Mathew [Thu, 14 Aug 2014 15:19:29 +0000 (16:19 +0100)]
Add support for selected Cortex-A57 errata workarounds
This patch adds workarounds for selected errata which affect the Cortex-A57 r0p0
part. Each workaround has a build time flag which should be used by the platform
port to enable or disable the corresponding workaround. The workarounds are
disabled by default. An assertion is raised if the platform enables a workaround
which does not match the CPU revision at runtime.
Change-Id: I9ae96b01c6ff733d04dc733bd4e67dbf77b29fb0
Soby Mathew [Thu, 14 Aug 2014 12:36:41 +0000 (13:36 +0100)]
Add CPU specific crash reporting handlers
This patch adds handlers for dumping Cortex-A57 and Cortex-A53 specific register
state to the CPU specific operations framework. The contents of CPUECTLR_EL1 are
dumped currently.
Change-Id: I63d3dbfc4ac52fef5e25a8cf6b937c6f0975c8ab
Soby Mathew [Thu, 14 Aug 2014 11:49:05 +0000 (12:49 +0100)]
Add CPU specific power management operations
This patch adds CPU core and cluster power down sequences to the CPU specific
operations framework introduced in a earlier patch. Cortex-A53, Cortex-A57 and
generic AEM sequences have been added. The latter is suitable for the
Foundation and Base AEM FVPs. A pointer to each CPU's operations structure is
saved in the per-cpu data so that it can be easily accessed during power down
seqeunces.
An optional platform API has been introduced to allow a platform to disable the
Accelerator Coherency Port (ACP) during a cluster power down sequence. The weak
definition of this function (plat_disable_acp()) does not take any action. It
should be overriden with a strong definition if the ACP is present on a
platform.
Change-Id: I8d09bd40d2f528a28d2d3f19b77101178778685d
Soby Mathew [Thu, 14 Aug 2014 11:22:32 +0000 (12:22 +0100)]
Add platform API for reset handling
This patch adds an optional platform API (plat_reset_handler) which allows the
platform to perform any actions immediately after a cold or warm reset
e.g. implement errata workarounds. The function is called with MMU and caches
turned off. This API is weakly defined and does nothing by default but can be
overriden by a platform with a strong definition.
Change-Id: Ib0acdccbd24bc756528a8bd647df21e8d59707ff
Soby Mathew [Thu, 14 Aug 2014 10:33:56 +0000 (11:33 +0100)]
Introduce framework for CPU specific operations
This patch introduces a framework which will allow CPUs to perform
implementation defined actions after a CPU reset, during a CPU or cluster power
down, and when a crash occurs. CPU specific reset handlers have been implemented
in this patch. Other handlers will be implemented in subsequent patches.
Also moved cpu_helpers.S to the new directory lib/cpus/aarch64/.
Change-Id: I1ca1bade4d101d11a898fb30fea2669f9b37b956
Soby Mathew [Tue, 19 Aug 2014 10:26:00 +0000 (11:26 +0100)]
Rework use of labels in assembly macros.
This patch provides a workaround for the ASM_ASSERT label issue
and also reworks the use of labels in assembly macros.
If the caller of the ASM_ASSERT macro happened to use the
label '1' to jump past the ASM_ASSERT macro, it would not have
worked since the ASM_ASSERT macro internally used the same label.
Hence, as a workaround, this patch makes the label a high
number in the expectation that the caller will never use it.
Also updated the other assembly macros using numerical labels to
named lables.
Change-Id: Iec892359db84f2391ad2a83a92141c4d7049776a
Achin Gupta [Sun, 27 Jul 2014 23:15:23 +0000 (00:15 +0100)]
Miscellaneous PSCI code cleanups
This patch implements the following cleanups in PSCI generic code:
1. It reworks the affinity level specific handlers in the PSCI implementation
such that.
a. Usage of the 'rc' local variable is restricted to only where it is
absolutely needed
b. 'plat_state' local variable is defined only when a direct invocation of
plat_get_phys_state() does not suffice.
c. If a platform handler is not registered then the level specific handler
returns early.
2. It limits the use of the mpidr_aff_map_nodes_t typedef to declaration of
arrays of the type instead of using it in function prototypes as well.
3. It removes dangling declarations of __psci_cpu_off() and
__psci_cpu_suspend(). The definitions of these functions were removed in
earlier patches.
Change-Id: I51e851967c148be9c2eeda3a3c41878f7b4d6978
Achin Gupta [Thu, 31 Jul 2014 16:45:51 +0000 (17:45 +0100)]
fvp: Rework when platform actions are performed
This patch reworks FVP port's power management implementation to perform
platform actions only when the platform exported hook is invoked for the highest
affinity level to enter/exit the OFF state.
For example, during a CPU_OFF operation, fvp_affinst_off() is called twice: for
affinity level 0 and affinity level 1 (in that order). CPU specific operations
are deferred until the next invocation if it is determined through a call to
psci_get_max_phys_off_afflvl() that this is CPU is the last in the cluster.
Similarly, during power up if the CPU is the first in the cluster, both CPU and
cluster specific operations are performed when fvp_affinst_on_finish() is
invoked for affinity level 1. Earlier, they were done across the two invocations
of the handler.
Change-Id: I4288ed3ba1385db36a69cc2e598deb219f209b8a
Achin Gupta [Thu, 31 Jul 2014 10:19:11 +0000 (11:19 +0100)]
Add APIs to preserve highest affinity level in OFF state
This patch adds APIs to find, save and retrieve the highest affinity level which
will enter or exit from the physical OFF state during a PSCI power management
operation. The level is stored in per-cpu data.
It then reworks the PSCI implementation to perform cache maintenance only
when the handler for the highest affinity level to enter/exit the OFF state is
called.
For example. during a CPU_SUSPEND operation, state management is done prior to
calling the affinity level specific handlers. The highest affinity level which
will be turned off is determined using the psci_find_max_phys_off_afflvl()
API. This level is saved using the psci_set_max_phys_off_afflvl() API. In the
code that does generic handling for each level, prior to performing cache
maintenance it is first determined if the current affinity level matches the
value returned by psci_get_max_phys_off_afflvl(). Cache maintenance is done if
the values match.
This change allows the last CPU in a cluster to perform cache maintenance
independently. Earlier, cache maintenance was started in the level 0 handler and
finished in the level 1 handler. This change in approach will facilitate
implementation of tf-issues#98.
Change-Id: I57233f0a27b3ddd6ddca6deb6a88b234525b0ae6
Achin Gupta [Sun, 27 Jul 2014 23:09:01 +0000 (00:09 +0100)]
Rework state management in the PSCI implementation
This patch pulls out state management from the affinity level specific handlers
into the top level functions specific to the operation
i.e. psci_afflvl_suspend(), psci_afflvl_on() etc.
In the power down path this patch will allow an affinity instance at level X to
determine the state that an affinity instance at level X+1 will enter before the
level specific handlers are called. This will be useful to determine whether a
CPU is the last in the cluster during a suspend/off request and so on.
Similarly, in the power up path this patch will allow an affinity instance at
level X to determine the state that an affinity instance at level X+1 has
emerged from, even after the level specific handlers have been called. This will
be useful in determining whether a CPU is the first in the cluster during a
on/resume request and so on.
As before, while powering down, state is updated before the level specific
handlers are invoked so that they can perform actions based upon their target
state. While powering up, state is updated after the level specific handlers have
been invoked so that they can perform actions based upon the state they emerged
from.
Change-Id: I40fe64cb61bb096c66f88f6d493a1931243cfd37
Achin Gupta [Fri, 25 Jul 2014 13:52:47 +0000 (14:52 +0100)]
Add PSCI service specific per-CPU data
This patch adds a structure defined by the PSCI service to the per-CPU data
array. The structure is used to save the 'power_state' parameter specified
during a 'cpu_suspend' call on the current CPU. This parameter was being saved
in the cpu node in the PSCI topology tree earlier.
The existing API to return the state id specified during a PSCI CPU_SUSPEND call
i.e. psci_get_suspend_stateid(mpidr) has been renamed to
psci_get_suspend_stateid_by_mpidr(mpidr). The new psci_get_suspend_stateid() API
returns the state id of the current cpu.
The psci_get_suspend_afflvl() API has been changed to return the target affinity
level of the current CPU. This was specified using the 'mpidr' parameter in the
old implementation.
The behaviour of the get_power_on_target_afflvl() has been tweaked such that
traversal of the PSCI topology tree to locate the affinity instance node for the
current CPU is done only in the debug build as it is an expensive operation.
Change-Id: Iaad49db75abda471f6a82d697ee6e0df554c4caf
Achin Gupta [Fri, 25 Jul 2014 13:47:05 +0000 (14:47 +0100)]
Add macro to flush per-CPU data
This patch adds a macro which will flush the contents of the specified member of
the per-CPU data structure to the PoC. This is required to enable an update of a
per-CPU data member to be visible to all observers.
Change-Id: I20e0feb9b9f345dc5a1162e88adc7956a7ad7a64
danh-arm [Tue, 19 Aug 2014 10:48:38 +0000 (11:48 +0100)]
Merge pull request #191 from danh-arm/jc/tf-issues/218
Add support for PSCI SYSTEM_OFF and SYSTEM_RESET APIs v2
Juan Castillo [Tue, 12 Aug 2014 10:17:06 +0000 (11:17 +0100)]
Add support for PSCI SYSTEM_OFF and SYSTEM_RESET APIs
This patch adds support for SYSTEM_OFF and SYSTEM_RESET PSCI
operations. A platform should export handlers to complete the
requested operation. The FVP port exports fvp_system_off() and
fvp_system_reset() as an example.
If the SPD provides a power management hook for system off and
system reset, then the SPD is notified about the corresponding
operation so it can do some bookkeeping. The TSPD exports
tspd_system_off() and tspd_system_reset() for that purpose.
Versatile Express shutdown and reset methods have been removed
from the FDT as new PSCI sys_poweroff and sys_reset services
have been added. For those kernels that do not support yet these
PSCI services (i.e. GICv3 kernel), the original dtsi files have
been renamed to *-no_psci.dtsi.
Fixes ARM-software/tf-issues#218
Change-Id: Ic8a3bf801db979099ab7029162af041c4e8330c8
Dan Handley [Tue, 19 Aug 2014 10:04:21 +0000 (11:04 +0100)]
Merge pull request #189 from achingupta/ag/tf-issues#153
Unmask SError interrupt and clear SCR_EL3.EA bit
Dan Handley [Tue, 19 Aug 2014 10:03:01 +0000 (11:03 +0100)]
Merge pull request #181 from danh-arm/dh/tsp_fvp_dependency
Move TSP private declarations into separate header
Clarify platform porting interface to TSP
Dan Handley [Mon, 4 Aug 2014 10:41:20 +0000 (11:41 +0100)]
Clarify platform porting interface to TSP
* Move TSP platform porting functions to new file:
include/bl32/tsp/platform_tsp.h.
* Create new TSP_IRQ_SEC_PHY_TIMER definition for use by the generic
TSP interrupt handling code, instead of depending on the FVP
specific definition IRQ_SEC_PHY_TIMER.
* Rename TSP platform porting functions from bl32_* to tsp_*, and
definitions from BL32_* to TSP_*.
* Update generic TSP code to use new platform porting function names
and definitions.
* Update FVP port accordingly and move all TSP source files to:
plat/fvp/tsp/.
* Update porting guide with above changes.
Note: THIS CHANGE REQUIRES ALL PLATFORM PORTS OF THE TSP TO
BE UPDATED
Fixes ARM-software/tf-issues#167
Change-Id: Ic0ff8caf72aebb378d378193d2f017599fc6b78f
Achin Gupta [Mon, 4 Aug 2014 22:13:10 +0000 (23:13 +0100)]
Unmask SError interrupt and clear SCR_EL3.EA bit
This patch disables routing of external aborts from lower exception levels to
EL3 and ensures that a SError interrupt generated as a result of execution in
EL3 is taken locally instead of a lower exception level.
The SError interrupt is enabled in the TSP code only when the operation has not
been directly initiated by the normal world. This is to prevent the possibility
of an asynchronous external abort which originated in normal world from being
taken when execution is in S-EL1.
Fixes ARM-software/tf-issues#153
Change-Id: I157b996c75996d12fd86d27e98bc73dd8bce6cd5
Dan Handley [Fri, 1 Aug 2014 16:58:27 +0000 (17:58 +0100)]
Move TSP private declarations into separate header
Move the TSP private declarations out of tsp.h and into a new
header, tsp_private.h. This clarifies the TSP interface to the TSPD.
Change-Id: I39af346eeba3350cadcac56c02d97a5cb978c28b
danh-arm [Thu, 14 Aug 2014 10:22:47 +0000 (11:22 +0100)]
Merge pull request #187 from danh-arm/dh/refactor-drivers
Refactor platform porting interface to drivers v2
Dan Handley [Mon, 4 Aug 2014 18:53:05 +0000 (19:53 +0100)]
Simplify interface to TZC-400 driver
The TZC-400 driver previously allowed the possibility of multiple
controller instances to be present in the same executable. This
was unnecessary since there will only ever be one instance.
This change simplifies the tzc_init() function to only take the
base address argument needed by implementation, conforming to the
driver initialization model of other drivers. It also hides some
of the implementation details that were previously exposed by the
API.
The FVP port has been updated accordingly.
THIS CHANGE REQUIRES ALL PLATFORM PORTS THAT USE THE TZC-400
DRIVER TO BE UPDATED
Fixes ARM-software/tf-issues#181
Change-Id: I7b721edf947064989958d8f457d6462d92e742c8
Dan Handley [Tue, 12 Aug 2014 13:20:28 +0000 (14:20 +0100)]
Move IO storage source to drivers directory
Move the remaining IO storage source file (io_storage.c) from the
lib to the drivers directory. This requires that platform ports
explicitly add this file to the list of source files.
Also move the IO header files to a new sub-directory, include/io.
Change-Id: I862b1252a796b3bcac0d93e50b11e7fb2ded93d6
Dan Handley [Mon, 4 Aug 2014 17:31:43 +0000 (18:31 +0100)]
Remove redundant io_init() function
The intent of io_init() was to allow platform ports to provide
a data object (io_plat_data_t) to the IO storage framework to
allocate into. The abstraction was incomplete because io_plat_data_t
uses a platform defined constant and the IO storage framework
internally allocates other arrays using platform defined constants.
This change simplifies the implementation by instantiating the
supporting objects in the IO storage framework itself. There is now
no need for the platform to call io_init().
The FVP port has been updated accordingly.
THIS CHANGE REQUIRES ALL PLATFORM PORTS THAT USE THE IO STORAGE
FRAMEWORK TO BE UDPATED.
Change-Id: Ib48ac334de9e538064734334c773f8b43df3a7dc
Dan Handley [Mon, 4 Aug 2014 15:11:15 +0000 (16:11 +0100)]
Remove platform dependency in CCI-400 driver
* Create cci_init() function in CCI-400 driver to allow platform
to provide arguments needed by the driver (i.e. base address
and cluster indices for the ACE slave interfaces).
* Rename cci_(en|dis)able_coherency to
cci_(en|dis)able_cluster_coherency to make it clear that
the driver only enables/disables the coherency of CPU
clusters and not other devices connected to the CCI-400.
* Update FVP port to use new cci_init() function and remove
unnecessary CCI defintions from platform_def.h. Also rename
fvp_cci_setup() to fvp_cci_enable() to more clearly
differentiate between CCI initialization and enabling.
THIS CHANGE REQUIRES PLATFORM PORTS THAT USE THE CCI-400 DRIVER
TO BE UPDATED
Fixes ARM-software/tf-issues#168
Change-Id: I1946a51409b91217b92285b6375082619f607fec
danh-arm [Thu, 14 Aug 2014 08:52:22 +0000 (09:52 +0100)]
Merge pull request #184 from jcastillo-arm/jc/tf-issues/100
FVP: make usage of Trusted DRAM optional at build time
danh-arm [Thu, 14 Aug 2014 08:50:45 +0000 (09:50 +0100)]
Merge pull request #186 from danh-arm/dh/fix-reset-to-bl31
Fix reset to BL3-1 instructions in user guide
Juan Castillo [Tue, 12 Aug 2014 12:51:51 +0000 (13:51 +0100)]
FVP: make usage of Trusted DRAM optional at build time
This patch groups the current contents of the Trusted DRAM region at
address 0x00_0600_0000 (entrypoint mailboxes and BL3-1 parameters) in
a single shared memory area that may be allocated to Trusted SRAM
(default) or Trusted DRAM at build time by setting the
FVP_SHARED_DATA_LOCATION make variable. The size of this shared
memory is 4096 bytes.
The combination 'Shared data in Trusted SRAM + TSP in Trusted DRAM'
is not currently supported due to restrictions in the maximum number
of mmu tables that can be created.
Documentation has been updated to reflect these changes.
Fixes ARM-software/tf-issues#100
Change-Id: I26ff04d33ce4cacf8d770d1a1e24132b4fc53ff0
Dan Handley [Wed, 13 Aug 2014 11:06:42 +0000 (12:06 +0100)]
Fix reset to BL3-1 instructions in user guide
Fix the instructions for resetting to the BL3-1 entrypoint in the
user guide. The BL3-1 and BL3-2 image locations changed in the fix
to ARM-software/tf-issues#117 (commit
a1b6db6).
Fixes ARM-software/tf-issues#237
Change-Id: I764eb17c66034511efb984c0e7cfda29bd99198f
danh-arm [Tue, 12 Aug 2014 15:57:46 +0000 (16:57 +0100)]
Merge pull request #183 from danh-arm/dh/print_output2
Add concept of console output log levels
Rationalize console log output
Dan Handley [Tue, 29 Jul 2014 16:14:00 +0000 (17:14 +0100)]
Rationalize console log output
Fix the following issues with the console log output:
* Make sure the welcome string is the first thing in the log output
(during normal boot).
* Prefix each message with the BL image name so it's clear which
BL the output is coming from.
* Ensure all output is wrapped in one of the log output macros so it can
be easily compiled out if necessary. Change some of the INFO() messages
to VERBOSE(), especially in the TSP.
* Create some extra NOTICE() and INFO() messages during cold boot.
* Remove all usage of \r in log output.
Fixes ARM-software/tf-issues#231
Change-Id: Ib24f7acb36ce64bbba549f204b9cde2dbb46c8a3
Dan Handley [Fri, 8 Aug 2014 13:36:42 +0000 (14:36 +0100)]
Add concept of console output log levels
Create new LOG_LEVEL build option, which controls the amount of
console output compiled into the build. This should be one of the
following:
0 (LOG_LEVEL_NONE)
10 (LOG_LEVEL_NOTICE)
20 (LOG_LEVEL_ERROR)
30 (LOG_LEVEL_WARNING)
40 (LOG_LEVEL_INFO)
50 (LOG_LEVEL_VERBOSE)
All log output up to and including the log level is compiled into the
build. The default value is 40 in debug builds and 20 in release
builds.
Complement the existing INFO, WARN and ERROR console output macros
with NOTICE and VERBOSE macros, which are conditionally compiled in
depending on the value of LOG_LEVEL.
Fixes ARM-software/tf-issues#232
Change-Id: I951e2f333e7b90fc4b1060741d9a6db699d5aa72
danh-arm [Tue, 12 Aug 2014 15:38:11 +0000 (16:38 +0100)]
Merge pull request #182 from soby-mathew/sm/stack_optimize
Reduce runtime stack size and add compilation macro for each BL stage
danh-arm [Tue, 12 Aug 2014 15:37:05 +0000 (16:37 +0100)]
Merge pull request #180 from jcastillo-arm/jc/tf-issues/207
Move up to Linaro 14.07 toolchain
Juan Castillo [Tue, 12 Aug 2014 12:04:43 +0000 (13:04 +0100)]
FVP: apply new naming conventions to memory regions
Secure ROM at address 0x0000_0000 is defined as FVP_TRUSTED_ROM
Secure RAM at address 0x0400_0000 is defined as FVP_TRUSTED_SRAM
Secure RAM at address 0x0600_0000 is defined as FVP_TRUSTED_DRAM
BLn_BASE and BLn_LIMIT definitions have been updated and are based on
these new memory regions.
The available memory for each bootloader in the linker script is
defined by BLn_BASE and BLn_LIMIT, instead of the complete memory
region.
TZROM_BASE/SIZE and TZRAM_BASE/SIZE are no longer required as part of
the platform porting.
FVP common definitions are defined in fvp_def.h while platform_def.h
contains exclusively (with a few exceptions) the definitions that are
mandatory in the porting guide. Therefore, platform_def.h now includes
fvp_def.h instead of the other way around.
Porting guide has been updated to reflect these changes.
Change-Id: I39a6088eb611fc4a347db0db4b8f1f0417dbab05
Soby Mathew [Mon, 4 Aug 2014 15:02:05 +0000 (16:02 +0100)]
Reduce the runtime stack size in BL stages.
This patch separates the stack size for each BL stage and
reduces it after stack usage analysis was done.
Fixes ARM-software/tf-issues#200
Change-Id: I8edc6de2551b0a6788761d121937692b2149bb29
Soby Mathew [Wed, 16 Jul 2014 14:12:21 +0000 (15:12 +0100)]
Add compilation macro for each BL stage
This patch defines a compile time macro for each boot loader stage
which allows compilation of code only for a specific stage.
Change-Id: I3a4068404cd3dc26d652556ca9ca7afea8dd28ef
Juan Castillo [Fri, 1 Aug 2014 11:58:12 +0000 (12:58 +0100)]
Move up to Linaro 14.07 toolchain
Tests show a slight reduction in code size compared to 13.11.
User guide updated.
Fixes ARM-software/tf-issues#207
Change-Id: I9b80a5d7820cdfd443cac4d4b63f925b74a8c3a3
danh-arm [Mon, 4 Aug 2014 09:34:18 +0000 (10:34 +0100)]
Merge pull request #179 from jcastillo-arm/jc/tf-issues/219
Call platform_is_primary_cpu() only from reset handler
danh-arm [Mon, 4 Aug 2014 09:31:54 +0000 (10:31 +0100)]
Merge pull request #178 from soby-mathew/sm/optmize_el3_context
Optimize EL3 register state stored in cpu_context structure
danh-arm [Fri, 1 Aug 2014 11:17:51 +0000 (12:17 +0100)]
Merge pull request #175 from vikramkanigiri/vk/spd-init-by-stack-unwinding
Vk/spd init by stack unwinding
Vikram Kanigiri [Tue, 15 Jul 2014 15:49:22 +0000 (16:49 +0100)]
Support asynchronous method for BL3-2 initialization
This patch adds support for BL3-2 initialization by asynchronous
method where BL3-1 transfers control to BL3-2 using world switch.
After BL3-2 initialization, it transfers control to BL3-3 via SPD
service handler. The SPD service handler initializes the CPU context
to BL3-3 entrypoint depending on the return function indentifier from
TSP initialization.
Fixes ARM-software/TF-issues#184
Change-Id: I7b135c2ceeb356d3bb5b6a287932e96ac67c7a34
Vikram Kanigiri [Tue, 15 Jul 2014 15:46:43 +0000 (16:46 +0100)]
Rework the TSPD setup code
There is no mechanism which allows the TSPD to specify what SPSR to
use when entering BL3-2 instead of BL3-3. This patch divides the
responsibility between tspd_setup() and tspd_init() for initializing
the TSPD and TSP to support the alternate BL3-2 initialization flow
where BL3-1 handsover control to BL3-2 instead of BL3-3.
SPSR generated by TSPD for TSP is preserved due the new division of
labour which fixes #174.
This patch also moves the cpu_context initialization code from
tspd_setup() to tspd_init() immediately before entering the TSP.
Instead tspd_setup() updates the BL3-2 entrypoint info structure
with the state required for initializing the TSP later.
Fixes ARM-software/TF-issues#174
Change-Id: Ida0a8a48d466c71d5b07b8c7f2af169b73f96940
Juan Castillo [Wed, 16 Jul 2014 14:53:43 +0000 (15:53 +0100)]
Call platform_is_primary_cpu() only from reset handler
The purpose of platform_is_primary_cpu() is to determine after reset
(BL1 or BL3-1 with reset handler) if the current CPU must follow the
cold boot path (primary CPU), or wait in a safe state (secondary CPU)
until the primary CPU has finished the system initialization.
This patch removes redundant calls to platform_is_primary_cpu() in
subsequent bootloader entrypoints since the reset handler already
guarantees that code is executed exclusively on the primary CPU.
Additionally, this patch removes the weak definition of
platform_is_primary_cpu(), so the implementation of this function
becomes mandatory. Removing the weak symbol avoids other
bootloaders accidentally picking up an invalid definition in case the
porting layer makes the real function available only to BL1.
The define PRIMARY_CPU is no longer mandatory in the platform porting
because platform_is_primary_cpu() hides the implementation details
(for instance, there may be platforms that report the primary CPU in
a system register). The primary CPU definition in FVP has been moved
to fvp_def.h.
The porting guide has been updated accordingly.
Fixes ARM-software/tf-issues#219
Change-Id: If675a1de8e8d25122b7fef147cb238d939f90b5e
Soby Mathew [Fri, 4 Jul 2014 15:02:26 +0000 (16:02 +0100)]
Optimize EL3 register state stored in cpu_context structure
This patch further optimizes the EL3 register state stored in
cpu_context. The 2 registers which are removed from cpu_context are:
* cntfrq_el0 is the system timer register which is writable
only in EL3 and it can be programmed during cold/warm boot. Hence
it need not be saved to cpu_context.
* cptr_el3 controls access to Trace, Floating-point, and Advanced
SIMD functionality and it is programmed every time during cold
and warm boot. The current BL3-1 implementation does not need to
modify the access controls during normal execution and hence
they are expected to remain static.
Fixes ARM-software/tf-issues#197
Change-Id: I599ceee3b73a7dcfd37069fd41b60e3d397a7b18
danh-arm [Mon, 28 Jul 2014 13:33:44 +0000 (14:33 +0100)]
Merge pull request #177 from jcastillo-arm/jc/tf-issues/096
Rework incorrect use of assert() and panic() in codebase
danh-arm [Mon, 28 Jul 2014 13:28:40 +0000 (14:28 +0100)]
Merge pull request #172 from soby-mathew/sm/asm_assert
Introduce asm assert and optimize crash reporting
danh-arm [Mon, 28 Jul 2014 13:27:25 +0000 (14:27 +0100)]
Merge pull request #170 from achingupta/ag/tf-issues#226
Simplify management of SCTLR_EL3 and SCTLR_EL1
danh-arm [Mon, 28 Jul 2014 13:24:52 +0000 (14:24 +0100)]
Merge pull request #169 from achingupta/ag/tf-issues#198
Ag/tf issues#198
Juan Castillo [Thu, 5 Jun 2014 08:45:36 +0000 (09:45 +0100)]
Rework incorrect use of assert() and panic() in codebase
Assert a valid security state using the macro sec_state_is_valid().
Replace assert() with panic() in those cases that might arise
because of runtime errors and not programming errors.
Replace panic() with assert() in those cases that might arise
because of programming errors.
Fixes ARM-software/tf-issues#96
Change-Id: I51e9ef0439fd5ff5e0edfef49050b69804bf14d5
Soby Mathew [Wed, 16 Jul 2014 08:23:52 +0000 (09:23 +0100)]
Add CPUECTLR_EL1 and Snoop Control register to crash reporting
This patch adds the CPUECTLR_EL1 register and the CCI Snoop Control
register to the list of registers being reported when an unhandled
exception occurs.
Change-Id: I2d997f2d6ef3d7fa1fad5efe3364dc9058f9f22c
Soby Mathew [Wed, 25 Jun 2014 09:07:40 +0000 (10:07 +0100)]
Rework the crash reporting in BL3-1 to use less stack
This patch reworks the crash reporting mechanism to further
optimise the stack and code size. The reporting makes use
of assembly console functions to avoid calling C Runtime
to report the CPU state. The crash buffer requirement is
reduced to 64 bytes with this implementation. The crash
buffer is now part of per-cpu data which makes retrieving
the crash buffer trivial.
Also now panic() will use crash reporting if
invoked from BL3-1.
Fixes ARM-software/tf-issues#199
Change-Id: I79d27a4524583d723483165dc40801f45e627da5
Soby Mathew [Mon, 14 Jul 2014 15:58:03 +0000 (16:58 +0100)]
Implement an assert() callable from assembly code
The patch implements a macro ASM_ASSERT() which can
be invoked from assembly code. When assertion happens,
file name and line number of the check is written
to the crash console.
Fixes ARM-software/tf-issues#95
Change-Id: I6f905a068e1c0fa4f746d723f18df60daaa00a86
Soby Mathew [Mon, 14 Jul 2014 15:57:23 +0000 (16:57 +0100)]
Introduce crash console APIs for crash reporting
This patch introduces platform APIs to initialise and
print a character on a designated crash console.
For the FVP platform, PL011_UART0 is the designated
crash console. The platform porting guide is also updated
to document the new APIs.
Change-Id: I5e97d8762082e0c88c8c9bbb479353eac8f11a66
Soby Mathew [Mon, 14 Jul 2014 14:43:21 +0000 (15:43 +0100)]
Parametrize baudrate and UART clock during console_init()
This patch adds baud rate and UART clock frequency as parameters
to the pl011 driver api console_init(). This allows each platform
to specify UART clock and baud rate according to their specific
hardware implementation.
Fixes ARM-software/tf-issues#215
Change-Id: Id13eef70a1c530e709b34dd1e6eb84db0797ced2
Soby Mathew [Tue, 24 Jun 2014 11:28:41 +0000 (12:28 +0100)]
Introduce asm console functions in TF
This patch replaces the pl011 console family of functions
with their equivalents defined in assembly. The baud rate is
defined by the PL011_BAUDRATE macro and IBRD and FBRD values
for pl011 are computed statically. This patch will enable
us to invoke the console functions without the C Runtime Stack.
Change-Id: Ic3f7b7370ded38bf9020bf746b362081b76642c7
Achin Gupta [Fri, 18 Jul 2014 17:38:28 +0000 (18:38 +0100)]
Simplify management of SCTLR_EL3 and SCTLR_EL1
This patch reworks the manner in which the M,A, C, SA, I, WXN & EE bits of
SCTLR_EL3 & SCTLR_EL1 are managed. The EE bit is cleared immediately after reset
in EL3. The I, A and SA bits are set next in EL3 and immediately upon entry in
S-EL1. These bits are no longer managed in the blX_arch_setup() functions. They
do not have to be saved and restored either. The M, WXN and optionally the C
bit are set in the enable_mmu_elX() function. This is done during both the warm
and cold boot paths.
Fixes ARM-software/tf-issues#226
Change-Id: Ie894d1a07b8697c116960d858cd138c50bc7a069
Achin Gupta [Thu, 26 Jun 2014 10:12:37 +0000 (11:12 +0100)]
Remove the concept of coherent stacks
This patch removes the allocation of memory for coherent stacks, associated
accessor function and some dead code which called the accessor function. It also
updates the porting guide to remove the concept and the motivation behind using
stacks allocated in coherent memory.
Fixes ARM-software/tf-issues#198
Change-Id: I00ff9a04f693a03df3627ba39727e3497263fc38
danh-arm [Fri, 25 Jul 2014 14:11:47 +0000 (15:11 +0100)]
Merge pull request #176 from danh-arm/jc/tf-issues/203-v3
Add support for printing version at runtime v3
Juan Castillo [Mon, 30 Jun 2014 10:41:46 +0000 (11:41 +0100)]
Add support for printing version at runtime
Print out Trusted Firmware version at runtime at each BL stage.
Message consists of TF version as defined statically in the Makefile
(e.g. v0.4), build mode (debug|release) and a customizable build
string:
1. By defining BUILD_STRING in command line when building TF
2. Default string is git commit ID
3. Empty if git meta-data is not available
Fixes ARM-software/tf-issues#203
Change-Id: I5c5ba438f66ab68810427d76b49c5b9177a957d6
Dan Handley [Fri, 25 Jul 2014 13:57:54 +0000 (14:57 +0100)]
Merge pull request #167 from jcastillo-arm/jc/tf-issues/217
FVP: Ensure system reset wake-up results in cold boot
Dan Handley [Fri, 25 Jul 2014 13:56:46 +0000 (14:56 +0100)]
Merge pull request #168 from sandrine-bailleux/sb/set-default-gic-arch
Define ARM_GIC_ARCH default value for all platforms
Dan Handley [Fri, 25 Jul 2014 13:54:38 +0000 (14:54 +0100)]
Merge pull request #174 from soby-mathew:sm/lean_printf_v2
Implement a leaner printf for Trusted Firmware
Soby Mathew [Thu, 12 Jun 2014 16:23:58 +0000 (17:23 +0100)]
Implement a leaner printf for Trusted Firmware
This patch implements a "tf_printf" which supports only the commonly
used format specifiers in Trusted Firmware, which uses a lot less
stack space than the stdlib printf function.
Fixes ARM-software/tf-issues#116
Change-Id: I7dfa1944f4c1e634b3e2d571f49afe02d109a351
Achin Gupta [Thu, 26 Jun 2014 08:58:52 +0000 (09:58 +0100)]
Remove coherent stack usage from the warm boot path
This patch uses stacks allocated in normal memory to enable the MMU early in the
warm boot path thus removing the dependency on stacks allocated in coherent
memory. Necessary cache and stack maintenance is performed when a cpu is being
powered down and up. This avoids any coherency issues that can arise from
reading speculatively fetched stale stack memory from another CPUs cache. These
changes affect the warm boot path in both BL3-1 and BL3-2.
The EL3 system registers responsible for preserving the MMU state are not saved
and restored any longer. Static values are used to program these system
registers when a cpu is powered on or resumed from suspend.
Change-Id: I8357e2eb5eb6c5f448492c5094b82b8927603784
Achin Gupta [Thu, 26 Jun 2014 07:59:07 +0000 (08:59 +0100)]
Make enablement of the MMU more flexible
This patch adds a 'flags' parameter to each exception level specific function
responsible for enabling the MMU. At present only a single flag which indicates
whether the data cache should also be enabled is implemented. Subsequent patches
will use this flag when enabling the MMU in the warm boot paths.
Change-Id: I0eafae1e678c9ecc604e680851093f1680e9cefa
Achin Gupta [Wed, 25 Jun 2014 18:26:22 +0000 (19:26 +0100)]
Remove coherent stack usage from the cold boot path
This patch reworks the cold boot path across the BL1, BL2, BL3-1 and BL3-2 boot
loader stages to not use stacks allocated in coherent memory for early platform
setup and enabling the MMU. Stacks allocated in normal memory are used instead.
Attributes for stack memory change from nGnRnE when the MMU is disabled to
Normal WBWA Inner-shareable when the MMU and data cache are enabled. It is
possible for the CPU to read stale stack memory after the MMU is enabled from
another CPUs cache. Hence, it is unsafe to turn on the MMU and data cache while
using normal stacks when multiple CPUs are a part of the same coherency
domain. It is safe to do so in the cold boot path as only the primary cpu
executes it. The secondary cpus are in a quiescent state.
This patch does not remove the allocation of coherent stack memory. That is done
in a subsequent patch.
Change-Id: I12c80b7c7ab23506d425c5b3a8a7de693498f830
Sandrine Bailleux [Thu, 17 Jul 2014 16:23:14 +0000 (17:23 +0100)]
Define ARM_GIC_ARCH default value for all platforms
The ARM_GIC_ARCH build option was supposed to default to 2 on all
platforms. However, the default value was set in the FVP makefile
so for all other platforms it wasn't even defined.
This patch moves the default value to the main Makefile. The platform
port can then override it if needed.
Change-Id: I8e2da1cce7ffa3ed18814bbdcbcf2578101f18a6
Juan Castillo [Fri, 11 Jul 2014 09:23:18 +0000 (10:23 +0100)]
FVP: Ensure system reset wake-up results in cold boot
platform_get_entrypoint() did not consider that a wakeup due to
System Reset Pin (by reading the power controller's PSYSR) requires
a cold boot. As a result, the code would execute the warm boot path
and eventually panic because entrypoint mailboxes are empty.
This patch ensures that the following wake-up reasons result in cold
boot:
- Cold Power-on
- System Reset Pin (includes reset by software)
Fixes ARM-software/tf-issues#217
Change-Id: I65ae0a0f7a46548b575900a5aac107d352b0e2cd
danh-arm [Fri, 11 Jul 2014 13:17:05 +0000 (14:17 +0100)]
Merge pull request #162 from jcastillo-arm/jc/tf-issues/194
Allow FP register context to be optional at build time
danh-arm [Fri, 11 Jul 2014 13:16:13 +0000 (14:16 +0100)]
Merge pull request #164 from sandrine-bailleux/sb/bl30-support-v2
Add support for BL3-0 image (v2)
danh-arm [Fri, 11 Jul 2014 10:19:27 +0000 (11:19 +0100)]
Merge pull request #163 from sandrine-bailleux/sb/tf-issue-117-v2
fvp: Reuse BL1 and BL2 memory through image overlaying (v2)
Sandrine Bailleux [Mon, 23 Jun 2014 16:00:23 +0000 (17:00 +0100)]
Update the documentation about the memory layout on FVP
Update the "Memory layout on FVP platforms" section in the Firmware
Design document to reflect the overlaying of BL1 and BL2 images
by BL3-1 and BL3-2.
Also update the Porting Guide document to mention the
BL31_PROGBITS_LIMIT and BL32_PROGBITS_LIMIT constants.
Change-Id: I0b23dae5b5b4490a01be7ff7aa80567cff34bda8
Sandrine Bailleux [Tue, 24 Jun 2014 13:19:36 +0000 (14:19 +0100)]
Add support for BL3-0 image
- Add support for loading a BL3-0 image in BL2. Information about
memory extents is populated by platform-specific code. Subsequent
handling of BL3-0 is also platform specific.
The BL2 main function has been broken down to improve readability.
The BL3-2 image is now loaded before the BL3-3 image to align with
the boot flow.
- Build system: Add support for specifying a BL3-0 image that will be
included into the FIP image.
- IO FIP driver: Add support for identifying a BL3-0 image inside a
FIP image.
- Update the documentation to reflect the above changes.
Change-Id: I067c184afd52ccaa86569f13664757570c86fc48
Sandrine Bailleux [Mon, 16 Jun 2014 15:12:27 +0000 (16:12 +0100)]
fvp: Reuse BL1 and BL2 memory through image overlaying
This patch re-organizes the memory layout on FVP as to give the
BL3-2 image as much memory as possible.
Considering these two facts:
- not all images need to live in memory at the same time. Once
in BL3-1, the memory used by BL1 and BL2 can be reclaimed.
- when BL2 loads the BL3-1 and BL3-2 images, it only considers the
PROGBITS sections of those 2 images. The memory occupied by the
NOBITS sections will be touched only at execution of the BL3-x
images;
Then it is possible to choose the different base addresses such that
the NOBITS sections of BL3-1 and BL3-2 overlay BL1 and BL2.
On FVP we choose to put:
- BL1 and BL3-1 at the top of the Trusted RAM, with BL3-1 NOBITS
sections overlaying BL1;
- BL3-2 at the bottom of the Trusted RAM, with its NOBITS sections
overlaying BL2;
This is illustrated by the following diagram:
0x0404_0000 ------------ ------------------
| BL1 | <= | BL3-1 NOBITS |
------------ <= ------------------
| | <= | BL3-1 PROGBITS |
------------ ------------------
| BL2 | <= | BL3-2 NOBITS |
------------ <= ------------------
| | <= | BL3-2 PROGBITS |
0x0400_0000 ------------ ------------------
New platform-specific constants have been introduced to easily check
at link time that BL3-1 and BL3-2 PROGBITS sections don't overwrite
BL1 and BL2. These are optional and the platform code is free to define
them or not. If not defined, the linker won't attempt to check
image overlaying.
Fixes ARM-software/tf-issues#117
Change-Id: I5981d1c3d66ee70eaac8bd052630c9ac6dd8b042
danh-arm [Thu, 10 Jul 2014 13:45:19 +0000 (14:45 +0100)]
Merge pull request #157 from sandrine-bailleux/sb/tf-issue-109
TF issue 109
danh-arm [Thu, 10 Jul 2014 13:44:24 +0000 (14:44 +0100)]
Merge pull request #146 from danh-arm/dh/refactor-fvp-gic
Refactor fvp config and gic code
danh-arm [Thu, 10 Jul 2014 13:43:48 +0000 (14:43 +0100)]
Merge pull request #161 from danh-arm/lm/calc-tcr-bits
Calculate TCR bits based on VA and PA
Juan Castillo [Wed, 25 Jun 2014 16:26:36 +0000 (17:26 +0100)]
Allow FP register context to be optional at build time
CTX_INCLUDE_FPREGS make variable allows us to include or exclude FP
registers from context structure, in case FP is not used by TSPD.
Fixes ARM-software/tf-issues#194
Change-Id: Iee41af382d691340c7ae21830ad1bbf95dad1f4b
Dan Handley [Fri, 20 Jun 2014 08:43:15 +0000 (09:43 +0100)]
Refactor fvp gic code to be a generic driver
Refactor the FVP gic code in plat/fvp/fvp_gic.c to be a generic ARM
GIC driver in drivers/arm/gic/arm_gic.c. Provide the platform
specific inputs in the arm_gic_setup() function so that the driver
has no explicit dependency on platform code.
Provide weak implementations of the platform interrupt controller
API in a new file, plat/common/plat_gic.c. These simply call through
to the ARM GIC driver.
Move the only remaining FVP GIC function, fvp_gic_init() to
plat/fvp/aarch64/fvp_common.c and remove plat/fvp/fvp_gic.c
Fixes ARM-software/tf-issues#182
Change-Id: Iea82fe095fad62dd33ba9efbddd48c57717edd21