project/bcm63xx/atf.git
6 years agoallwinner: Find DTB in BL33 image
Andre Przywara [Sun, 16 Sep 2018 01:08:06 +0000 (02:08 +0100)]
allwinner: Find DTB in BL33 image

The initial PMIC setup for the Allwinner platform is quite board
specific, and used to be guarded by reading the .dtb stub *name* from the
SPL image in the legacy ATF port. This doesn't scale particularly well,
and requires constant maintainance.
Instead having the actual .dtb available would be much better, as the PMIC
setup requirements could be read from there directly.
The only available BL33 for Allwinner platforms so far is U-Boot, and
fortunately U-Boot comes with the full featured .dtb, appended to the
end of the U-Boot image.

Introduce some code that scans the beginning of the BL33 image to look
for the load address, which is followed by the image size. Adding those
two values together gives us the end of the image and thus the .dtb
address. Verify that this heuristic is valid by sanitising some values
and checking the DTB magic.

Print out the DTB address and the model name, if specified in the root
node.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
6 years agoallwinner: A64: Add AXP803 PMIC support to power off the board
Andre Przywara [Sat, 15 Sep 2018 00:18:49 +0000 (01:18 +0100)]
allwinner: A64: Add AXP803 PMIC support to power off the board

Boards with the Allwinner A64 SoC are mostly paired with an AXP803 PMIC,
which allows to programmatically power down the board.

Use the newly introduced RSB driver to detect and program the PMIC on
boot, then later to turn off the main voltage rails when receiving a
PSCI SYSTEM_POWER_OFF command.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
6 years agoallwinner: H6: Factor out I2C platform setup
Andre Przywara [Sun, 14 Oct 2018 21:13:53 +0000 (22:13 +0100)]
allwinner: H6: Factor out I2C platform setup

In the H6 platform code there is a routine to do the platform
initialisation of the R_I2C controller. We will need a very similar
setup routine to initialise the RSB controller on the A64.

Move this code to sunxi_common.c and generalise it to support all SoCs
and also to cover the related RSB bus.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
6 years agoallwinner: Add RSB driver
Andre Przywara [Wed, 13 Dec 2017 01:08:01 +0000 (01:08 +0000)]
allwinner: Add RSB driver

The "Reduced Serial Bus" is an Allwinner specific bus, bearing many
similarities with I2C. It sports a much higher bus frequency, though,
(typically 3 MHz) and requires much less handholding for the typical
task of manipulating slave registers (fire-and-forget).
On most A64 boards this bus is used to connect the PMIC to the SoC.

This driver provides basic primitives to read and write slave registers,
it will be later used by the PMIC code.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
6 years agoallwinner: H5: Implement power down for H5 reference design boards
Andre Przywara [Mon, 1 Oct 2018 23:21:53 +0000 (00:21 +0100)]
allwinner: H5: Implement power down for H5 reference design boards

Allwinner produces reference board designs, which apparently most board
vendors copy from. So every H5 board I checked uses regulators which are
controlled by the same PortL GPIO pins to power the ARM CPU cores, the
DRAM and the I/O ports.
Add a SoC specific power down routine, which turns those regulators off
when ATF detects running on an H5 SoC and the rich OS triggers a
SYSTEM_POWEROFF PSCI call.

NOTE: It sounds very tempting to turn the CPU power off, but this is not
working as expected, instead the system is rebooting. Most probably this
is due to VCC-SYS also being controlled by the same GPIO line, and
turning this off requires an elaborate and not fully understood setup.
Apparently not even Allwinner reference code is turning this regulator
off. So for now we refrain to pulling down PL8, the power consumption is
quite low anyway, so we are as close to poweroff as reasonably possible.
Many thanks to Samuel for doing some research on that topic.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
6 years agoallwinner: Introduce GPIO helper function
Andre Przywara [Sun, 14 Oct 2018 11:03:23 +0000 (12:03 +0100)]
allwinner: Introduce GPIO helper function

Many boards without a dedicated PMIC contain simple regulators, which
can be controlled via GPIO pins.

To later allow turning them off easily, introduce a simple function to
configure a given pin as a GPIO out pin and set it to the desired level.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
6 years agoallwinner: Export sunxi_private.h
Andre Przywara [Sun, 14 Oct 2018 11:02:02 +0000 (12:02 +0100)]
allwinner: Export sunxi_private.h

So far we have a sunxi_private.h header file in the common code directory.
This holds the prototypes of various functions we share in *common*
code. However we will need some of those in the platform specific code
parts as well, and want to introduce new functions shared across the
whole platform port.

So move the sunxi_private.h file into the common/include directory, so
that it becomes visible to all parts of the platform code.
Fix up the existing #includes and add missing ones, also add the
sunxi_read_soc_id() prototype here.

This will be used in follow up patches.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
6 years agoallwinner: A64/H5: Add basic and generic shutdown method
Andre Przywara [Mon, 1 Oct 2018 23:21:49 +0000 (00:21 +0100)]
allwinner: A64/H5: Add basic and generic shutdown method

Some boards don't have a PMIC, so they can't easily turn their power
off. To cover those boards anyway, let's turn off as many devices and
clocks as possible, so that the power consumption is reduced. Then
halt the last core, as before.
This will later be extended with proper PMIC support for supported
boards.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
6 years agoallwinner: Pass SoC ID to sunxi_pmic_setup()
Andre Przywara [Sat, 8 Sep 2018 18:18:37 +0000 (19:18 +0100)]
allwinner: Pass SoC ID to sunxi_pmic_setup()

In the BL31 platform setup we read the Allwinner SoC ID to identify the
chip and print its name.
In addition to that we will need to differentiate the power setup
between the SoCs, to pass on the SoC ID to the PMIC setup routine.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
6 years agoallwinner: Introduce names for SoC IDs
Andre Przywara [Sun, 16 Sep 2018 23:03:09 +0000 (00:03 +0100)]
allwinner: Introduce names for SoC IDs

We will soon make more use of the Allwinner SoC ID, to differentiate the
platform setup.
Introduce definitions to avoid dealing with magic numbers and make the
code more readable.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
6 years agoallwinner: H6: Fix SRAM size
Andre Przywara [Mon, 15 Oct 2018 23:58:22 +0000 (00:58 +0100)]
allwinner: H6: Fix SRAM size

The SRAM in the Allwinner H6 SoC starts at 0x2000, with the last part
ending at 0x117fff (although with gaps in between).
So SUNXI_SRAM_SIZE should be 0xf8000, not 0x98000.

Fix this to map the arisc exception vector area, which we will need
shortly.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
6 years agoallwinner: Disable USE_COHERENT_MEM
Andre Przywara [Thu, 11 Oct 2018 21:14:30 +0000 (22:14 +0100)]
allwinner: Disable USE_COHERENT_MEM

According to the documentation, platforms may choose to trade memory
footprint for performance (and elegancy) by not providing a separately
mapped coherent page.

Since a debug build is getting close to the SRAM size limit already, this
allows us to save about 3.5KB of BSS and have some room for future
enhancements.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
6 years agoallwinner: Adjust memory mapping to fit into 256MB
Andre Przywara [Thu, 20 Sep 2018 20:13:55 +0000 (21:13 +0100)]
allwinner: Adjust memory mapping to fit into 256MB

At the moment we map as much of the DRAM into EL3 as possible, however
we actually don't use it. The only exception is the secure DRAM for
BL32 (if that is configured).

To decrease the memory footprint of ATF, we save on some page tables by
reducing the memory mapping to the actually required regions: SRAM, device
MMIO, secure DRAM and U-Boot (to be used later).
This introduces a non-identity mapping for the DRAM regions.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
6 years agoallwinner: Unify platform.mk files
Andre Przywara [Thu, 27 Sep 2018 23:37:19 +0000 (00:37 +0100)]
allwinner: Unify platform.mk files

For the two different platforms we support in the Allwinner port we
mostly rely on header files covering the differences. This leads to the
platform.mk files in the respective directories to be almost identical.

To avoid further divergence and make sure that one platform doesn't
break accidentally, let's create a shared allwinner-common.mk file and
include that from the platform directory.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
6 years agoMerge pull request #1632 from Yann-lms/stm32mp1_mmc
Soby Mathew [Thu, 18 Oct 2018 09:44:53 +0000 (10:44 +0100)]
Merge pull request #1632 from Yann-lms/stm32mp1_mmc

Add MMC support for STM32MP1

6 years agoMerge pull request #1582 from ldts/rcar_gen3/upstream
Soby Mathew [Thu, 18 Oct 2018 08:54:55 +0000 (09:54 +0100)]
Merge pull request #1582 from ldts/rcar_gen3/upstream

rcar_gen3: initial support

6 years agoMerge pull request #1553 from glneo/dcache-late-disable
Soby Mathew [Thu, 18 Oct 2018 08:49:03 +0000 (09:49 +0100)]
Merge pull request #1553 from glneo/dcache-late-disable

Allow D-Cache to remain on during core power-down

6 years agoMerge pull request #1629 from robertovargas-arm/hw-assisted-coherency-lock
Soby Mathew [Thu, 18 Oct 2018 08:35:14 +0000 (09:35 +0100)]
Merge pull request #1629 from robertovargas-arm/hw-assisted-coherency-lock

Optimize bakery locks when HW_ASSISTED_COHERENCY is enabled

6 years agoMerge pull request #1631 from deepan02/deepak-arm/relocate-jump_if_cpu_midr
Soby Mathew [Thu, 18 Oct 2018 08:34:20 +0000 (09:34 +0100)]
Merge pull request #1631 from deepan02/deepak-arm/relocate-jump_if_cpu_midr

plat/arm: relocate the jump_if_cpu_midr macro.

6 years agoMerge pull request #1628 from antonio-nino-diaz-arm/an/sharing
Soby Mathew [Thu, 18 Oct 2018 08:20:04 +0000 (09:20 +0100)]
Merge pull request #1628 from antonio-nino-diaz-arm/an/sharing

plat/arm: Small reorganization of platform code

6 years agorcar_gen3: drivers: watchdog
Jorge Ramirez-Ortiz [Sun, 23 Sep 2018 07:42:08 +0000 (09:42 +0200)]
rcar_gen3: drivers: watchdog

Signed-off-by: ldts <jramirez@baylibre.com>
6 years agorcar_gen3: drivers: serial controller interface
Jorge Ramirez-Ortiz [Sun, 23 Sep 2018 07:41:53 +0000 (09:41 +0200)]
rcar_gen3: drivers: serial controller interface

Signed-off-by: ldts <jramirez@baylibre.com>
6 years agorcar_gen3: drivers: spi multio bus controller
Jorge Ramirez-Ortiz [Sun, 23 Sep 2018 07:41:39 +0000 (09:41 +0200)]
rcar_gen3: drivers: spi multio bus controller

Signed-off-by: ldts <jramirez@baylibre.com>
6 years agorcar_gen3: drivers: rom api
Jorge Ramirez-Ortiz [Sun, 23 Sep 2018 07:41:21 +0000 (09:41 +0200)]
rcar_gen3: drivers: rom api

Signed-off-by: ldts <jramirez@baylibre.com>
6 years agorcar_gen3: drivers: power controller
Jorge Ramirez-Ortiz [Sun, 23 Sep 2018 07:41:10 +0000 (09:41 +0200)]
rcar_gen3: drivers: power controller

Signed-off-by: ldts <jramirez@baylibre.com>
6 years agorcar_gen3: drivers: console
Jorge Ramirez-Ortiz [Sun, 23 Sep 2018 07:41:00 +0000 (09:41 +0200)]
rcar_gen3: drivers: console

Signed-off-by: ldts <jramirez@baylibre.com>
6 years agorcar_gen3: drivers: io [emmc/mem]
Jorge Ramirez-Ortiz [Sun, 23 Sep 2018 07:40:45 +0000 (09:40 +0200)]
rcar_gen3: drivers: io [emmc/mem]

Signed-off-by: ldts <jramirez@baylibre.com>
6 years agorcar_gen3: drivers: i2c dvfs
Jorge Ramirez-Ortiz [Sun, 23 Sep 2018 07:40:26 +0000 (09:40 +0200)]
rcar_gen3: drivers: i2c dvfs

Signed-off-by: ldts <jramirez@baylibre.com>
6 years agorcar_gen3: drivers: emmc
Jorge Ramirez-Ortiz [Sun, 23 Sep 2018 07:39:56 +0000 (09:39 +0200)]
rcar_gen3: drivers: emmc

Signed-off-by: ldts <jramirez@baylibre.com>
6 years agorcar_gen3: drivers: dma
Jorge Ramirez-Ortiz [Sun, 23 Sep 2018 07:39:48 +0000 (09:39 +0200)]
rcar_gen3: drivers: dma

Signed-off-by: ldts <jramirez@baylibre.com>
6 years agorcar_gen3: drivers: micro delay generator
Jorge Ramirez-Ortiz [Sun, 23 Sep 2018 07:39:37 +0000 (09:39 +0200)]
rcar_gen3: drivers: micro delay generator

Signed-off-by: ldts <jramirez@baylibre.com>
6 years agorcar_gen3: drivers: cpld
Jorge Ramirez-Ortiz [Sun, 23 Sep 2018 07:39:19 +0000 (09:39 +0200)]
rcar_gen3: drivers: cpld

Signed-off-by: ldts <jramirez@baylibre.com>
6 years agorcar_gen3: drivers: board identification
Jorge Ramirez-Ortiz [Sun, 23 Sep 2018 07:39:11 +0000 (09:39 +0200)]
rcar_gen3: drivers: board identification

Signed-off-by: ldts <jramirez@baylibre.com>
6 years agorcar_gen3: drivers: avs [adaptive voltage scaling]
Jorge Ramirez-Ortiz [Sun, 23 Sep 2018 07:38:56 +0000 (09:38 +0200)]
rcar_gen3: drivers: avs [adaptive voltage scaling]

Signed-off-by: ldts <jramirez@baylibre.com>
6 years agorcar_gen3: drivers: authentication
Jorge Ramirez-Ortiz [Sun, 23 Sep 2018 07:38:24 +0000 (09:38 +0200)]
rcar_gen3: drivers: authentication

Signed-off-by: ldts <jramirez@baylibre.com>
6 years agorcar_gen3: drivers: staging
Jorge Ramirez-Ortiz [Sun, 23 Sep 2018 07:36:52 +0000 (09:36 +0200)]
rcar_gen3: drivers: staging

 - ddr
 - pfc [pin function controller]
 - qos [bandwidth]

checkpatch.pl is generating too many errors.

6 years agorcar-gen3: initial commit for the rcar-gen3 boards
Jorge Ramirez-Ortiz [Sun, 23 Sep 2018 07:36:13 +0000 (09:36 +0200)]
rcar-gen3: initial commit for the rcar-gen3 boards

Reference code:
==============

rar_gen3: IPL and Secure Monitor Rev1.0.22
https://github.com/renesas-rcar/arm-trusted-firmware [rcar_gen3]

Author: Takuya Sakata <takuya.sakata.wz@bp.renesas.com>
Date:   Thu Aug 30 21:26:41 2018 +0900
Update IPL and Secure Monitor Rev1.0.22

General Information:
===================

This port has been tested on the Salvator-X Soc_id r8a7795 revision
ES1.1 (uses an SPD).

Build Tested:
-------------
ATFW_OPT="LSI=H3 RCAR_DRAM_SPLIT=1 RCAR_LOSSY_ENABLE=1"
MBEDTLS_DIR=$mbedtls

$ make clean bl2 bl31 rcar PLAT=rcar ${ATFW_OPT} SPD=opteed

Other dependencies:
------------------
* mbed_tls:
  git@github.com:ARMmbed/mbedtls.git [devel]

  Merge: 68dbc94 f34a4c1
  Author: Simon Butcher <simon.butcher@arm.com>
  Date:   Thu Aug 30 00:57:28 2018 +0100

* optee_os:
  https://github.com/BayLibre/optee_os

  Until it gets merged into OP-TEE, the port requires Renesas' Trusted
  Environment with a modification to support power management.

  Author: Jorge Ramirez-Ortiz <jramirez@baylibre.com>
  Date:   Thu Aug 30 16:49:49 2018 +0200
    plat-rcar: cpu-suspend: handle the power level
Signed-off-by: Jorge Ramirez-Ortiz <jramirez@baylibre.com>
* u-boot:
  The port has beent tested using mainline uboot.

  Author: Fabio Estevam <festevam@gmail.com>
  Date:   Tue Sep 4 10:23:12 2018 -0300

*linux:
  The port has beent tested using mainline kernel.

  Author: Linus Torvalds <torvalds@linux-foundation.org>
  Date:   Sun Sep 16 11:52:37 2018 -0700
      Linux 4.19-rc4

Overview
---------

BOOTROM starts the cpu at EL3; In this port BL2 will therefore be entered
at this exception level (the Renesas' ATF reference tree [1] resets into
EL1 before entering BL2 - see its bl2.ld.S)

BL2 initializes DDR (and i2c to talk to the PMIC on some platforms)
before determining the boot reason (cold or warm).

During suspend all CPUs are switched off and the DDR is put in
backup mode (some kind of self-refresh mode). This means that BL2 is
always entered in a cold boot scenario.

Once BL2 boots, it determines the boot reason, writes it to shared
memory (BOOT_KIND_BASE) together with the BL31 parameters
(PARAMS_BASE) and jumps to BL31.

To all effects, BL31 is as if it is being entered in reset mode since
it still needs to initialize the rest of the cores; this is the reason
behind using direct shared memory access to  BOOT_KIND_BASE and
PARAMS_BASE instead of using registers to get to those locations (see
el3_common_macros.S and bl31_entrypoint.S for the RESET_TO_BL31 use
case).

Depending on the boot reason BL31 initializes the rest of the cores:
in case of suspend, it uses a MBOX memory region to recover the
program counters.

[1] https://github.com/renesas-rcar/arm-trusted-firmware
Tests
-----

* cpuidle
  -------
   enable kernel's cpuidle arm_idle driver and boot

* system suspend
  --------------
  $ cat suspend.sh
    #!/bin/bash
    i2cset -f -y 7 0x30 0x20 0x0F
    read -p "Switch off SW23 and press return " foo
    echo mem > /sys/power/state

* cpu hotplug:
  ------------
  $ cat offline.sh
    #!/bin/bash
    nbr=$1
    echo 0 > /sys/devices/system/cpu/cpu$nbr/online
    printf "ONLINE:  " && cat /sys/devices/system/cpu/online
    printf "OFFLINE: " && cat /sys/devices/system/cpu/offline

  $ cat online.sh
    #!/bin/bash
    nbr=$1
    echo 1 > /sys/devices/system/cpu/cpu$nbr/online
    printf "ONLINE:  " && cat /sys/devices/system/cpu/online
    printf "OFFLINE: " && cat /sys/devices/system/cpu/offline

Signed-off-by: ldts <jramirez@baylibre.com>
6 years agoti: k3: common: Do not disable cache on TI K3 core powerdown
Andrew F. Davis [Fri, 12 Oct 2018 20:37:04 +0000 (15:37 -0500)]
ti: k3: common: Do not disable cache on TI K3 core powerdown

Leave the caches on and explicitly flush any data that
may be stale when the core is powered down. This prevents
non-coherent interconnect access which has negative side-
effects on AM65x.

Signed-off-by: Andrew F. Davis <afd@ti.com>
6 years agoscmi: Optimize bakery locks when HW_ASSISTED_COHERENCY is enabled
Roberto Vargas [Mon, 13 Nov 2017 13:41:58 +0000 (13:41 +0000)]
scmi: Optimize bakery locks when HW_ASSISTED_COHERENCY is enabled

When HW_ASSISTED_COHERENCY is enabled we can use spinlocks
instead of using the more complex and slower bakery algorithm.

Change-Id: I9d791a70050d599241169b9160a67e57d5506564
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
6 years agoplat/arm: relocate the jump_if_cpu_midr macro.
Deepak Pandey [Thu, 11 Oct 2018 08:14:43 +0000 (13:44 +0530)]
plat/arm: relocate the jump_if_cpu_midr macro.

macro jump_if_cpu_midr is used commonly by many arm platform.
It has now been relocated to common place to remove duplication
of code.

Change-Id: Ic0876097dbc085df4f90eadb4b7687dde7c726da
Signed-off-by: Deepak Pandey <Deepak.Pandey@arm.com>
6 years agostm32mp1: update platform files to use MMC devices
Yann Gautier [Mon, 15 Oct 2018 07:36:58 +0000 (09:36 +0200)]
stm32mp1: update platform files to use MMC devices

Signed-off-by: Yann Gautier <yann.gautier@st.com>
6 years agostm32mp1: add an IO to read MMC devices
Yann Gautier [Mon, 15 Oct 2018 07:36:44 +0000 (09:36 +0200)]
stm32mp1: add an IO to read MMC devices

Whereas the GPT table is read with io_block, the binaries to be loaded
(e.g. BL33) cannot use it, as it is not suitable to read them block by
block, or the boot time would be very bad.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
6 years agostm32mp1: add an IO to read STM32IMAGE binaries
Yann Gautier [Mon, 15 Oct 2018 07:36:32 +0000 (09:36 +0200)]
stm32mp1: add an IO to read STM32IMAGE binaries

This IO is required to read binaries with STM32 header.
This header is added with the stm32image tool.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
6 years agoAdd new defines for STM32MP1 platform
Yann Gautier [Mon, 15 Oct 2018 07:36:21 +0000 (09:36 +0200)]
Add new defines for STM32MP1 platform

To boot on eMMC or SD-cards, STM32MP1 platform needs:
- GPT_IMAGE_ID to read GPT table on those devices
- STM32_IMAGE_ID and IO_TYPE_STM32IMAGE to read images with STM32 header
- IO_TYPE_MMC to have a IO for MMC devices

Signed-off-by: Yann Gautier <yann.gautier@st.com>
6 years agostm32mp1: add sdmmc2 driver
Yann Gautier [Mon, 15 Oct 2018 07:36:04 +0000 (09:36 +0200)]
stm32mp1: add sdmmc2 driver

This driver is for the STMicroelectronics sdmmc2 IP
which is in STM32MP1 SoC.
It uses the MMC framework, and can address either eMMC or SD-card.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
6 years agoMerge pull request #1626 from Yann-lms/partition_verbose
Dimitris Papastamos [Fri, 12 Oct 2018 16:45:56 +0000 (17:45 +0100)]
Merge pull request #1626 from Yann-lms/partition_verbose

drivers: partition: correct compilation error in VERBOSE mode

6 years agoMerge pull request #1627 from sandrine-bailleux-arm/sb/object-pool-allocator
Dimitris Papastamos [Fri, 12 Oct 2018 16:45:31 +0000 (17:45 +0100)]
Merge pull request #1627 from sandrine-bailleux-arm/sb/object-pool-allocator

Introduce object pool allocator

6 years agoMerge pull request #1630 from antonio-nino-diaz-arm/an/fix-console
Dimitris Papastamos [Fri, 12 Oct 2018 16:45:09 +0000 (17:45 +0100)]
Merge pull request #1630 from antonio-nino-diaz-arm/an/fix-console

pl011: cnds: cbmem: 16550: Fix comments

6 years agopl011: cnds: cbmem: 16550: Fix comments
Antonio Nino Diaz [Mon, 8 Oct 2018 12:26:48 +0000 (13:26 +0100)]
pl011: cnds: cbmem: 16550: Fix comments

The comments with the prototypes of the register functions of the
console drivers are incorrect. The arguments are wrong. This patch fixes
them.

Change-Id: I38c4b481ee69e840780111c42f03c0752eb6315c
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
6 years agoMerge pull request #1615 from Andre-ARM/make_s
Soby Mathew [Fri, 12 Oct 2018 13:39:50 +0000 (14:39 +0100)]
Merge pull request #1615 from Andre-ARM/make_s

Makefile: Support totally quiet output with -s

6 years agoMerge pull request #1606 from satheesbalya-arm/sb1_2603_misra_plat
Soby Mathew [Fri, 12 Oct 2018 13:19:28 +0000 (14:19 +0100)]
Merge pull request #1606 from satheesbalya-arm/sb1_2603_misra_plat

plat/arm: Fix misra warnings in platform code

6 years agoMerge pull request #1622 from bryanodonoghue/master+imx7-mmc_fix
Soby Mathew [Fri, 12 Oct 2018 13:17:59 +0000 (14:17 +0100)]
Merge pull request #1622 from bryanodonoghue/master+imx7-mmc_fix

drivers: imx: mxc_usdhc: Do not set MMC_RSP_48 for MMC_RESPONSE_R2

6 years agoMerge pull request #1624 from glneo/less-cache-flushing
Soby Mathew [Fri, 12 Oct 2018 13:16:57 +0000 (14:16 +0100)]
Merge pull request #1624 from glneo/less-cache-flushing

PSCI cache flush and comment fixup

6 years agoplat/arm: Fix misra warnings in platform code
Sathees Balya [Thu, 27 Sep 2018 13:41:02 +0000 (14:41 +0100)]
plat/arm: Fix misra warnings in platform code

Change-Id: Ica944acc474a099219d50b041cfaeabd4f3d362f
Signed-off-by: Sathees Balya <sathees.balya@arm.com>
6 years agoIntroduce object pool allocator
Sandrine Bailleux [Fri, 1 Jun 2018 12:17:08 +0000 (14:17 +0200)]
Introduce object pool allocator

The object pool allocator provides a simplistic interface to manage
allocation in a fixed-size static array. The caller creates a static
"object pool" out of such an array and may then call pool_alloc() to
get the next available object within the pool. There is also a variant
to get multiple consecutive objects: pool_alloc_n().

Note that this interface does not provide any way to free the objects
afterwards. This is by design and it is not a limitation. We do not
want to introduce complexity induced by memory freeing, such as
use-after-free bugs, memory fragmentation and so on.

Change-Id: Iefc2e153767851fbde5841a295f92ae48adda71f
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
6 years agodrivers: partition: correct compilation error in VERBOSE mode
Yann Gautier [Thu, 4 Oct 2018 17:04:17 +0000 (19:04 +0200)]
drivers: partition: correct compilation error in VERBOSE mode

Signed-off-by: Yann Gautier <yann.gautier@st.com>
6 years agoMerge pull request #1625 from ldts/psci
Soby Mathew [Thu, 11 Oct 2018 12:37:53 +0000 (13:37 +0100)]
Merge pull request #1625 from ldts/psci

psci: platform control of SYSTEM_SUSPEND entry

6 years agoplat/arm: Remove file arm_board_def.h
Antonio Nino Diaz [Thu, 11 Oct 2018 12:02:34 +0000 (13:02 +0100)]
plat/arm: Remove file arm_board_def.h

This file is shared between FVP and all CSS platforms. While it may be
true that some definitions can be common, it doesn't make sense
conceptually. For example, the stack size depends on the platform and so
does the SRAM size.

After removing them, there are not enough common definitions to justify
having this header, so the other definitions have been moved to the
platform_def.h of FVP, board_css_def.h and arm_def.h.

Change-Id: Ifbf4b017227f9dfefa1a430f67d7d6baae6a4ba1
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
6 years agoMerge pull request #1621 from jts-arm/typos
Soby Mathew [Thu, 11 Oct 2018 11:00:48 +0000 (12:00 +0100)]
Merge pull request #1621 from jts-arm/typos

Various corrections of typos

6 years agoMerge pull request #1619 from antonio-nino-diaz-arm/an/norflash
Soby Mathew [Thu, 11 Oct 2018 10:59:37 +0000 (11:59 +0100)]
Merge pull request #1619 from antonio-nino-diaz-arm/an/norflash

plat/arm: Move norflash driver to drivers/ folder

6 years agopsci: platform control of SYSTEM_SUSPEND entry
ldts [Thu, 11 Oct 2018 06:40:32 +0000 (08:40 +0200)]
psci: platform control of SYSTEM_SUSPEND entry

Some platforms can only resume from system suspend from the boot
CPU, hence they should only enter that state from that same core.

The following commit presents an interface that allows the platform to
reject system suspend entry near its very last stage (last CPU).

6 years agoplat/arm: Move board_css_common.c to juno folder
Antonio Nino Diaz [Wed, 10 Oct 2018 10:02:34 +0000 (11:02 +0100)]
plat/arm: Move board_css_common.c to juno folder

This file is only used by Juno as all other CSS platforms have their own
private memory maps.

Change-Id: I1c9f27aac7b1d8bff4d92674e8bde5505b93c8c4
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
6 years agoMerge pull request #1620 from deepan02/deepak-arm/move-reset-to-bl31
Soby Mathew [Thu, 11 Oct 2018 08:55:00 +0000 (09:55 +0100)]
Merge pull request #1620 from deepan02/deepak-arm/move-reset-to-bl31

plat/arm: allow RESET_TO_BL31 for CSS-based platforms

6 years agoPSCI: Do not flush cache when unneeded
Andrew F. Davis [Thu, 30 Aug 2018 17:13:57 +0000 (12:13 -0500)]
PSCI: Do not flush cache when unneeded

When a platform enables its caches before it accesses the
psci_non_cpu_pd_nodes structure then explicit cache maintenance
is not needed.

Signed-off-by: Andrew F. Davis <afd@ti.com>
6 years agoPSCI: Update comment on MMU disablement
Andrew F. Davis [Thu, 30 Aug 2018 17:08:01 +0000 (12:08 -0500)]
PSCI: Update comment on MMU disablement

The MMU is not disabled in this path, update the comment to
reflect this. Also clarify that both paths call prepare_cpu_pwr_dwn(),
but the second path does stack cache maintenance.

Signed-off-by: Andrew F. Davis <afd@ti.com>
6 years agoMerge pull request #1614 from MISL-EBU-System-SW/integration-fix
Soby Mathew [Wed, 10 Oct 2018 13:00:34 +0000 (14:00 +0100)]
Merge pull request #1614 from MISL-EBU-System-SW/integration-fix

Fix service CPU image load at BL2 stage and update maintainers list

6 years agoMerge pull request #1612 from antonio-nino-diaz-arm/an/tools
Soby Mathew [Wed, 10 Oct 2018 13:00:14 +0000 (14:00 +0100)]
Merge pull request #1612 from antonio-nino-diaz-arm/an/tools

tools: Make invocation of host compiler correct

6 years agoMerge pull request #1607 from girishpathak/gp/346_sgm775_earlylog_fix_v2
Soby Mathew [Wed, 10 Oct 2018 12:59:47 +0000 (13:59 +0100)]
Merge pull request #1607 from girishpathak/gp/346_sgm775_earlylog_fix_v2

plat/arm/css/sgm: Reorder early platform init

6 years agoMerge pull request #1489 from teknoraver/master
Soby Mathew [Wed, 10 Oct 2018 12:58:23 +0000 (13:58 +0100)]
Merge pull request #1489 from teknoraver/master

doimage: get rid of non null terminated strings by strncpy

6 years agodrivers: imx: mxc_usdhc: Do not set MMC_RSP_48 for MMC_RESPONSE_R2
Bryan O'Donoghue [Wed, 10 Oct 2018 11:08:33 +0000 (12:08 +0100)]
drivers: imx: mxc_usdhc: Do not set MMC_RSP_48 for MMC_RESPONSE_R2

commit 97d5db8c5cb95c7ce69ff4d36bcda2aeda143576 reverts an update to the
MMC layer that accompanied the original submission of this MMC driver this
is the right-thing-to-do in terms of the MMC spec.

Unfortunately the reversion also breaks this driver. The issue is the i.MX
controller doesn't want MMC_RSP_48 set for MMC_RESPONSE_R2.

The appropriate place to place that constraint is obviously in
drivers/imx/usdhc/imx_usdhc.c not in the shared MMC codebase. This patch
restores the logic the i.MX controller requires without breaking it for
everyone else.

Fixes: 97d5db8c5cb95c7ce69ff4d36bcda2aeda143576
Fixes: 2a82a9c95f6c06079f58d69315544a6b49cf64a4
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Cc: Jun Nie <jun.nie@linaro.org>
6 years agoFix typos in changelog
John Tsichritzis [Fri, 5 Oct 2018 13:16:26 +0000 (14:16 +0100)]
Fix typos in changelog

Change-Id: Icc6fb03abb9b4ef85931b9e3d767b5a9c271b5f3
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
6 years agodocs: Clarify usage of LOG_LEVEL
John Tsichritzis [Fri, 5 Oct 2018 11:02:29 +0000 (12:02 +0100)]
docs: Clarify usage of LOG_LEVEL

Change-Id: I1ce771a155e6e83885a00d2f05591bf98cd69854
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
6 years agoReplace S-EL3 references by EL3
John Tsichritzis [Fri, 14 Sep 2018 09:34:57 +0000 (10:34 +0100)]
Replace S-EL3 references by EL3

The "Secure" prefix (S-ELx) is valid only for S-EL0 and S-EL1 but is
meaningless for EL3, since EL3 is always secure. Hence, the "S" prefix
has been removed from wherever it was used as "S-EL3".

Change-Id: Icdeac9506d763f9f83d7297c7113aec7b85e9dbe
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
6 years agoReorder log level macro definitions for clarity
John Tsichritzis [Fri, 7 Sep 2018 13:42:09 +0000 (14:42 +0100)]
Reorder log level macro definitions for clarity

The definitions of the logging macros are reordered to be consistent
with the definitions of the log levels.

Change-Id: I6ff07b93eb64786ff147d39014d1c8e15db28444
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
6 years agoplat/arm/css/sgm: Reorder early platform init
Girish Pathak [Tue, 2 Oct 2018 14:18:34 +0000 (15:18 +0100)]
plat/arm/css/sgm: Reorder early platform init

In the function, bl1_early_platform_setup in the file
plat/arm/css/sgm/sgm_bl1_setup.c:

  plat_config_init();

  arm_bl1_early_platform_setup();

The debug messages logged by plat_config_init() are lost because
the console is initialized in the function
arm_bl1_early_platform_setup()

To see the logs of plat_config_init, this fix re-orders above calls
so that the console is initialized before call to plat_config_init.

Change-Id: I2e98f1f67c591cca24e28905acd0838ea3697a7c
Signed-off-by: Girish Pathak <girish.pathak@arm.com>
6 years agoMerge pull request #1618 from satheesbalya-arm/sb1_2601_misra_smc_pwr
Soby Mathew [Wed, 10 Oct 2018 10:35:28 +0000 (11:35 +0100)]
Merge pull request #1618 from satheesbalya-arm/sb1_2601_misra_smc_pwr

Fix misra warnings in SMC and power mgmt code

6 years agoplat/arm: Move norflash driver to drivers/ folder
Antonio Nino Diaz [Wed, 10 Oct 2018 10:14:44 +0000 (11:14 +0100)]
plat/arm: Move norflash driver to drivers/ folder

This way it can be reused by other platforms if needed.

Note that this driver is designed to work with the Versatile Express NOR
flash of Juno and FVP. In said platforms, the memory is organized as an
interleaved memory of two chips with a 16 bit word.

Any platform that wishes to reuse it with a different configuration will
need to modify the driver so that it is more generic.

Change-Id: Ic721758425864e0cf42b7b9b04bf0d9513b6022e
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
6 years agoplat/arm: allow RESET_TO_BL31 for CSS-based platforms
Deepak Pandey [Fri, 25 May 2018 07:13:30 +0000 (12:43 +0530)]
plat/arm: allow RESET_TO_BL31 for CSS-based platforms

This lets any future CSS platforms to use RESET_TO_BL31 flag.

Change-Id: I32a90fce43cb0c6f4d33589653a0fd6a7ecc9577
Signed-off-by: Deepak Pandey <Deepak.Pandey@arm.com>
6 years agoFix misra warnings in SMC and power mgmt code
Sathees Balya [Fri, 5 Oct 2018 12:30:59 +0000 (13:30 +0100)]
Fix misra warnings in SMC and power mgmt code

Change-Id: Ia00eba2b18804e6498d935d33ec104953e0e5e03
Signed-off-by: Sathees Balya <sathees.balya@arm.com>
6 years agoMerge pull request #1617 from antonio-nino-diaz-arm/an/bugfix
Dimitris Papastamos [Mon, 8 Oct 2018 16:34:59 +0000 (17:34 +0100)]
Merge pull request #1617 from antonio-nino-diaz-arm/an/bugfix

xlat: Fix checks in mmap_add() and mmap_add_ctx()

6 years agoxlat: Fix checks in mmap_add() and mmap_add_ctx()
Antonio Nino Diaz [Mon, 8 Oct 2018 15:11:11 +0000 (16:11 +0100)]
xlat: Fix checks in mmap_add() and mmap_add_ctx()

Commit 79621f0038b789de23ecc8891024f7cf6aa65999 broke sgi575.

It is possible to have a region with 0 as value for the attributes. It
means device memory, read only, secure, executable. This is legitimate
if the code is in flash and the code is executed from there.

This is the case for SGI_MAP_FLASH0_RO, defined in the file
plat/arm/css/sgi/sgi_plat.c.

This problem is solved by checking both size and attributes in xlat v1.
In xlat v2, it is enough to check the granularity, as it can never be 0.

Change-Id: I7be11f1b0e51c4c2ffd560b4a6cdfbf15de2c276
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
6 years agoMakefile: Support totally quiet output with -s
Andre Przywara [Thu, 27 Sep 2018 09:56:05 +0000 (10:56 +0100)]
Makefile: Support totally quiet output with -s

"-s" is a command line option to the make tool, to suppress normal output,
something to the effect of prepending every line with '@' in the Makefile.
However with our V={0|1} support, we now print the shortened command line
output in any case (even with V=1, in addition to the long line!).
Normally -s helps to not miss non-fatal warnings, which tend to scroll out
of the window easily.

Introduce a new Makefile variable ECHO, to control the shortened output.
We only set it in the (current default) V=0 case, and replace every
occurence of "@echo" with that variable.
When the user specifies "-s", we set ECHO to some magic string which
changes the output line into a comment, so the output is suppressed.

Beside suppressing every output for "-s", we also avoid the redundant
short output when compiling with V=1.

This changes the output to:
==========
$ make -s PLAT=.... bl31

Built build/.../release/bl31.bin

==========
$ make PLAT=.... bl31
...
  CC      lib/libc/strncmp.c
  CC      lib/libc/strnlen.c
...
==========
$ make V=1 PLAT=.... bl31
...
gcc -DDEBUG=0 .... -o build/.../release/libc/strncmp.o
gcc -DDEBUG=0 .... -o build/.../release/libc/strnlen.o
...
==========

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
6 years agoplat: marvell: invoke platform specific scp_bl2 image handler
Grzegorz Jaszczyk [Thu, 4 Oct 2018 07:44:56 +0000 (09:44 +0200)]
plat: marvell: invoke platform specific scp_bl2 image handler

Before switching to new API the scp_bl2 handler was invoked from
bl2/bl2_image_load.c which was removed. Invoke the platform specific
scp_bl2 handler in analogy to ARM and HiSilicon.

Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
6 years agoadd Marvell tools to maintained sources list
Konstantin Porotchkin [Sun, 7 Oct 2018 09:21:31 +0000 (12:21 +0300)]
add Marvell tools to maintained sources list

Declate Marvell's ownership on tools/doimage

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
6 years agoMerge pull request #1611 from antonio-nino-diaz-arm/an/misra-common
Dimitris Papastamos [Thu, 4 Oct 2018 15:46:53 +0000 (16:46 +0100)]
Merge pull request #1611 from antonio-nino-diaz-arm/an/misra-common

Remove some MISRA defects in common code

6 years agoMerge pull request #1610 from sandrine-bailleux-arm/sb/fix-makefile
Dimitris Papastamos [Thu, 4 Oct 2018 15:45:40 +0000 (16:45 +0100)]
Merge pull request #1610 from sandrine-bailleux-arm/sb/fix-makefile

Remove incorrect tabulation in Makefile

6 years agoMerge pull request #1583 from danielboulby-arm/db/AArch32_Multi_Console
Dimitris Papastamos [Thu, 4 Oct 2018 15:43:39 +0000 (16:43 +0100)]
Merge pull request #1583 from danielboulby-arm/db/AArch32_Multi_Console

Enable Multi Console API in AArch32

6 years agoRemove some MISRA defects in common code
Antonio Nino Diaz [Thu, 4 Oct 2018 08:55:23 +0000 (09:55 +0100)]
Remove some MISRA defects in common code

No functional changes.

Change-Id: I9638e02acb9b22eb794ebf45aad84348a710287e
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
6 years agoMerge pull request #1595 from Yann-lms/dts_dep
Soby Mathew [Thu, 4 Oct 2018 14:23:09 +0000 (15:23 +0100)]
Merge pull request #1595 from Yann-lms/dts_dep

MAKE_DTB: dependencies on device tree source files

6 years agotools: Make invocation of host compiler correct
Antonio Nino Diaz [Thu, 4 Oct 2018 13:35:38 +0000 (14:35 +0100)]
tools: Make invocation of host compiler correct

HOSTCC should be used in any of the tools inside the tools/ directory
instead of CC. That way it is possible to override both values from the
command line when building the Trusted Firmware and the tools at the
same time. Also, use HOSTCCFLAGS instead of CFLAGS.

Also, instead of printing the strings CC and LD in the console during
the compilation of the tools, HOSTCC and HOSTLD have to be used for
clarity. This is how it is done in other projects like U-Boot or Linux.

Change-Id: Icd6f74c31eb74cdd1c353583399ab19e173e293e
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
6 years agoMerge pull request #1609 from MISL-EBU-System-SW/integration-ble
Soby Mathew [Thu, 4 Oct 2018 13:31:58 +0000 (14:31 +0100)]
Merge pull request #1609 from MISL-EBU-System-SW/integration-ble

plat/marvell: Move BLE into the platform tree, minor fix in tools.

6 years agoMerge pull request #1603 from antonio-nino-diaz-arm/db/reclaim-init
Soby Mathew [Thu, 4 Oct 2018 13:23:31 +0000 (14:23 +0100)]
Merge pull request #1603 from antonio-nino-diaz-arm/db/reclaim-init

 Reclaim BL31 initialization code memory for runtime data

6 years agoMerge pull request #1608 from npoushin/integration
Soby Mathew [Wed, 3 Oct 2018 14:38:12 +0000 (15:38 +0100)]
Merge pull request #1608 from npoushin/integration

maintainers: Correct github username for nariman to npoushin

6 years agoMerge pull request #1584 from danielboulby-arm/db/Switches
Soby Mathew [Wed, 3 Oct 2018 14:36:37 +0000 (15:36 +0100)]
Merge pull request #1584 from danielboulby-arm/db/Switches

Ensure the flow through switch statements is clear

6 years agoRemove incorrect tabulation in Makefile
Sandrine Bailleux [Wed, 3 Oct 2018 12:56:38 +0000 (14:56 +0200)]
Remove incorrect tabulation in Makefile

When attempting to compile TF-A with "SPD=something ARCH=aarch32", the
following error message is printed:

 Makefile:291: *** recipe commences before first target.  Stop.

This is because the call to the error function is indented using a tab
whereas it's not part of a rule's recipe. Replace the tab by spaces.

Change-Id: Ic9b603837a0e43f2f7070cb39137541c332365d2
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
6 years agotools: Fix broken object compilation rules
Jan Kiszka [Tue, 2 Oct 2018 07:28:00 +0000 (09:28 +0200)]
tools: Fix broken object compilation rules

As these rules depend on non-existing headers as well (likely copy &
pasted from fiptool), they never matched, and the built-in rules were
used. That led to random breakages when e.g. CPPFLAGS was suddenly
evaluated and contained invalid options.

For the stm32image, this reveals that we were relying on the built-in
rules by passing -D_GNU_SOURCE via CPPFLAGS, rather than using CFLAGS as
used in the local rule. Fix that as well.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
6 years agomarvell: Move BLE from external repo to the platform folder
Konstantin Porotchkin [Wed, 3 Oct 2018 11:21:42 +0000 (14:21 +0300)]
marvell: Move BLE from external repo to the platform folder

The BLE is the pre-TF-A boot stage required by Marvell Armada
BootROM for bringing up DRAM and allow the boot image copy to it.
Since this is not a standard boot level and only uses the TF-A
as a build environment, it was introduced out of source tree.
However it turns out that such remote location introduces additional
complexity to the upstream TF-A build process.
In order to simplify the build environment the BLE source folder
is relocated from the external repository to A8K platform directory.
The build documentation is updated accordingly.

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
6 years agoFVP: Reclaim init code for the stack
Daniel Boulby [Tue, 18 Sep 2018 10:52:49 +0000 (11:52 +0100)]
FVP: Reclaim init code for the stack

Map the initialization code for BL31 to overlap with the memory
required for the secondary cores stack. Once BL31 has been
initialized the memory can be remapped to RW data so that it can
be used for secondary cores stacks. By moving code from .text to
.text.init the size of the BL31 image is decreased by a page.

Split arm_common.ld.S into two linker scripts, one for tzc_dram
(arm_tzc_dram.ld.S) and one for reclaiming initialization code
(arm_reclaim_init.ld.S) so that platforms can chose which memory
regions they wish to include.

Change-Id: I648e88f3eda1aa71765744cf34343ecda9320b32
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
6 years agomaintainers: Correct github username for nariman to npoushin
Nariman Poushin [Wed, 3 Oct 2018 11:03:42 +0000 (12:03 +0100)]
maintainers: Correct github username for nariman to npoushin

Signed-off-by: Nariman Poushin <nariman.poushin@linaro.org>
6 years agoMark GICV3, CCI and CCN boot time code as init
Daniel Boulby [Tue, 18 Sep 2018 12:36:39 +0000 (13:36 +0100)]
Mark GICV3, CCI and CCN boot time code as init

Mark the GICv3, CCI and CCN code only used in Bl31 initialization
with __init to be reclaimed once no longer needed.

Change-Id: I3d77f36758450d9d1d87ecc60bc1c63fe4082667
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>