Victor Chong [Sat, 27 May 2017 15:14:25 +0000 (00:14 +0900)]
hikey: Add BL32 (OP-TEE) support
Signed-off-by: Victor Chong <victor.chong@linaro.org>
Victor Chong [Sat, 27 May 2017 15:14:25 +0000 (00:14 +0900)]
hikey: Remove unnecessary code
PLATFORM_LINKER_FORMAT
and
PLATFORM_LINKER_ARCH
defines are removed from
plat/hisilicon/hikey/include/platform_def.h
since there are already defined in
include/plat/common/common_def.h
which is included by
plat/hisilicon/hikey/hikey_def.h
which is included by
plat/hisilicon/hikey/include/platform_def.h
The line
$(eval $(call FIP_ADD_IMG,SCP_BL2,--scp-fw))
is removed from
plat/hisilicon/hikey/platform.mk
to clear the warning below:
Makefile:544: warning: overriding commands for target `check_SCP_BL2'
plat/hisilicon/hikey/platform.mk:19: warning: ignoring old commands for target `check_SCP_BL2'
$(eval $(call FIP_ADD_IMG,SCP_BL2,--scp-fw))
already exists in
Makefile
and applies to plat hikey so is redundant in
plat/hisilicon/hikey/platform.mk
Signed-off-by: Victor Chong <victor.chong@linaro.org>
Victor Chong [Wed, 12 Jul 2017 07:13:43 +0000 (16:13 +0900)]
hikey: Fix errors in doc
Signed-off-by: Victor Chong <victor.chong@linaro.org>
Victor Chong [Wed, 12 Jul 2017 07:27:51 +0000 (16:27 +0900)]
hikey: Fix DDR_SIZE
Signed-off-by: Victor Chong <victor.chong@linaro.org>
davidcunado-arm [Mon, 10 Jul 2017 19:52:09 +0000 (20:52 +0100)]
Merge pull request #1016 from Xilinx/dup-const
zynqmp: Remove duplicate 'const' declaration
davidcunado-arm [Mon, 10 Jul 2017 17:37:18 +0000 (18:37 +0100)]
Merge pull request #1012 from rockchip-linux/rk3399/l2cache
rockchip/rk3399: fixes the typo and the WARNINGS during suspend/resume
davidcunado-arm [Mon, 10 Jul 2017 15:37:48 +0000 (16:37 +0100)]
Merge pull request #993 from rockchip-linux/hdcp-rk3399
rockchip: support to use hdcp for rk3399
Haojian Zhuang [Fri, 30 Jun 2017 08:21:54 +0000 (16:21 +0800)]
hikey: enable options to fix errata
Fix cortex a53 errata issues: #836870, #843419, #855873.
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
davidcunado-arm [Fri, 7 Jul 2017 21:12:10 +0000 (22:12 +0100)]
Merge pull request #1025 from davidcunado-arm/dc/version_update
Release v1.4: Update minor version number to 4
davidcunado-arm [Fri, 7 Jul 2017 21:11:45 +0000 (22:11 +0100)]
Merge pull request #1026 from eleanorbonnici-arm/eb/OoB_test
Updates user guide following out of box testing.
Eleanor Bonnici [Fri, 7 Jul 2017 13:33:24 +0000 (14:33 +0100)]
Updates user guide following out of box testing.
Change-Id: I0cd355d9fc7f14fb4eabb443d596d6f0858f609e
Signed-off-by: Eleanor Bonnici <Eleanor.bonnici@arm.com>
davidcunado-arm [Thu, 6 Jul 2017 17:42:37 +0000 (18:42 +0100)]
Merge pull request #1022 from danh-arm/dh/v1.4-readme
Update readme for v1.4 release
David Cunado [Thu, 6 Jul 2017 16:50:47 +0000 (17:50 +0100)]
Release v1.4: Update minor version number to 4
Change-Id: I8676a22649dce92d0ddd98013fc6dafcfbe94c90
Signed-off-by: David Cunado <david.cunado@arm.com>
davidcunado-arm [Thu, 6 Jul 2017 17:07:35 +0000 (18:07 +0100)]
Merge pull request #1024 from davidcunado-arm/dc/update_userguide
Release v1.4: update change-log.rst
David Cunado [Mon, 3 Jul 2017 17:59:07 +0000 (18:59 +0100)]
Release v1.4: update change-log.rst
Updated change-log.rst with summary of changes since release v1.3.
Change-Id: Iecd31ed315bd9ad7ffe8bce6550f7c90e1e3a9b0
Signed-off-by: David Cunado <david.cunado@arm.com>
davidcunado-arm [Thu, 6 Jul 2017 14:25:15 +0000 (15:25 +0100)]
Merge pull request #1023 from davidcunado-arm/dc/update_userguide
Migrate to Linaro release 17.04
David Cunado [Thu, 29 Jun 2017 11:01:33 +0000 (12:01 +0100)]
Migrate to Linaro release 17.04
ARM TF has been tested against Linaro Release 17.04 - the Linaro
binaries have been update and also the version of the compiler.
Linaro binaries: 17.01 --> 17.04
AArch64 & AArch32 compilers: 5.3-2015.05 (gcc 5.3) -> 6.2-2016.11 (gcc 6.2)
This patch updates the User Guide is to state that Linaro
release 17.04 is supported.
Additionally, the following fixes are made to the User Guide:
- Removed out of date reference to Linaro release 16.06.
- Updated the Juno variant coverage to include r2.
Change-Id: Iebbced3356f8c6b3c2bff2df62574db9f937ca7b
Signed-off-by: David Cunado <david.cunado@arm.com>
davidcunado-arm [Thu, 6 Jul 2017 13:03:26 +0000 (14:03 +0100)]
Merge pull request #1010 from davidcunado-arm/dc/update_userguide
Update Foundation, AEM and Cortex Models versions
Dan Handley [Wed, 5 Jul 2017 16:40:29 +0000 (17:40 +0100)]
Update readme for v1.4 release
Update the release notes (readme.rst) for the ARM Trusted Firmware v1.4 release.
Also, reorder and fix some of the links following the conversion to
reStructured text format.
Change-Id: I8f5e8aa86cb891f61b6b62cf9fab0ad0f0ebb36b
Signed-off-by: Dan Handley <dan.handley@arm.com>
David Cunado [Tue, 27 Jun 2017 16:31:12 +0000 (17:31 +0100)]
Update Foundation, AEM and Cortex Models versions
Trusted Firmware has been tested as part of its CI system against Cortex
and Foundation models in the 11.0 Model release available on
developer.arm.com. Trusted Firmware has also been tested against the v8.5
AEM model.
This patch updates the user guide documentation to reflect the version of
the Foundation, AEM and Cortex Models that Trusted Firmware has been
tested against.
Change-Id: I3b5b4d1e4220bda1dcc88aa9cfa01fa711ed92cd
Signed-off-by: David Cunado <david.cunado@arm.com>
danh-arm [Wed, 5 Jul 2017 11:27:34 +0000 (12:27 +0100)]
Merge pull request #1011 from douglas-raillard-arm/dr/doc_convert_to_rst
Convert Markdown to reStructuredText
Ziyuan Xu [Fri, 10 Feb 2017 03:54:52 +0000 (11:54 +0800)]
rockchip: implement hdcp key decryption feature for rk3399
Decrypt device private keys which transfer from kernel, then stuff it to
DP controller. So that DP driver could start HDCP authentication in
kernel.
Change-Id: If3c2cd99bca811fe5fc30acc88bf5dc1afd7416d
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Soren Brinkmann [Sun, 2 Jul 2017 03:24:47 +0000 (20:24 -0700)]
zynqmp: Remove duplicate 'const' declaration
Fixing compilation errors due to duplicate 'const' keyword:
plat/xilinx/zynqmp/pm_service/pm_client.c:39:29: error: duplicate 'const' declaration specifier [-Werror=duplicate-decl-specifier]
static const struct pm_proc const pm_procs_all[] = {
^~~~~
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Caesar Wang [Mon, 19 Jun 2017 06:02:52 +0000 (14:02 +0800)]
rockchip/rk3399: fixes the typo and the WARNINGS during suspend/resume
This patch fixes the two things as follows:
1) rk3399_flash_l2_b" seems to be a typo. That's "flush", not "flash".
2) fixes the warnings log.
We always hit the warnings thing during the suspend, as below log:
..
[ 51.022334] CPU5: shutdown
[ 51.025069] psci: CPU5 killed.
INFO: sdram_params->ddr_freq =
928000000
WARNING: rk3399_flash_l2_b:reg
28830380,wait
When the L2 completes the clean and invalidate sequence, it asserts the
L2FLUSHDONE signal. The SoC can now deassert L2FLUSHREQ signal and then
the L2 deasserts L2FLUSHDONE.
Then, a loop without a delay isn't really great to measure time. We should
probably add a udelay(10) or so in there and then maybe replace the WARN()
after the loop. In the actual tests, the L2 cache will take ~4ms by
default for big cluster.
In the real world that give 10ms for the enough margin, like the
ddr/cpu/cci frequency and other factors that will affect it.
Change-Id: I55788c897be232bf72e8c7b0e10cf9b06f7aa50d
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Douglas Raillard [Thu, 29 Jun 2017 15:22:45 +0000 (16:22 +0100)]
Remove Markdown documentation
Removed Markdown documents as they have been converted to
reStructuredText.
Change-Id: I3148222eb31258f158f64de4ddcdda4b232ce483
Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>
Douglas Raillard [Wed, 28 Jun 2017 15:14:55 +0000 (16:14 +0100)]
Manual fixes to reST documentations
Non-automated fixes to the converted documentation.
Change-Id: I61f3d37c7a8d6a56a7351048060b970c5b3751e4
Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>
Douglas Raillard [Wed, 28 Jun 2017 14:23:03 +0000 (15:23 +0100)]
Convert documentation to reStructuredText
Due to recent issues in the rendering of the documentation on GitHub and
some long-standing issues like the lack of automatic table of content in
Markdown, the documentation has been converted to reStructuredText.
Basic constructs looks pretty similar to Markdown.
Automatically convert GitHub markdown documentation to reStructuredText
using pandoc.
Change-Id: If20b695acedc6d1b49c8d9fb64efd6b6ba23f4a9
Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>
Douglas Raillard [Tue, 20 Jun 2017 14:22:19 +0000 (15:22 +0100)]
Fix various small issues in the documentation
Change some hard-to-convert constructs to cleaner ones.
Fix a broken link.
Change-Id: Ida70aa1da0af7a107b0e05eb20b8d46669a0380b
Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>
danh-arm [Wed, 28 Jun 2017 15:29:55 +0000 (16:29 +0100)]
Merge pull request #1007 from soby-mathew/sm/ccint
Enable integration of ARM TrustZone Cryptocell for TBB
Soby Mathew [Fri, 2 Jun 2017 16:44:07 +0000 (17:44 +0100)]
Use CryptoCell to set/get NVcounters and ROTPK
This patch implements the platform APIs plat_get_rotpk_info,
plat_get_nv_ctr, plat_set_nv_ctr to invoke CryptoCell SBROM
APIs when ARM_CRYPTOCELL_INT is set.
Change-Id: I693556b3c7f42eceddd527abbe6111e499f55c45
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
Soby Mathew [Mon, 5 Jun 2017 14:55:59 +0000 (15:55 +0100)]
Do basic CryptoCell LCS check
This patch implements the basic lifecycle state check when CryptoCell
SBROM is initialized. Currently the check ensures that if the lifecycle
state is Security Disabled (SD), the boot process does not proceed
further.
Change-Id: I5101335453cd3ea413e97bcfb9138a96c05e1aea
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
Soby Mathew [Wed, 10 May 2017 10:50:30 +0000 (11:50 +0100)]
ARM plat changes to enable CryptoCell integration
This patch makes the necessary changes to enable ARM platform to
successfully integrate CryptoCell during Trusted Board Boot. The
changes are as follows:
* A new build option `ARM_CRYPTOCELL_INTEG` is introduced to select
the CryptoCell crypto driver for Trusted Board boot.
* The TrustZone filter settings for Non Secure DRAM is modified
to allow CryptoCell to read this memory. This is required to
authenticate BL33 which is loaded into the Non Secure DDR.
* The CSS platforms are modified to use coherent stacks in BL1 and BL2
when CryptoCell crypto is selected. This is because CryptoCell makes
use of DMA to transfer data and the CryptoCell SBROM library allocates
buffers on the stack during signature/hash verification.
Change-Id: I1e6f6dcd1899784f1edeabfa2a9f279bbfb90e31
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
Soby Mathew [Wed, 10 May 2017 10:49:58 +0000 (11:49 +0100)]
Add CC crypto driver to the Auth module
This patch adds a crypto driver which utilizes the ARM® TrustZone®
CryptoCell-712 to verify signature and hash during Trusted Board Boot. Along
with this driver, the CryptoCell SBROM library is required to successfully
build the BL image. The path to this library is specified via
the `CCSBROM_LIB_PATH` variable. Please note that, mbedTLS is still required
to do the X509 certificate ASN.1 parsing and CryptoCell is only utilized for
signature and hash verification.
Change-Id: If82dfbae0d7772ba1c64839f0b27850c103fe253
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
Soby Mathew [Wed, 10 May 2017 10:48:40 +0000 (11:48 +0100)]
Add headers to enable CryptoCell integration
This patch adds header files with required declarations and
macro definitions to enable integration with CryptoCell SBROM
version `CC712 – Release 1.0.0.1061`. These headers enable ARM
Trusted Firmware to build and link with CryptoCell SBROM
library.
Change-Id: I501eda7fe1429acb61db8e1cab78cc9aee9c1871
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
Soby Mathew [Wed, 10 May 2017 10:48:04 +0000 (11:48 +0100)]
Add support to link an external lib with ARM TF
This patch defines the variable `LDLIBS` which allows external
libraries to be specified to 'ld' to enable it to link the
libraries.
Change-Id: I02a490eca1074063d00153ccb0ee974ef8859a0e
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
danh-arm [Wed, 28 Jun 2017 14:50:20 +0000 (15:50 +0100)]
Merge pull request #1008 from douglas-raillard-arm/dr/add_TF_LDFLAGS
Introduce TF_LDFLAGS and improve CFLAGS documentation
Douglas Raillard [Thu, 22 Jun 2017 14:03:50 +0000 (15:03 +0100)]
Document CFLAGS make option
CFLAGS content can be set on the command line to allow passing extra
options to the compiler. Its content is appended after the options set
by the Makefile (TF_CFLAGS).
The Makefiles must use TF_CFLAGS instead of CFLAGS, as the latter can be
completely overriden by setting it on the command line.
Also tell about LDFLAGS in the "Debugging options" section.
Change-Id: Iaf27b424002898ef3040133f78cb133983a37aee
Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>
Douglas Raillard [Thu, 22 Jun 2017 13:44:48 +0000 (14:44 +0100)]
Introduce TF_LDFLAGS
Use TF_LDFLAGS from the Makefiles, and still append LDFLAGS as well to
the compiler's invocation. This allows passing extra options from the
make command line using LDFLAGS.
Document new LDFLAGS Makefile option.
Change-Id: I88c5ac26ca12ac2b2d60a6f150ae027639991f27
Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>
danh-arm [Wed, 28 Jun 2017 13:51:37 +0000 (14:51 +0100)]
Merge pull request #1009 from islmit01/im/aarch32_juno
Add Juno AArch32 and AArch64 User Guide instructions
Isla Mitchell [Mon, 26 Jun 2017 13:25:44 +0000 (14:25 +0100)]
Add Juno AArch32 and AArch64 User Guide instructions
Updated section 6, building a FIP for Juno and FVP, adding
instructions for AArch32 and AArch64.
Updated section 4.1, summary of build options, to include a
description of the `JUNO_AARCH32_EL3_RUNTIME` build flag.
Change-Id: I4ed006522cab981371c382859063f088fbfcb8f7
Signed-off-by: Isla Mitchell <isla.mitchell@arm.com>
danh-arm [Wed, 28 Jun 2017 12:48:31 +0000 (13:48 +0100)]
Merge pull request #1006 from robertovargas-arm/doc-format
Improve format of exception vectors in BL1 description
danh-arm [Wed, 28 Jun 2017 12:48:14 +0000 (13:48 +0100)]
Merge pull request #1004 from rockchip-linux/erratum-rk3399
rockchip: enable A53's erratum 855873 for rk3399
danh-arm [Wed, 28 Jun 2017 12:47:57 +0000 (13:47 +0100)]
Merge pull request #1003 from douglas-raillard-arm/dr/doc_fix_broken_link
Fix broken link in documentation
danh-arm [Wed, 28 Jun 2017 12:47:40 +0000 (13:47 +0100)]
Merge pull request #1002 from douglas-raillard-arm/dr/fix_errata_a53
Apply workarounds for A53 Cat A Errata 835769 and 843419
danh-arm [Wed, 28 Jun 2017 12:46:46 +0000 (13:46 +0100)]
Merge pull request #1001 from davidcunado-arm/dc/fix-signed-comparisons
Resolve signed-unsigned comparison issues
danh-arm [Wed, 28 Jun 2017 12:46:19 +0000 (13:46 +0100)]
Merge pull request #978 from etienne-lms/minor-build
Minor build fixes
Roberto Vargas [Mon, 19 Jun 2017 08:39:09 +0000 (09:39 +0100)]
Improve format of exception vectors in BL1 description
Without the additional newlines all the text becomes a single paragraph
and next newlines are ignored.
Change-Id: I783198477f654e3923fcabb21248f2bc62c33e9d
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
Caesar Wang [Wed, 28 Jun 2017 00:40:26 +0000 (08:40 +0800)]
rockchip: enable A53's erratum 855873 for rk3399
For rk3399, the L2ACTLR[14] is 0 by default, as ACE CCI-500 doesn't
support WriteEvict. and you will hit the condition L2ACTLR[3] with 0,
as the Evict transactions should propagate to CCI-500 since it has
snoop filters.
Maybe this erratum applies to all Cortex-A53 cores so far, especially
if RK3399's A53 is a r0p4. we should enable it to avoid data corruption,
Change-Id: Ib86933f1fc84f8919c8e43dac41af60fd0c3ce2f
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
davidcunado-arm [Tue, 27 Jun 2017 22:10:47 +0000 (23:10 +0100)]
Merge pull request #1000 from dp-arm/dp/aarch32-boot
juno/aarch32: Fix boot on Cortex A57 and A72
Douglas Raillard [Thu, 22 Jun 2017 14:36:02 +0000 (15:36 +0100)]
Fix broken link in documentation
Fix link in docs/firmware-update.md and docs/change-log.md:
https://github.com/ARM-software/arm-trusted-firmware/wiki/ARM-Trusted-Firmware-Image-Terminology
Change-Id: I2d51d373fd0f7da59b548cd6bed52c47772014fd
Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>
David Cunado [Wed, 21 Jun 2017 15:52:45 +0000 (16:52 +0100)]
Resolve signed-unsigned comparison issues
A recent commit
030567e6f51731982a7e71cbd387de93bc0e35fd added U()/ULL()
macro to TF constants. This has caused some signed-unsigned comparison
warnings / errors in the TF static analysis.
This patch addresses these issues by migrating impacted variables from
signed ints to unsigned ints and vice verse where applicable.
Change-Id: I4b4c739a3fa64aaf13b69ad1702c66ec79247e53
Signed-off-by: David Cunado <david.cunado@arm.com>
davidcunado-arm [Tue, 27 Jun 2017 08:51:56 +0000 (09:51 +0100)]
Merge pull request #999 from douglas-raillard-arm/dr/fix_tegra_CFLAGS
Fix Tegra CFLAGS usage
Dimitris Papastamos [Mon, 19 Jun 2017 13:15:31 +0000 (14:15 +0100)]
juno: Invalidate all caches before warm reset to AArch32 state.
On Juno AArch32, the L2 cache may contain garbage after the warm reset
from AArch64 to AArch32. This is all fine until the MMU is configured
and the data caches enabled. To avoid fetching stale data from the L2
unified cache, invalidate it before the warm reset to AArch32 state.
Change-Id: I7d27e810692c02c3e83c9f31de67f6bae59a960a
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
Dimitris Papastamos [Wed, 14 Jun 2017 13:47:36 +0000 (14:47 +0100)]
juno/aarch32: Restore `SCP_BOOT_CFG_ADDR` to the cold boot value
Before BL2 loads the SCP ram firmware, `SCP_BOOT_CFG_ADDR` specifies
the primary core. After the SCP ram firmware has started executing,
`SCP_BOOT_CFG_ADDR` is modified. This is not normally an issue but
the Juno AArch32 boot flow is a special case. BL1 does a warm reset
into AArch32 and the core jumps to the `sp_min` entrypoint. This is
effectively a `RESET_TO_SP_MIN` configuration. `sp_min` has to be
able to determine the primary core and hence we need to restore
`SCP_BOOT_CFG_ADDR` to the cold boot value before `sp_min` runs.
This magically worked when booting on A53 because the core index was
zero and it just so happened to match with the new value in
`SCP_BOOT_CFG_ADDR`.
Change-Id: I105425c680cf6238948625c1d1017b01d3517c01
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
Ziyuan Xu [Thu, 27 Oct 2016 11:07:35 +0000 (19:07 +0800)]
rockchip: include hdcp.bin and declare hdcp key decryption handler
For some reason, HDCP key decrytion can't open source in ATF, so we
build it as hdcp.bin. Besides declare the handler for decrypting.
Change-Id: Ia67ff2442ab43cb3ee4875b3d59cc1608e854b4b
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
davidcunado-arm [Mon, 26 Jun 2017 08:54:24 +0000 (09:54 +0100)]
Merge pull request #994 from soby-mathew/sm/fwu_fix
Fix FWU and cache helper optimization
davidcunado-arm [Fri, 23 Jun 2017 13:42:06 +0000 (14:42 +0100)]
Merge pull request #976 from etienne-lms/minor-psci
psci: minor fixes in lib
davidcunado-arm [Fri, 23 Jun 2017 11:48:11 +0000 (12:48 +0100)]
Merge pull request #997 from dp-arm/dp/spe
aarch64: Enable Statistical Profiling Extensions for lower ELs
Douglas Raillard [Thu, 22 Jun 2017 13:47:01 +0000 (14:47 +0100)]
Fix Tegra CFLAGS usage
Use TF_CFLAGS instead of CFLAGS, to allow CFLAGS to be overriden from
the make command line.
Change-Id: I3e5726c04bcd0176f232581b8be2c94413374ac7
Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>
davidcunado-arm [Fri, 23 Jun 2017 07:39:19 +0000 (08:39 +0100)]
Merge pull request #995 from davidcunado-arm/dc/init_reg
Fully initialise essential control registers
Etienne Carriere [Wed, 7 Jun 2017 14:45:15 +0000 (16:45 +0200)]
io_dummy: correct sparse warnings
Include io_dummy.h header file.
Use static for device_type_dummy function.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Etienne Carriere [Wed, 7 Jun 2017 14:43:19 +0000 (16:43 +0200)]
io_storage: use unsigned int for index
This change avoids warning about type conversion.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Etienne Carriere [Wed, 7 Jun 2017 14:42:42 +0000 (16:42 +0200)]
PSCI: use same function prototype as in header file
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Etienne Carriere [Wed, 7 Jun 2017 14:42:26 +0000 (16:42 +0200)]
delay_timer: correct sparse issues and warnings
Use NULL instead of 0 where required.
Include headers to have the prototype of the functions.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Etienne Carriere [Wed, 7 Jun 2017 14:41:50 +0000 (16:41 +0200)]
bl1: include bl1_private.h in aarch* files
This change avoids warnings when setting -Wmissing-prototypes or when
using sparse tool.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Etienne Carriere [Fri, 23 Jun 2017 07:37:49 +0000 (09:37 +0200)]
context_mgmt: declare extern cm_set_next_context() for AArch32
This change avoids warning when setting -Wmissing-prototypes to
compile bl1_context_mgmt.c.
Reported-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Etienne Carriere [Wed, 7 Jun 2017 14:45:42 +0000 (16:45 +0200)]
bl: security_state should be of type unsigned int
security_state is either 0 or 1. Prevent sign conversion potential
error (setting -Werror=sign-conversion results in a build error).
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Etienne Carriere [Thu, 22 Jun 2017 20:10:32 +0000 (22:10 +0200)]
psci: minor fixes in lib
Call svc_suspend_finish if registered.
psci_get_stat() is static to psci_stat.c
Fix types used in comparison.
Fix coding style (empty line between variable definition and instructions
block).
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
davidcunado-arm [Thu, 22 Jun 2017 20:07:26 +0000 (21:07 +0100)]
Merge pull request #996 from dp-arm/dp/aarch32-813419
aarch32: Apply workaround for errata 813419 of Cortex-A57
Douglas Raillard [Mon, 19 Jun 2017 14:38:02 +0000 (15:38 +0100)]
Apply workarounds for A53 Cat A Errata 835769 and 843419
These errata are only applicable to AArch64 state. See the errata notice
for more details:
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.epm048406/index.html
Introduce the build options ERRATA_A53_835769 and ERRATA_A53_843419.
Enable both of them for Juno.
Apply the 835769 workaround as following:
* Compile with -mfix-cortex-a53-835769
* Link with --fix-cortex-a53-835769
Apply the 843419 workaround as following:
* Link with --fix-cortex-a53-843419
The erratum 843419 workaround can lead the linker to create new sections
suffixed with "*.stub*" and 4KB aligned. The erratum 835769 can lead the
linker to create new "*.stub" sections with no particular alignment.
Also add support for LDFLAGS_aarch32 and LDFLAGS_aarch64 in Makefile for
architecture-specific linker options.
Change-Id: Iab3337e338b7a0a16b0d102404d9db98c154f8f8
Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>
Dimitris Papastamos [Tue, 20 Jun 2017 08:25:10 +0000 (09:25 +0100)]
aarch32: Apply workaround for errata 813419 of Cortex-A57
TLBI instructions for monitor mode won't have the desired effect under
specific circumstances in Cortex-A57 r0p0. The workaround is to
execute DSB and TLBI twice each time.
Even though this errata is only needed in r0p0, the current errata
framework is not prepared to apply run-time workarounds. The current one
is always applied if compiled in, regardless of the CPU or its revision.
The `DSB` instruction used when initializing the translation tables has
been changed to `DSB ISH` as an optimization and to be consistent with
the barriers used for the workaround.
NOTE: This workaround is present in AArch64 TF and already enabled by
default on Juno.
Change-Id: I10b0baa304ed64b13b7b26ea766e61461e759dfa
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
davidcunado-arm [Thu, 22 Jun 2017 14:12:20 +0000 (15:12 +0100)]
Merge pull request #990 from masahir0y/uniphier
uniphier: embed ROTPK hash into BL1/BL2
davidcunado-arm [Thu, 22 Jun 2017 14:09:51 +0000 (15:09 +0100)]
Merge pull request #988 from Leo-Yan/fix_cpu_off_v1
plat: Hikey960: fix the CPU hotplug
dp-arm [Tue, 23 May 2017 08:32:49 +0000 (09:32 +0100)]
aarch64: Enable Statistical Profiling Extensions for lower ELs
SPE is only supported in non-secure state. Accesses to SPE specific
registers from SEL1 will trap to EL3. During a world switch, before
`TTBR` is modified the SPE profiling buffers are drained. This is to
avoid a potential invalid memory access in SEL1.
SPE is architecturally specified only for AArch64.
Change-Id: I04a96427d9f9d586c331913d815fdc726855f6b0
Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
David Cunado [Thu, 13 Apr 2017 21:38:29 +0000 (22:38 +0100)]
Fully initialise essential control registers
This patch updates the el3_arch_init_common macro so that it fully
initialises essential control registers rather then relying on hardware
to set the reset values.
The context management functions are also updated to fully initialise
the appropriate control registers when initialising the non-secure and
secure context structures and when preparing to leave EL3 for a lower
EL.
This gives better alignement with the ARM ARM which states that software
must initialise RES0 and RES1 fields with 0 / 1.
This patch also corrects the following typos:
"NASCR definitions" -> "NSACR definitions"
Change-Id: Ia8940b8351dc27bc09e2138b011e249655041cfc
Signed-off-by: David Cunado <david.cunado@arm.com>
Soby Mathew [Thu, 15 Jun 2017 15:18:45 +0000 (16:18 +0100)]
Exit early if size zero for cache helpers
This patch enables cache helper functions `flush_dcache_range`,
`clean_dcache_range` and `invalidate_dcache_range` to exit early
if the size argument specified is zero
Change-Id: I0b63e8f4bd3d47ec08bf2a0b0b9a7ff8a269a9b0
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
Soby Mathew [Thu, 15 Jun 2017 15:11:48 +0000 (16:11 +0100)]
Fix issues in FWU code
This patch fixes the following issues in Firmware Update (FWU) code:
1. The FWU layer maintains a list of loaded image ids and
while checking for image overlaps, INVALID_IMAGE_IDs were not
skipped. The patch now adds code to skip INVALID_IMAGE_IDs.
2. While resetting the state corresponding to an image, the code
now resets the memory used by the image only if the image were
copied previously via IMAGE_COPY smc. This prevents the invalid
zeroing of image memory which are not copied but are directly
authenticated via IMAGE_AUTH smc.
Change-Id: Idf18e69bcba7259411c88807bd0347d59d9afb8f
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
davidcunado-arm [Tue, 20 Jun 2017 21:05:48 +0000 (22:05 +0100)]
Merge pull request #983 from dp-arm/dp/aarch32-errata
aarch32: Implement errata workarounds for Cortex A53 and A57
Masahiro Yamada [Wed, 14 Jun 2017 11:38:12 +0000 (20:38 +0900)]
uniphier: embed ROTPK hash into BL1/BL2
Currently, ROTPK_NOT_DEPLOYED flag is set in plat_get_rotpk_info().
It is up to users how to retrieve ROTPK if the ROT verification is
desired. This is not nice.
This commit improves plat_get_rotpk_info() implementation and automates
the ROTPK deployment. UniPhier platform has no ROTPK storage, so it
should be embedded in BL1/BL2, like ARM_ROTPK_LOCATION=devel_rsa case.
This makes sense because UniPhier platform implements its internal ROM
i.e. BL1 is used as updatable pseudo ROM.
Things work like this:
- ROT_KEY (default: $(BUILD_PLAT)/rot_key.pem) is created if missing.
Users can override ROT_KEY from the command line if they want to
use a specific ROT key.
- ROTPK_HASH is generated based on ROT_KEY.
- ROTPK_HASH is included by uniphier_rotpk.S and compiled into BL1/BL2.
- ROT_KEY is input to cert_create tool.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
davidcunado-arm [Tue, 20 Jun 2017 14:34:54 +0000 (15:34 +0100)]
Merge pull request #992 from davidcunado-arm/dc/fix-signed-comparisons
xlat_tables_v2: fix signed/unsigned comparisons
Dimitris Papastamos [Mon, 19 Jun 2017 14:54:58 +0000 (15:54 +0100)]
juno: Fix AArch32 build
Commit
6de8b24f52cf2bd74adefbaa86dd2a0676c3eaa2 broke Juno AArch32
build.
Change-Id: Ied70d9becb86e53ccb46a2e3245e2a551d1bf701
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
Dimitris Papastamos [Tue, 13 Jun 2017 11:33:39 +0000 (12:33 +0100)]
aarch32: Fix L2CTRL definition for Cortex A57 and A72
Fixes ARM-software/tf-issues#495
Change-Id: I6a0aea78f670cc199873218a18af1d9cc2a6fafd
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
Dimitris Papastamos [Mon, 5 Jun 2017 13:55:41 +0000 (14:55 +0100)]
aarch32: Implement errata workarounds for Cortex A57
This brings the implementation on par with the software
errata workarounds for AArch64.
Change-Id: I98a85fd92e32ae4259f4ec5b3e93cffc87090064
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
Dimitris Papastamos [Mon, 5 Jun 2017 12:37:25 +0000 (13:37 +0100)]
aarch32: Implement errata workarounds for Cortex A53
This brings the implementation on par with the software
errata workarounds for AArch64.
Change-Id: Id103602e35b1c0ad3705a5b2b7cdb34dd8a8c5e2
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
Dimitris Papastamos [Mon, 5 Jun 2017 12:36:34 +0000 (13:36 +0100)]
aarch32: Implement cpu_rev_var_hs()
Helper function to assist with errata workaround application.
Change-Id: Idba42ca238442cc826f43444dbfa754e433a5e5e
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
Dimitris Papastamos [Wed, 7 Jun 2017 11:22:01 +0000 (12:22 +0100)]
sp_min: Flush console at end of main()
Flush the console so the errata report is printed correctly
before exit to normal world.
Change-Id: Idd6b5199b5fb8bda9d16a7b5c6426cdda7c73167
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
Dimitris Papastamos [Wed, 7 Jun 2017 12:45:41 +0000 (13:45 +0100)]
sp_min: Implement `sp_min_plat_runtime_setup()`
On ARM platforms before exiting from SP_MIN ensure that
the default console is switched to the runtime serial port.
Change-Id: I0ca0d42cc47e345d56179eac16aa3d6712767c9b
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
Varun Wadekar [Fri, 16 Jun 2017 21:15:34 +0000 (14:15 -0700)]
xlat_tables_v2: fix signed/unsigned comparisons
This patch changes input param level in xlat_tables_print_internal() to
an unsigned int to fix the signed/unsigned comparison warnings. The
compiler complains about these warnings, thus halting the build flow
for Tegra platforms.
Change-Id: Ieccc262a63daca7a26ca6a14d81466397af8b89f
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Signed-off-by: David Cunado <david.cunado@arm.com>
davidcunado-arm [Tue, 20 Jun 2017 11:20:08 +0000 (12:20 +0100)]
Merge pull request #966 from davidcunado-arm/dc/build_with_gcc6.2
Resolve build errors flagged by GCC 6.2
David Cunado [Thu, 1 Jun 2017 11:48:39 +0000 (12:48 +0100)]
Resolve build errors flagged by GCC 6.2
With GCC 6.2 compiler, more C undefined behaviour is being flagged as
warnings, which result in build errors in ARM TF build.
This patch addresses issue caused by enums with values that exceed
maximum value for an int. For these cases the enum is converted to
a set of defines.
Change-Id: I5114164be10d86d5beef3ea1ed9be5863855144d
Signed-off-by: David Cunado <david.cunado@arm.com>
davidcunado-arm [Tue, 20 Jun 2017 09:21:38 +0000 (10:21 +0100)]
Merge pull request #991 from davidcunado-arm/dc/update_hikey
hikey960: migrate to use A53 specific defines
David Cunado [Mon, 19 Jun 2017 10:48:22 +0000 (11:48 +0100)]
hikey960: migrate to use A53 specific defines
The patch
fb7d32e5881ef2445e8fe2305005f5590d4a7cfa migrated the CPU
libraries to have unique defines, prefixing them with the CPU name.
This patch migrates the hikey960 platform port to use the A53 specific
defines.
Change-Id: Id76f544b0b236bbd4974ab5ffa1203f073c20021
Signed-off-by: David Cunado <david.cunado@arm.com>
Leo Yan [Thu, 15 Jun 2017 05:51:22 +0000 (13:51 +0800)]
plat: Hikey960: fix the CPU hotplug
In CPU off callback function, the old code uses the function
hisi_test_pwrdn_allcores() to check if all CPUs in cluster have been
powered off and if it's valid then power off the whole cluster. But the
function hisi_test_pwrdn_allcores() only maintains the different power
states only for CPU suspend/resume flow, so it cannot return correct
states for CPU on/off flow.
This patch is to change use hisi_test_cpu_down() to check if all CPUs
have been powered off, so that can power off the whole cluster properly
when all CPUs in cluster have been hotplugged off.
Signed-off-by: Tao Wang <kevin.wangtao@hisilicon.com>
Signed-off-by: Leo Yan <leo.yan@linaro.org>
davidcunado-arm [Fri, 16 Jun 2017 11:06:24 +0000 (12:06 +0100)]
Merge pull request #953 from vwadekar/tegra-misra-fixes-v1
Tegra misra fixes v1
davidcunado-arm [Fri, 16 Jun 2017 08:17:45 +0000 (09:17 +0100)]
Merge pull request #984 from masahir0y/uniphier
uniphier memory-overrun bug fix
davidcunado-arm [Fri, 16 Jun 2017 08:17:28 +0000 (09:17 +0100)]
Merge pull request #986 from jagadeeshujja/jagujj/fix-get-power-state
CSS:Fix scpi "get_power_state" when ARM_PLAT_MT is set
davidcunado-arm [Thu, 15 Jun 2017 22:57:04 +0000 (23:57 +0100)]
Merge pull request #980 from dp-arm/dp/make-fix
tools: Use exported quiet flag from top-level Makefile
davidcunado-arm [Thu, 15 Jun 2017 22:50:30 +0000 (23:50 +0100)]
Merge pull request #981 from soby-mathew/sm/cov_scmi
Fix coverity error in CSS SCMI driver
davidcunado-arm [Thu, 15 Jun 2017 22:26:01 +0000 (23:26 +0100)]
Merge pull request #985 from hzhuang1/remove_mailbox
hikey960: remove mailbox driver
jagadeesh ujja [Thu, 11 May 2017 11:02:18 +0000 (16:32 +0530)]
CSS:Fix scpi "get_power_state" when ARM_PLAT_MT is set
The ARM_PLAT_MT bit enables the support for MT bit in
MPIDR format. This means that the level 0 affinity
represents the thread and CPU / Cluster levels are
at affinity level 1 and 2 respectively.
This was not catered for in the scpi 'css_scp_get_power_state, API.
Since the SCPI driver can only cater for single threaded CPUs,
this patch fixes the problem by catering for this shift by
effectively ignoring the Thread (level 0) affinity level.
Change-Id: If44f55c9fb2773c8d3f8a9bbcf5420a6f7409dfe
Signed-off-by: jagadeesh ujja <jagadeesh.ujja@arm.com>