Jagan Teki [Tue, 9 Apr 2019 09:38:51 +0000 (15:08 +0530)]
arm: allwinner: r40: Sync R40 dts(i) files from Linux 5.1-rc2
Sync sun8i-r40 dts(i) files from Linux 5.1-rc2
Linux commit details about the sun8i-r40* sync:
"ARM: dts: sun8i: r40: bananapi-m2-ultra: Add Bluetooth device node"
(sha1:
1e5f1db4ccd8348a21da55bff82f4263000879ef)
Linux commit details about the sun8i-v40* sync:
"ARM: dts: sunxi: Fix I2C bus warnings"
(sha1:
0729b4af5753b65aa031f58c435da53dbbf56d19)
Cc: Pablo Sebastián Greco <pgreco@centosproject.org>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Jagan Teki [Wed, 27 Feb 2019 18:57:01 +0000 (00:27 +0530)]
board: sunxi: gmac: Remove Ethernet clock and reset
Since Ethernet clock and reset is now handling via
CLK and RESET frameworks via driver API's remove
explicit ccm writes.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Jagan Teki [Wed, 27 Feb 2019 18:56:58 +0000 (00:26 +0530)]
net: sun8i_emac: Add CLK and RESET support
Add CLK and RESET support for sun8i_emac driver to
enable TX clock and reset pins via CLK and RESET
framework.
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Lothar Felten <lothar.felten@gmail.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Jagan Teki [Wed, 27 Feb 2019 18:56:51 +0000 (00:26 +0530)]
net: sun8i_emac: Retrieve GMAC clock via 'syscon' phandle
Unlike other Allwinner SoC's R40 GMAC clock control register
is locate in CCU, but rest located via syscon itself. Since
the phandle property for current code look for 'syscon' and
it will grab the respective ccu or syscon base address based
on DT property defined in respective SoC dtsi.
So, use the existing 'syscon' code even for R40 for retrieving
GMAC clock via CCU and update the register directly in
sun8i_emac_set_syscon instead of writing it separately using
ccm base.
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Lothar Felten <lothar.felten@gmail.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Jagan Teki [Wed, 27 Feb 2019 18:56:50 +0000 (00:26 +0530)]
net: sunxi_emac: Add CLK support
Add CLk support for sunxi_emac to enable AHB_EMAC clock
via CLK framework.
Cc: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Jagan Teki [Mon, 15 Apr 2019 11:12:16 +0000 (16:42 +0530)]
clk: sunxi: r40: Fix GMAC reset reg offset
GMAC reset reg offset added by below commit seems to assume
it as EMAC but R40 indeed using GMAC.
"clk: sunxi: Implement EMAC, GMAC clocks, resets"
(sha1:
68620c9698f109c1f001f80d282138a5c67cabef)
So, fix by updating the reg offset for RST_BUS_GMAC.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Jagan Teki [Sun, 14 Apr 2019 16:52:21 +0000 (22:22 +0530)]
arm64: allwinner: sun50i: Sync H6 dts(i) files from Linux
Usually the Linux dts changes were synced in specific tags in Allwinner,
to keep track for whats been synced so-far and plan for future syncs.
But this patch sync sun50i-h6* dts(i) files from Linux w/o any specific
tag since these dts(i) changes are required for new H6 boards support.
Linux commit details about the sun50i-h6* sync:
"arm64: dts: allwinner: h6: move MMC pinctrl to dtsi"
(sha1:
6ba2e45d57afdfd982d12f168edd6a79a65075d8)
Linux commit details about the sun8i-tcon-top.h sync:
"dt-bindings: display: sunxi-drm: Add TCON TOP description"
(sha1:
59a9c39544cd1e5952c2a33028d71aa8180648f8)
Part of the sync initiated by 'Clément Péron'.
Signed-off-by: Clément Péron <peron.clem@gmail.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Tom Rini [Sun, 14 Apr 2019 04:03:06 +0000 (00:03 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-spi
Conflicts:
arch/arm/dts/armada-385-amc.dts
arch/arm/dts/armada-xp-theadorable.dts
arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Sat, 13 Apr 2019 12:27:35 +0000 (08:27 -0400)]
Merge tag 'pull-12apr19' of git://git.denx.de/u-boot-dm
fdtdec tests and improvements for carve-outs
pinctrl race-condition fix
various other fixes in sandbox, sound, mkimage, etc.
Tom Rini [Sat, 13 Apr 2019 12:27:26 +0000 (08:27 -0400)]
Merge tag 'mips-pull-2019-04-12' of git://git.denx.de/u-boot-mips
- mt76xx: add USB support, small fixes
- ath79: small fixes, add support for QCA9563 SoC and AP152 reference board
- mscc: small fixes, add network support for JR2 and ServalT SoCs
- bmips: small fixes, enable more drivers for ARM specific BCM6858 and BCM63158 SoCs
- MIPS: fix redundant relocation of initrd images
Tom Rini [Fri, 12 Apr 2019 19:43:19 +0000 (15:43 -0400)]
Merge tag 'u-boot-stm32-
20190412' of https://github.com/patrickdelaunay/u-boot
stm32 patches for v2019.07-rc1
- Add trusted boot with TF-A for stm32mp1
- stm32mp1 dts files sync'ed with Linux version
- add STM32MP1 Discovery boards (DK1 and DK2)
- add STMFX gpio expander driver
- misc improvement for stm3mp1 supports
- rename stpmu1 to stpmic1 (official name)
- stm32_qspi: move to exec_op (spi nor driver for stm32 mpu and mcu)
- add STM32 FMC2 NAND flash controller driver
Tom Rini [Fri, 12 Apr 2019 19:43:08 +0000 (15:43 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-sunxi
Tom Rini [Fri, 12 Apr 2019 19:43:04 +0000 (15:43 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-i2c
Tom Rini [Fri, 12 Apr 2019 16:34:44 +0000 (12:34 -0400)]
Merge git://git.denx.de/u-boot-marvell
- Misc dts files sync'ed with Linux version (Chris)
- Orion watchdog fix (Chris)
- kwbimage changed to also support Marvell bin_hdr binary (Chris)
- Add DM support to enable CONFIG_BLK for sata_mv (Stefan)
- Enable BLK on multiple platforms (Stefan)
- Misc minor fixes to AXP theadorable board (Stefan)
- Correct logic for DM_SCSI + unconverted drivers check (stefan)
- Misc changes to kirkwood to enable DM_USB here (Chris)
- Change ahci_mvebu to enable usage on A38x (Baruch)
- Update the kirkwood entry in git-mailrc (Baruch)
- Misc minor improvements (turris, documentation) (Baruch)
- Enhance sata_mv to support Kirkwood as well (Michael)
- Add wdt command (Michael)
- Add Marvell integrated CPUs (MSYS) support with DB-XC3-24G4XG
board support (Chris)
Tom Rini [Fri, 12 Apr 2019 16:22:43 +0000 (12:22 -0400)]
Merge branch '2019-04-11-ti-master-imports'
- Improve Keystone 3 SoC support (DMA, TI SCI)
- Improve Keystone 2 SoC support (PHY fixes on various platforms)
- Improve am335x families (new platforms, more boot mode options in SPL
via DM).
- General DaVinci, OMAP5 fixes.
Stefan Roese [Fri, 5 Apr 2019 11:44:44 +0000 (13:44 +0200)]
mips: mt76xx: linkit-smart-7688: Enable USB and FS support
This patch enables USB and file-system support on the LinkIt smart
MT7688 module for both, the normal and the RAM default config.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Stefan Roese [Fri, 5 Apr 2019 11:44:43 +0000 (13:44 +0200)]
phy: Add USB PHY driver for the MT76x8 (7628/7688) SoC
This driver is derived from this Linux driver:
linux/drivers/phy/ralink/phy-ralink-usb.c
The driver sets up power and host mode, but also needs to configure PHY
registers for the MT7628 and MT7688.
I removed the reset controller handling for the USB host and device, as
it does not seem to be necessary right now. The soft reset bits for both
devices are enabled by default and testing has shown (with hackish
reset handling added), that USB related commands work identical with
or without the reset handling.
Please note that the resulting USB support is tested only very minimal.
I was able to detect one of my 3 currently available USB sticks.
Perhaps some further work is needed to fully support the EHCI controller
integrated in the MT76x8 SoC.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Horatiu Vultur [Mon, 8 Apr 2019 08:31:38 +0000 (10:31 +0200)]
configs: mscc_servalt: Add network support
Update default config to use network driver for ServalT SoCs.
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Horatiu Vultur [Mon, 8 Apr 2019 08:31:37 +0000 (10:31 +0200)]
net: mscc: servalt: Add ethernet nodes for ServalT
Add ethernet nodes for ServalT SoCs family. Currently there is only one
pcb(pcb116) in this family.
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Horatiu Vultur [Mon, 8 Apr 2019 08:31:36 +0000 (10:31 +0200)]
net: Add MSCC ServalT network driver.
Add network driver for Microsemi Ethernet switch.
It is present on ServalT SoCs.
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Horatiu Vultur [Mon, 8 Apr 2019 11:32:18 +0000 (13:32 +0200)]
configs: vcoreiii: Change CONFIG_ENV_SIZE
Shrink the environment size for 3 reasons:
- reading the environment it is slow, therefore having a smaller env
improves the speed.
- usually in the environment there are only few variables, therefore
the enviromnent is almost empty.
- because the same image can run on different boards which may have
different flashes with different page sizes, the CONFIG_ENV_SECT_SIZE
can't be change, it is set to least common multiple of the page sizes.
Adding this change improves the boot time. Before update for reading the
entire environment it took ~850 msec, after the change it takes ~40 msecs.
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Horatiu Vultur [Wed, 3 Apr 2019 17:54:48 +0000 (19:54 +0200)]
configs: mscc_jr2: Add network support
Update default confing to use network driver for Jaguar2 SoCs.
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Horatiu Vultur [Wed, 3 Apr 2019 17:54:47 +0000 (19:54 +0200)]
net: mscc: jaguar2: Add ethenet nodes for Jaguar2.
Add ethernet nodes for Jaguar2 SoCs family. There are 3 pcb in this
family: pcb110, pcb111 and pcb112.
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Horatiu Vultur [Wed, 3 Apr 2019 17:54:46 +0000 (19:54 +0200)]
board: mscc: jr2: Update MSCC Jaguar2 boards
In Jaguar2 SoC family there are 3 different pcb. Each of this needs
to configure the phys in different ways. Therefore implement the
function board_phy_config and based on pcb configure them accordingly.
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Horatiu Vultur [Wed, 3 Apr 2019 17:54:45 +0000 (19:54 +0200)]
net: Add MSCC Jaguar2 network driver.
Add network driver for Microsemi Ethernet switch.
It is present on Jaguar2 SoCs.
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Philippe Reynes [Thu, 7 Mar 2019 10:36:44 +0000 (11:36 +0100)]
bcm963158: enable gpio support
Enable the gpio support (driver and command)
in the configuration of the board bcm963158.
Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
Philippe Reynes [Thu, 7 Mar 2019 10:36:43 +0000 (11:36 +0100)]
dt: bcm963158: enable gpio controller
Enable all the gpio controllers in the device tree
of the board bcm963158.
Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
Philippe Reynes [Thu, 7 Mar 2019 10:36:42 +0000 (11:36 +0100)]
dt: bcm63158: add gpio controller
Add 8 gpio controllers in the bcm63158 device tree.
Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
Philippe Reynes [Thu, 7 Mar 2019 10:36:41 +0000 (11:36 +0100)]
gpio: do not include <asm/arch/gpio.h> on ARCH_BCM63158
As no gpio.h is defined for this architecture, to avoid
a compilation failure, do not include <asm/arch/gpio.h>
for arch bcm63158.
Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
Philippe Reynes [Thu, 7 Mar 2019 10:36:40 +0000 (11:36 +0100)]
gpio: bcm6345: allow this driver on ARCH_BCM63158
This IP is also used on some arm SoC, so we allow
to use this driver on arch bcm63158.
Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
Philippe Reynes [Thu, 7 Mar 2019 10:36:39 +0000 (11:36 +0100)]
bcm968580xref: enable gpio support
Enable the gpio support (driver and command)
in the configuration of the board bcm968580xref.
Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
Philippe Reynes [Thu, 7 Mar 2019 10:36:38 +0000 (11:36 +0100)]
dt: bcm968580xref: enable gpio controller
Enable all the gpio controllers in the device tree
of the board bcm968580xref.
Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
Philippe Reynes [Thu, 7 Mar 2019 10:36:37 +0000 (11:36 +0100)]
dt: bcm6858: add gpio controller
Add 8 gpio controllers in the bcm6858 device tree.
Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
Philippe Reynes [Thu, 7 Mar 2019 10:36:36 +0000 (11:36 +0100)]
gpio: do not include <asm/arch/gpio.h> on ARCH_BCM6858
As no gpio.h is defined for this architecture, to avoid
compilation failure, do not include <asm/arch/gpio.h> for
arch bcm6858.
Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
Philippe Reynes [Thu, 7 Mar 2019 10:36:35 +0000 (11:36 +0100)]
gpio: bcm6345: allow this driver on ARCH_BCM6858
This IP is also used on some arm SoC, so we allow
to use this driver on arch bcm6858.
Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
Philippe Reynes [Thu, 7 Mar 2019 10:36:34 +0000 (11:36 +0100)]
bcm968380gerg: enable gpio support
Enable the gpio support (driver and command)
in the configuration of the board bcm968380gerg
Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
Philippe Reynes [Thu, 7 Mar 2019 10:36:33 +0000 (11:36 +0100)]
dt: bcm968380gerg: enable gpio controller
Enable the gpio controllers in the device tree
of the board bcm968380gerg.
Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Philippe Reynes [Thu, 7 Mar 2019 10:36:32 +0000 (11:36 +0100)]
dt: bcm6838: add gpio controller
Add gpio controllers in bcm6838 device tree.
Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Philippe Reynes [Thu, 7 Mar 2019 10:36:31 +0000 (11:36 +0100)]
gpio: bcm6345: switch to raw I/O functions
This driver is used on several big endian mips board.
So we could use raw I/O function instead of forcing
big endian access.
Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Rosy Song [Sat, 16 Mar 2019 01:24:50 +0000 (09:24 +0800)]
ag7xxx: add initial support for s17
S17 ethernet support is for QCA8337N, which used on
AP152 (QCA9563) board. It is a 7 ports GbE switch.
Signed-off-by: Rosy Song <rosysong@rosinson.com>
Changes for v2-v3:
- add more commit message for s17
Changes for v4-v5:
- coding style cleanup
Rosy Song [Sat, 16 Mar 2019 01:24:44 +0000 (09:24 +0800)]
mips: add initial support for qca956x referenced board
QCA9563 is CPU used on AP152 board :
Clock speed : 750 MHz ,
Arch : Mips 74Kc,
Eth : SGMII interface,
MIMO config : 3 * 3 450M,
2 * USB 2.0,
Signed-off-by: Rosy Song <rosysong@rosinson.com>
Changes for v2:
- coding style cleanup
- remove ununsed flash chip in defconfig
- enable automatic icache / dcache size in defconfig
Changes for v3:
- add detailed information for qca956x in commit message
Changes for v4:
- remove pre-configured network settings in ap152.h
Changes for v5:
- coding style cleanup
Rosy Song [Sat, 16 Mar 2019 01:24:37 +0000 (09:24 +0800)]
mips: fix erros on registers macros of pll-ddr-config1-nfrac for QCA956X
See details in chapter 8.6.2 and 8.6.4 (page 140-141) of qca9563 datasheet,
NFRAC[17:0]
So the mask of [17:5] is 0x1fff not 0x3fff.
Signed-off-by: Rosy Song <rosysong@rosinson.com>
Changes for v2-v3:
- add more information for this commit
Changes for v4-v5:
- coding style cleanup
Álvaro Fernández Rojas [Fri, 22 Mar 2019 17:22:31 +0000 (18:22 +0100)]
dma: bcm6348: check if driver is enabled before send/recv
This patch prevents errors when running tftpput.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Horatiu Vultur [Wed, 27 Mar 2019 09:16:18 +0000 (10:16 +0100)]
net: mscc: ocelot: Fix reset of the phys
The function mscc_miim_reset resets all the phys, but it is called for
each phy separetely. One consequence of this is that the boot time
is increased by 2 seconds.
The fix consists for calling the mscc_miim_reset function only once for
all phys.
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Horatiu Vultur [Thu, 7 Mar 2019 15:49:41 +0000 (16:49 +0100)]
bootm: mips: Remove boot_reloc_ramdisk
Remove the function boot_reloc_ramdisk in the file arch/mips/lib/bootm
because it is relocating again the ramdisk. The function do_bootm_states()
already relocates the ramdisk even if it is a legacy uImage or a FIT image.
The relocation in the function do_bootm_states() was introduce in the
commit
c2e7e72bb9f0cb47d024997b381cb64786eb5402 ("bootm: relocate ramdisk
if CONFIG_SYS_BOOT_RAMDISK_HIGH set")
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Stefan Roese [Fri, 15 Mar 2019 08:09:34 +0000 (09:09 +0100)]
mips: mt76xx: gardena-smart-gateway: Correct spelling of GARDENA
This patch changes Gardena to the correct GARDENA spelling. Also the
platform name is "GARDENA smart Gateway". This patch changes the
incorrect occurrances.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Stefan Roese [Mon, 18 Feb 2019 09:46:55 +0000 (10:46 +0100)]
mips: mt76xx: linkit: Add mtd command support
The new mtd is very useful so let's enable it on the LinkIt Smart
7688 as well.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Jiri Kastner <cz172638@gmail.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Rosy Song [Tue, 5 Feb 2019 09:50:55 +0000 (17:50 +0800)]
mips: add ethernet support for qca953x referenced boards
Signed-off-by: Rosy Song <rosysong@rosinson.com>
Rosy Song [Tue, 5 Feb 2019 09:50:44 +0000 (17:50 +0800)]
drivers: add ethernet support for qca953x in ag7xxx driver
Signed-off-by: Rosy Song <rosysong@rosinson.com>
Rosy Song [Tue, 5 Feb 2019 09:49:43 +0000 (17:49 +0800)]
drivers: fix typo for pinctrl qca953x
Signed-off-by: Rosy Song <rosysong@rosinson.com>
Christophe Kerello [Fri, 5 Apr 2019 09:41:50 +0000 (11:41 +0200)]
mtd: rawnand: stm32_fmc2: add STM32 FMC2 NAND flash controller driver
The driver adds the support for the STMicroelectronics FMC2 NAND
Controller found on STM32MP SOCs.
This patch adds the polling mode, a basic mode that do not need
any DMA channels.
Only NAND_ECC_HW mode is actually supported.
The driver supports a maximum 8k page size.
The following ECC strength and step size are currently supported:
- nand-ecc-strength = <8>, nand-ecc-step-size = <512> (BCH8)
- nand-ecc-strength = <4>, nand-ecc-step-size = <512> (BCH4)
- nand-ecc-strength = <1>, nand-ecc-step-size = <512> (Extended ECC
based on Hamming)
This patch has been tested on Micron MT29F8G08ABACAH4.
Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
Christophe Kerello [Fri, 5 Apr 2019 09:41:49 +0000 (11:41 +0200)]
dt-bindings: mtd: stm32_fmc2: add STM32 FMC2 NAND controller documentation
This patch adds the documentation of the device tree bindings for the STM32
FMC2 NAND controller.
Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@st.com>
Christophe Kerello [Fri, 5 Apr 2019 09:46:50 +0000 (11:46 +0200)]
spi: stm32_qspi: move to exec_op
We are facing issues in the driver since SPI NOR framework has moved
on SPI MEM framework, and SPI NAND framework is not running properly
with the current driver.
To be able to solve issues met on SPI NOR Flashes and to be able to
support SPI NAND Flashes, the driver has been reworked. We are now using
exec_op ops instead of using xfer ops.
Thanks to this rework, the driver has been successfully tested with:
- mx66l51235l SPI NOR Flash on stm32f746 SOC
- n25q128a SPI NOR Flash on stm32f769 SOC
- mx66l51235l SPI NOR Flash on stm32mp1 SOC
- mt29f2g01abagd SPI NAND Flash on stm32mp1 SOC
Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
Tested-by: Patrick DELAUNAY <patrick.delaunay@st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@st.com>
Patrick Delaunay [Fri, 12 Apr 2019 12:38:28 +0000 (14:38 +0200)]
ARM: dts: Add STMFX gpio expander support for stm32mp157c-ev1
Adds alias to set the pincontrol seq id.
For STMFX gpio expander, force sequence number after
the last bank (GPIOZ) to avoid conflict between STM32MP and STMFX
gpio bank sequence number.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Patrice Chotard [Mon, 11 Mar 2019 10:13:17 +0000 (11:13 +0100)]
board: stm32mp1: Force pinctrl driver probe in board_init()
In order to insure that hog GPIOs are configured early during
the boot process, force all pinctrl driver probing in board_init().
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Patrick Delaunay [Mon, 11 Mar 2019 10:13:16 +0000 (11:13 +0100)]
config: stm32mp15: Enable STMFX support
Activate PINCTRL_STMFX and needed part for generic pincontrol
PINCTRL_FULL, PINCONF. Increase pre-reloc memory for MALLOC
(needed for each DM pinconfig node).
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Patrick Delaunay [Mon, 11 Mar 2019 10:13:15 +0000 (11:13 +0100)]
pinctrl: Add STMFX GPIO expander Pinctrl/GPIO driver
This patch adds pinctrl/GPIO driver for STMicroelectronics
Multi-Function eXpander (STMFX) GPIO expander.
STMFX is an I2C slave controller, offering up to 24 GPIOs.
The driver relies on UCLASS_PINCTRL and UCLASS_GPIO.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Patrice Chotard [Tue, 12 Feb 2019 15:50:41 +0000 (16:50 +0100)]
ARM: dts: stm32mp1: Add adc nodes
Add adc related nodes. These nodes are used to detect the
current supplied by USB type-C power in port on DK1 and DK2
boards.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Patrice Chotard [Tue, 12 Feb 2019 15:50:40 +0000 (16:50 +0100)]
Board: stm32mp1: Add supply current boot information
For DK1/DK2 boards, check if power supply provides enough current
to allow the board to boot correctly.
ADC@0 channel 18 and 19 are connected to USB type-C CC1 and CC2
signals. The table below shows the behavior for different range of
CC1 or CC2:
range | power supply | red led | console message
(Volts) | (Amps) | blinks |
--------------|--------------|---------|-----------------------------------
[2.10 - 1.23[ | 3 | NO | NO
[1.23 - 0.66[ | 1.5 | 3 times | WARNING 1.5A power supply detected
[0.66 - 0] | 0.5 | 2 times | WARNING 500mA power supply detected
If detected current is < 3A, red led is kept ON after blinking.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Patrice Chotard [Tue, 12 Feb 2019 15:50:39 +0000 (16:50 +0100)]
board: stm32mp1: Update README file
Update README with DK1 and DK2 boards related informations
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Patrice Chotard [Tue, 12 Feb 2019 15:50:38 +0000 (16:50 +0100)]
ARM: dts: stm32: Synchronize DT with kernel one
This patch synchronizes U-boot DT with kernel one
This is based on https://patchwork.kernel.org/cover/
10797115/
This patch adds initial support of STM32MP157 discovery boards:
- Add support of stm32mp157a discovery1 board (part number: STM32MP157A-DK1).
This board embeds a STM32MP157a SOC with AC package (TFBGA361, 148 ios)
and 512MB of DDR3. Several connections are available on this boards:
4*USB2.0, 1*USB2.0 typeC, SDcard, RJ45, HDMI, Arduino connector, ...
- Add support of stm32mp157c discovery2 board (part number: STM32MP157C-DK2).
This board is a "super-set" of stm32mp157a-dk1. A display panel (otm8009a)
and Murata wifi/BT combo is added.
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Patrick Delaunay [Mon, 4 Feb 2019 10:26:22 +0000 (11:26 +0100)]
stpmic1: add NVM update support in fuse command
Add functions to read/update the non volatile memory of STPMIC1
(8 bytes-register at 0xF8 address) and allow access
with fuse command (bank=1, word > 0xF8).
For example:
STM32MP> fuse read 1 0xf8 8
Reading bank 1:
Word 0x000000f8:
000000ee 00000092 000000c0 00000002
Word 0x000000fc:
000000f2 00000080 00000002 00000033
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Patrick Delaunay [Mon, 4 Feb 2019 10:26:21 +0000 (11:26 +0100)]
stm32mp1: dts: activate psci-1.0
Updates the stm32mp157c devicetree to bind the U-Boot PSCI driver need for
power off command; TF-A for stm32mp15x supports PSCI 1.0.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Patrick Delaunay [Fri, 12 Apr 2019 09:55:46 +0000 (11:55 +0200)]
stm32mp1: add command poweroff
Activate the command poweroff by default for STM32MP1:
- with PCSI from TF-A for trusted boot
- with PMIC sysreset request for basic boot (SYSRESET_POWER)
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Patrick Delaunay [Mon, 4 Feb 2019 10:26:19 +0000 (11:26 +0100)]
pmic: stpmu1: add power switch off support
Add sysreset support, and support power switch off request,
needed by poweroff command.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Patrick Delaunay [Mon, 4 Feb 2019 10:26:18 +0000 (11:26 +0100)]
stpmic1: update register names
Alignment with STPMIC1 datasheet
s/MAIN_CONTROL_REG/MAIN_CR/g
s/MASK_RESET_BUCK/BUCKS_MRST_CR/g
s/MASK_RESET_LDOS/LDOS_MRST_CR/g
s/BUCKX_CTRL_REG/BUCKX_MAIN_CR/g
s/VREF_CTRL_REG/REFDDR_MAIN_CR/g
s/LDOX_CTRL_REG/LDOX_MAIN_CR/g
s/USB_CTRL_REG/BST_SW_CR/g
s/STPMIC1_NVM_USER_STATUS_REG/STPMIC1_NVM_SR/g
s/STPMIC1_NVM_USER_CONTROL_REG/STPMIC1_NVM_CR/g
and update all the associated defines.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Patrick Delaunay [Mon, 4 Feb 2019 10:26:17 +0000 (11:26 +0100)]
power: rename stpmu1 to official name stpmic1
Alignment with kernel driver name & binding
introduced by https://patchwork.kernel.org/cover/
10761943/
to use the final marketing name = STPMIC1.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Patrick Delaunay [Mon, 4 Feb 2019 10:26:16 +0000 (11:26 +0100)]
power: stpmu1: rename files to stpmic1
Prepare file modification for kernel alignment and
rename driver to stpmic1.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Patrick Delaunay [Mon, 4 Feb 2019 10:26:15 +0000 (11:26 +0100)]
regulator: stpmu1: update buck1 range
SW impact for Rev 1.2 of STPMIC1 in U-Boot:
Buck converters output voltage change for Buck1
=> Vdd min 0,725 to max 1,5V instead of 0.6V to 1.35V
(see STPMIC1 datasheet / chapter 5.3 Buck converters)
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Patrick Delaunay [Wed, 27 Feb 2019 16:01:29 +0000 (17:01 +0100)]
stm32mp1: Replace OTP read by SHADOW read
Replace STM32_BSEC_OTP() by STM32_BSEC_SHADOW() to
increase read performance.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Patrick Delaunay [Wed, 27 Feb 2019 16:01:28 +0000 (17:01 +0100)]
stm32mp1: bsec: shadow all the upper OTP (no secure) during boot
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Patrick Delaunay [Wed, 27 Feb 2019 16:01:27 +0000 (17:01 +0100)]
stm32mp1: bsec: use device tree new compatible
Update bsec driver to use the device tree provided by Kernel.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Patrick Delaunay [Wed, 27 Feb 2019 16:01:26 +0000 (17:01 +0100)]
stm32mp1: basic boot: SPL enable access to GPIOZ bank
SPL need to set GPIOZ_SECCFGR = 0 to enable access to GPIOZ bank
(open security).
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Patrick Delaunay [Wed, 27 Feb 2019 16:01:25 +0000 (17:01 +0100)]
stm32mp1: align serial number on bootrom
Always use upper case for serial number.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Patrick Delaunay [Wed, 27 Feb 2019 16:01:24 +0000 (17:01 +0100)]
stm32mp1: add syscfg initialization
Initialize the system configuration for basic boot
- update interconnect setting
- disable pull-down for boot pin
- enable High Speed Low Voltage Pad mode for SPI, SDMMC, ETH, QSPI
- activate I/O compensation
Done by SSBL = TF-A for trusted boot
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Patrick Delaunay [Wed, 27 Feb 2019 16:01:23 +0000 (17:01 +0100)]
stm32mp1: add some syscon drivers for syscfg and etpzc
Add SYSCON driver for syscfg and etpzc and reorder in alphabetics order
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Patrick Delaunay [Wed, 27 Feb 2019 16:01:22 +0000 (17:01 +0100)]
stm32mp1: activated some configuration
Add configuration useful for test
- FIT support
- MEMTEST
- DFU
- CACHE
- TIME
- TIMER
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Patrick Delaunay [Wed, 27 Feb 2019 16:01:21 +0000 (17:01 +0100)]
stm32mp1: update memory layout
Update the memory layout to be aligned with other platform and avoid
overlap with 32MB Linux kernel (multiv7 image).
+ Kernel => 32MiB offset = 0xC2000000
and increase the bootm size to 32MiB
+ FDT => 64MiB offset = 0xc4000000
+ SCRIPT => 65Mib offset = 0xc4100000
+ PXESCRIPT => 66Mib offset = 0xc4200000
+ SPLASHIMAGE => 67Mib offset = 0xc4300000
+ RAMDISK => 68Mib offset = 0xc4400000
(not limited size)
In sources/boot/u-boot/doc/README.distro
+ kernel_addr_r: A size of 16MB for the kernel is likely adequate.
+ pxefile_addr_r: A size of 1MB for extlinux.conf is more than adequate.
+ fdt_addr_r: A size of 1MB for the FDT/DTB seems reasonable.
+ ramdisk_addr_r: It is recommended that this location be highest in RAM
out of fdt_addr_, kernel_addr_r, and ramdisk_addr_r,
so that the RAM disk can vary in size and use any
available RAM.
+ pxefile_addr_r: A size of 1MB for extlinux.conf is more than adequate.
+ scriptaddr: A size of 1MB for extlinux.conf is more than adequate.
For suggestions on memory locations for ARM systems, you must follow
the guidelines specified in Documentation/arm/Booting
in the Linux kernel tree.
And in sources/linux-stm32mp/Documentation/arm/Booting
The zImage may also be placed in system RAM and called there. The
kernel should be placed in the first 128MiB of RAM. It is recommended
that it is loaded above 32MiB in order to avoid the need to relocate
prior to decompression, which will make the boot process slightly
faster.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Patrick Delaunay [Wed, 27 Feb 2019 16:01:20 +0000 (17:01 +0100)]
stm32mp1: support forced boot mode
The boot mode can be forced by key press
or by TAMP register, requested in kernel by syscon-reboot-mode
tamp: tamp@
5c00a000 {
compatible = "simple-bus", "syscon", "simple-mfd";
reg = <0x5c00a000 0x400>;
reboot-mode {
compatible = "syscon-reboot-mode";
offset = <0x150>; /* reg20 */
mask = <0xff>;
mode-normal = <0>;
mode-fastboot = <0x1>;
mode-recovery = <0x2>;
mode-stm32cubeprogrammer = <0x3>;
mode-ums_mmc0 = <0x10>;
mode-ums_mmc1 = <0x11>;
mode-ums_mmc2 = <0x12>;
};
};
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Patrick Delaunay [Wed, 27 Feb 2019 16:01:19 +0000 (17:01 +0100)]
stm32mp1: activate FASTBOOT on eMMC
activate Fastboot for eMMC on EV1 board (mmc1)
$> sudo apt-get install android-tools-adb android-tools-fastboot
$> fastboot -i 0x0483 getvar bootloader-version
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Patrick Delaunay [Wed, 27 Feb 2019 16:01:18 +0000 (17:01 +0100)]
stm32mp1: update bootcmd
Clearly separate bootcmd for stm32mp1 board
(bootcmd_stm32mp) and preboot management.
That solve issue for fastboot continue command.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Patrick Delaunay [Wed, 27 Feb 2019 16:01:17 +0000 (17:01 +0100)]
stm32mp1: spl: hang with trace when DDR init failed
When DDR initialization failed, print error message
and stop the SPL execution.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Patrick Delaunay [Wed, 27 Feb 2019 16:01:16 +0000 (17:01 +0100)]
stm32mp1: cosmetic: add comment on psci_migrate_info_type return value
Add explaination for the return value of psci_migrate_info_type:
2 = Trusted OS.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Patrick Delaunay [Wed, 27 Feb 2019 16:01:15 +0000 (17:01 +0100)]
stm32mp1: cosmetic cleanup Kconfig
Cosmetic cleanup in mach-stm32mp Kconfig
- remove duplicated SPL_DRIVERS_MISC_SUPPORT
- update help for TARGET_STM32MP1
- set value for NR_DRAM_BANKS
- remove one comment as DEBUG_UART is deactivated by default
- include board Kconfig at the end of the file
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Patrick Delaunay [Wed, 27 Feb 2019 16:01:14 +0000 (17:01 +0100)]
stm32mp1: spl: add spl_display_print
SPL displays the board model from device tree.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Patrick Delaunay [Wed, 27 Feb 2019 16:01:13 +0000 (17:01 +0100)]
stm32mp1: update print_cpuinfo()
Display CPU part number and package information.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Patrick Delaunay [Wed, 27 Feb 2019 16:01:12 +0000 (17:01 +0100)]
stm32mp1: update boot mode management
- export the function get_bootmode() and reused it in spl code
- manage uart instance by alias (prepare v4.19 binding)
- solve issue on nand instance
- restore console for uart boot
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Patrick Delaunay [Wed, 27 Feb 2019 16:01:11 +0000 (17:01 +0100)]
stm32mp1: add runtime information in environment
Set board name with the first dts compatible found in DT
code under CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
The result with DEVICE_TREE=stm32mp157c-ev1 is:
STM32MP> env print
board=stm32mp1
board_name=stm32mp157c-ev1
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Patrick Delaunay [Tue, 12 Feb 2019 10:44:41 +0000 (11:44 +0100)]
stm32mp1: display board information
Implement checkboard() function to display
- the boot chain used: basic or trusted
- the board compatible in device tree
- the board identifier and revision, saved in OTP59 for ST boards
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Patrick Delaunay [Tue, 12 Feb 2019 10:44:40 +0000 (11:44 +0100)]
stm32mp1: bsec: access with SMC for trusted boot
As BSEC is secure aware, all register access need to be done
by TF-A for TRUSTED boot chain, when U-Boot is executed in
normal world.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Patrick Delaunay [Tue, 12 Feb 2019 10:44:39 +0000 (11:44 +0100)]
stm32mp1: add trusted boot with TF-A
Add support of trusted boot, using TF-A as first stage bootloader,
The boot sequence is
BootRom >=> TF-A.stm32 (clock & DDR) >=> U-Boot.stm32
The TF-A monitor provides secure monitor with support of SMC
- proprietary to manage secure devices (BSEC for example)
- PSCI for power
The same device tree is used for STMicroelectronics boards with
basic boot and with trusted boot.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Jagan Teki [Fri, 12 Apr 2019 13:14:34 +0000 (18:44 +0530)]
MAINTAINERS: Change Jagan's email address
Missed few mails from openedev, since most of the day I look at
amarulasolutions mail so update the same.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Neil Armstrong [Fri, 12 Apr 2019 09:50:10 +0000 (11:50 +0200)]
mtd: spi-nor-ids: Add Gigadevice gd25lq128 ID
This adds support for the Gigadevice gd25lq128 ID needed on the
upcoming libretech-ac board.
SPI_NOR_QUAD_READ is not set since it has not been tested in Quad
mode.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Faiz Abbas [Fri, 5 Apr 2019 08:48:46 +0000 (14:18 +0530)]
mmc: omap_hsmmc: Set 3.3V for IO voltage
Pbias voltage should match the IO voltage set for the SD card. With the
latest pbias change to 3.3V, update the capabilities and IO voltages
settings to 3.3V.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Faiz Abbas [Fri, 5 Apr 2019 08:48:45 +0000 (14:18 +0530)]
ARM: dts: dra71-evm: Correct evm_sd regulator max voltage
Correct vpo_sd_1v8_3v3 regulator max voltage to 3.3V
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Reviewed-by: Keerthy <j-keerthy@ti.com>
Faiz Abbas [Fri, 5 Apr 2019 08:48:44 +0000 (14:18 +0530)]
ARM: dts: dra7: Change pbias voltage to 3.3V
As per recent TRM[1], PBIAS cell on dra7 devices supports
3.3v and not 3.0v as documented earlier.
Update PBIAS regulator max voltage and the voltage written
in the driver to reflect this.
[1] http://www.ti.com/lit/pdf/sprui30
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Adam Ford [Sun, 31 Mar 2019 14:18:29 +0000 (09:18 -0500)]
ARM: am3517_evm: Add spl_start_uboot for Falcon Mode
When booting the am3517-evm, the following message appears:
SPL: Please implement spl_start_uboot() for your board
SPL: Direct Linux boot not active!
This patch implements spl_start_uboot to clear this message
and allow device to know if it should boot U-Boot or kernel.
Fixes: 1c6b6f383a41 ("ARM: am3517_evm: Enable Falcon Mode")
Signed-off-by: Adam Ford <aford173@gmail.com>
Tom Rini [Tue, 19 Mar 2019 11:14:37 +0000 (07:14 -0400)]
ti: keystone2: Move CONFIG_ISW_ENTRY_ADDR to a common place
The ISW_ENTRY_ADDR Kconfig option under mach-omap2 isn't a SoC specific
notion but rather "where is our previous stage loaded in memory?"
option. Make use of this on ARCH_KEYSTONE rather than SPL_TEXT_BASE for
our HS builds that are not using SPL anyhow.
Cc: Vitaly Andrianov <vitalya@ti.com>
Cc: Andrew F. Davis <afd@ti.com>
Cc: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com?
Faiz Abbas [Mon, 18 Mar 2019 08:24:41 +0000 (13:54 +0530)]
board: ti: am335x: Remove non DM_ETH code
With DM_ETH enabled in am335x devices, remove all the unused
non-DM code.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Faiz Abbas [Mon, 18 Mar 2019 08:24:40 +0000 (13:54 +0530)]
configs: am335x_evm: Update VCI String
Update VCI string to keep it compatible with legacy test setups.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
projects / project / bcm63xx / u-boot.git / log