Kevin Wang [Tue, 23 Apr 2019 03:02:24 +0000 (11:02 +0800)]
drm/amd/powerplay: add function unforce_dpm_levels for navi10
add callback function unforce_dpm_levels for navi10 asic
Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kevin Wang [Tue, 23 Apr 2019 02:53:51 +0000 (10:53 +0800)]
drm/amd/powerplay: add funciton force_dpm_limit for navi10
add callback function force_dpm_limit for navi10 asic
Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kevin Wang [Tue, 23 Apr 2019 06:16:52 +0000 (14:16 +0800)]
drm/amd/powerplay: add function display_configuration_changed for navi10
1.add callback function to support navi10 asic.
2.Remove unnecessary logical code.
Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kevin Wang [Mon, 22 Apr 2019 06:37:46 +0000 (14:37 +0800)]
drm/amd/powerplay: add function pre_display_config_changed for navi10
add callback function pre_display_config_changed for navi10 asic
Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kevin Wang [Fri, 19 Apr 2019 06:05:58 +0000 (14:05 +0800)]
drm/amd/powerplay: add function get_clock_by_type_with_latency for navi10
add callback function get_clock_by_type_with_latency for navi10 asic
Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kevin Wang [Fri, 19 Apr 2019 05:27:19 +0000 (13:27 +0800)]
drm/amd/powerplay: add function populate_umd_state_clk for navi10
add callback function populate_umd_state_clk for navi10 asic
Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kevin Wang [Fri, 19 Apr 2019 02:31:18 +0000 (10:31 +0800)]
drm/amd/powerplay: add function force_clk_levels for navi10
add sysfs interface of force_clk_levels sysfs for navi10.
Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kevin Wang [Mon, 22 Apr 2019 06:40:30 +0000 (14:40 +0800)]
drm/amd/powerplay: add helper function of smu_set_hard_freq_range
add this function to get dpm clock information.
Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kevin Wang [Fri, 19 Apr 2019 02:19:28 +0000 (10:19 +0800)]
drm/amd/powerplay: add helper function of smu_set_soft_freq_range
add this helper function to get dpm clk information.
Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kevin Wang [Thu, 18 Apr 2019 10:46:04 +0000 (18:46 +0800)]
drm/amd/powerplay: add helper function of smu_get_dpm_freq_range
add this helper function to get dpm clk information (min, max);
Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kevin Wang [Thu, 18 Apr 2019 07:06:34 +0000 (15:06 +0800)]
drm/amd/powerplay: add function print_clk_levels for navi10
add sysfs interface of print_clk_levels sysfs for navi10.
Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kevin Wang [Wed, 27 Mar 2019 06:46:20 +0000 (14:46 +0800)]
drm/amd/powerplay: add helper function to get dpm freq informations
this function can help driver to get ppclk informations
Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kevin Wang [Wed, 17 Apr 2019 06:58:28 +0000 (14:58 +0800)]
drm/amd/powerplay: add function get current clock freq interface for navi10
add function of get_current_clk_freq_by_table for navi10.
Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Mon, 6 May 2019 10:55:23 +0000 (18:55 +0800)]
drm/amdgpu/gfx10: require to pin/unpin CSIB BO when suspend/resume
CSIB BO is required to be pinned down to guarantee
bo is always valid when resume, and to be unpinned it
so that its content can be saved during suspend.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Mon, 6 May 2019 08:40:48 +0000 (16:40 +0800)]
drm/amdgpu/gfx10: remove unnecessary waiting on gfx inactive
The following KIQ ring test could guarantee the previous unmap
has been done.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Mon, 6 May 2019 08:35:41 +0000 (16:35 +0800)]
drm/amdgpu: RLC must be disabled after SMU when S3 on navi
SMU requires to interact with RLC when disable all features,
so RLC shouldn't be disabled ahead of SMU.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Mon, 6 May 2019 08:28:22 +0000 (16:28 +0800)]
drm/amd/powerplay/smu11: disable PLL shutdown when gfxoff enabled
MP1 cannot access clock IP during MP1 FW reload, disable PLL
shutdown as a workaround.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
tiancyin [Mon, 29 Apr 2019 08:56:16 +0000 (16:56 +0800)]
drm/amd/powerplay: disable uclk dpm by default
[why]
The uclk dpm feature is not supported by some certain navi10
board like 18202, while supported by some board like 18201.
It causes modprobe failure on 18202 board.
[how]
Disabled this feature by default, it can be enabled by module parameter
uclk_dpm_support=1.
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: tiancyin <tianci.yin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Leo Liu [Tue, 30 Apr 2019 14:15:38 +0000 (10:15 -0400)]
drm/amdgpu/VCN2.0: remove powergating for UVDW tile
No UVDW tile any more from VCN2.0, so mark out related fields.
It fixes error:
"[drm] Register(0) [mmUVD_PGFSM_STATUS] failed to reach value 0x002aaaaa != 0x00aaaaaa"
Signed-off-by: Leo Liu <leo.liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kenneth Feng [Fri, 26 Apr 2019 05:53:10 +0000 (13:53 +0800)]
amd/powerplay: enable uclk dpm
Enable uclk dpm on navi10 as the result of
removing fast switch setting.
Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kenneth Feng [Thu, 30 May 2019 04:20:24 +0000 (23:20 -0500)]
amd/powerplay: fix the issue of uclk dpm
PPSMC_MSG_SetUclkFastSwitch message can be applied on vega20,
but can't on navi10. This is the prerequisite of uclk dpm on
navi10.
Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojie Yuan [Fri, 19 Apr 2019 10:44:18 +0000 (18:44 +0800)]
drm/amdgpu/gfx10: fix unbalanced MAP/UNMAP_QUEUES when async_gfx_ring is disabled
gfx_v10_0_kiq_enable_kgq() is called only when async_gfx_ring is
enabled, so should gfx_v10_0_kiq_disable_kgq().
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojie Yuan [Fri, 21 Jun 2019 16:14:37 +0000 (11:14 -0500)]
drm/amdgpu/gfx10: drop redundant se/sh selection
we already selected se/sh at the beginning of the for loop
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Mon, 15 Apr 2019 09:03:01 +0000 (17:03 +0800)]
drm/amdgpu/mes10.1: enable mes FW backdoor loading
It enables MES FW backdoor loading in ip block functions.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Sun, 14 Apr 2019 09:16:48 +0000 (17:16 +0800)]
drm/amdgpu/mes10.1: implement mes enablement function
After MES firmware gets loaded, it enables MES engine starting execution.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Sun, 14 Apr 2019 08:17:30 +0000 (16:17 +0800)]
drm/amdgpu/mes10.1: implement MES firmware backdoor loading
It implements MES firmware backdoor loading.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Fri, 12 Apr 2019 11:11:18 +0000 (19:11 +0800)]
drm/amdgpu/mes10.1: implement ucode buffers destruction
Free ucode GPU buffers.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Fri, 12 Apr 2019 10:58:57 +0000 (18:58 +0800)]
drm/amdgpu/mes10.1: upload mes data ucode to gpu buffer
Allocate GPU buffer and upload mes data ucode to the buffer.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Fri, 12 Apr 2019 10:53:35 +0000 (18:53 +0800)]
drm/amdgpu/mes10.1: upload mes ucode to gpu buffer
Allocate GPU buffer and upload ucode firmware to the buffer.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Mon, 15 Apr 2019 08:58:20 +0000 (16:58 +0800)]
drm/amdgpu/mes10.1: implement ucode CPU buffer destruction
It implements the CPU buffer destruction of ucode.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Mon, 15 Apr 2019 03:31:04 +0000 (11:31 +0800)]
drm/amdgpu/mes10.1: load mes firmware file to CPU buffer
It requests MES firmware binary and uploads to CPU buffer.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Mon, 15 Apr 2019 03:34:03 +0000 (11:34 +0800)]
drm/amdgpu/mes10.1: add mes firmware info fields
The newly added fields is to store mes firmware related information.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Mon, 15 Apr 2019 03:33:05 +0000 (11:33 +0800)]
drm/amdgpu/ucode: add mes firmware file support
The newly added firmware struct is for mes firmware file.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Fri, 12 Apr 2019 06:23:44 +0000 (14:23 +0800)]
drm/amdgpu/ucode: add the definitions of MES ucode and ucode data
MES requires two seperate firmwares: ucode and ucode data.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Wed, 24 Apr 2019 02:55:20 +0000 (10:55 +0800)]
drm/amdgpu/sdma5: incorrect variable type for gpu address
Incorrect programming with 64bit gpu address assignment for
32bit variable.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
tiancyin [Mon, 22 Apr 2019 09:07:06 +0000 (17:07 +0800)]
drm/amdgpu/sdma5: fix a sdma potential hang in VK_Examples test
[why]
When page fault happens, it could lead to sdma hang is RESP_MODE =
0 for non-PRT case.
[how]
Setting SDMAx_UTCL1_CNTL.RESP_MODE to 0b011 to avoid SDMA halt.
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: tiancyin <tianci.yin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Mon, 22 Apr 2019 13:06:22 +0000 (21:06 +0800)]
drm/amd/powerplay: remove uvd_gated/vce_gated from smu_power_context (v2)
It's not needed for navi.
v2: remove unused variable (Alex)
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Thu, 18 Apr 2019 07:55:27 +0000 (15:55 +0800)]
drm/amdgpu/nv: set vcn pg flag
Enable VCN power gating by default.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Thu, 18 Apr 2019 10:11:55 +0000 (18:11 +0800)]
drm/amdgpu: enable vcn dpm scheme for navi
On navi1x, vcn dpm scheme was merged into powergating scheme.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Thu, 18 Apr 2019 09:37:14 +0000 (17:37 +0800)]
drm/amdgpu/vcn2: don't access register when power gated
It will cause bus hang to access register UVD_STATUS
when VCN is in the state of power gated.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kenneth Feng [Thu, 18 Apr 2019 02:00:48 +0000 (10:00 +0800)]
drm/amd/powerplay: add new interface for vcn powergating
add new interface for vcn powrergating and vcn dpm as well.
Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kenneth Feng [Tue, 16 Apr 2019 08:47:10 +0000 (16:47 +0800)]
drm/amd/powerplay: enable vcn powergating v2
enable vcn powergating in driver for navi10
v2: set vcn pg bit according to AMD_PG_SUPPORT_VCN flag
Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Thu, 18 Apr 2019 08:20:10 +0000 (16:20 +0800)]
drm/amdgpu/vcn2: notify SMU power up/down VCN
For sw control power gating, it needs notify SMU to power up/down VCN
when enter/exit working state.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Tue, 16 Apr 2019 09:27:41 +0000 (17:27 +0800)]
drm/amdgpu/gfx10: fix issues for suspend/resume
1). use PREEMPT_QUEUE instead of RESET_QUEUE for gfx ring disablement.
2). Need wait for unmapping queue done before continue execution.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Tianci Yin <tianci.yin@amd.com>
Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Thu, 30 May 2019 04:18:01 +0000 (23:18 -0500)]
drm/amd/powerplay: set dpm_enabled flag but don't enable vcn dpm
This patch sets dpm_enabled flag but don't enable vcn dpm, because vcn dpm
doesn't work so far and we needs to enable the sysfs interfaces.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Acked-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kenneth Feng [Tue, 16 Apr 2019 08:33:43 +0000 (16:33 +0800)]
drm/amd/powerplay: update smu11_driver_if_navi10.h
update the smu11_driver_if_navi10.h since navi10 smu fw
update to 42.15.0
Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojie Yuan [Mon, 1 Apr 2019 13:44:21 +0000 (21:44 +0800)]
drm/amdgpu/gfx10: fix resume failure when enabling async gfx ring
'adev->in_suspend' code path is missing in gfx_v10_0_gfx_init_queue()
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tianci Yin [Thu, 11 Apr 2019 10:59:07 +0000 (18:59 +0800)]
drm/amdgpu: disable some gfx light sleep
temporarily disable to avoid s3 test failure.
s3 test failure log:
"[drm:amdgpu_job_timedout [amdgpu]] *ERROR* ring sdma0 timeout,
signaled seq=8278, emitted seq=8281"
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Tianci Yin <tianci.yin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tianci Yin [Wed, 3 Apr 2019 08:38:31 +0000 (16:38 +0800)]
drm/amdgpu/gfx10: update gfx golden settings
add new registers: mmCGTT_SPI_CLK_CTRL, mmDB_DEBUG3 and
mmGL2C_CGTT_SCLK_CTRL.
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Tianci Yin <tianci.yin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Thu, 30 May 2019 04:15:54 +0000 (23:15 -0500)]
drm/amd/powerplay: do not set dpm_enabled flag before VCN/DCN DPM is workable
This dpm_enabled flag will be recognized as the VCN DPM enabled as well. In fact
VCN/DCN DPM on Navi10 is not good so far, so we cannot enable it for now.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Acked-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kenneth Feng [Thu, 4 Apr 2019 04:50:23 +0000 (12:50 +0800)]
drm/amd/powerplay: fix the incorrect type of pptable
This patch is to fix the incorrect type of pptable, otherwise, the data will be
totally wrong in parsing phase.
Signed-off-by: Kenneth Feng <Kenneth.Feng@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Sun, 31 Mar 2019 08:08:21 +0000 (16:08 +0800)]
drm/amd/powerplay: don't include the smu11 driver if header in smu v11 (v2)
This header is actually for each asic, so we should not include in smu_v11_0.c.
And rename the one for navi10.
v2: add hack for XGMI (Alex)
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Mon, 1 Apr 2019 10:06:36 +0000 (18:06 +0800)]
drm/amd/powerplay: move getting MAX_FAN_RPM value to asic level
Getting MAX_FAN_RPM value needs to be read by pptable, so it should be moved to
asic level.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Sun, 31 Mar 2019 07:53:42 +0000 (15:53 +0800)]
drm/amd/powerplay: introduce smu power source type to handle AC/DC source for each asic
This patch introduces new smu power source type, it's to handle the different
AC/DC source defines for each asic with the same smu ip.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Sun, 31 Mar 2019 07:15:49 +0000 (15:15 +0800)]
drm/amd/powerplay: move Watermarks_t uses into asic level
This patch moves the rest of Watermarks_t uses into asic level. It's to avoid
the conflicts with different asic.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Sun, 31 Mar 2019 06:53:23 +0000 (14:53 +0800)]
drm/amd/powerplay: move SmuMetrics_t uses into asic level
This patch moves the rest of SmuMetrics_t uses into asic level. It's to avoid the
conflicts with different asic.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Sun, 31 Mar 2019 05:25:04 +0000 (13:25 +0800)]
drm/amd/powerplay: move PPTable_t uses into asic level
This patch moves the rest of PPTable_t uses into asic level. It's to avoid the
conflicts with different asic.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Sun, 31 Mar 2019 04:49:11 +0000 (12:49 +0800)]
drm/amd/powerplay: use the table size member in the structure instead of getting directly
This patch uses the table size member in the structure instead of getting
directly, because the table is different in each asic.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Sun, 31 Mar 2019 04:02:00 +0000 (12:02 +0800)]
drm/amd/powerplay: modify smu_update_table to use SMU_TABLE_xxx as the input
Table id may be different for each asic, so it's good to use this as the input
for common interface.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Mon, 22 Apr 2019 19:06:42 +0000 (14:06 -0500)]
drm/amd/powerplay/smu11: remove smu_update_table_with_arg
Nothing was using it. Just replace with smu_update_table
which is what everything was using via a wrapper anyway.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Sun, 31 Mar 2019 03:53:28 +0000 (11:53 +0800)]
drm/amd/powerplay: add tables_init interface for each asic
The smc tables defines should be in the asic level.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Fri, 29 Mar 2019 10:07:23 +0000 (18:07 +0800)]
drm/amd/powerplay: init table_count for smu tables on asic level
TABLE_COUNT should be inited in asic level. Because the value may be different
on each asic even on the same ip.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Fri, 29 Mar 2019 09:52:11 +0000 (17:52 +0800)]
drm/amd/powerplay: introduce smu table id type to handle the smu table for each asic
This patch introduces new smu table type, it's to handle the different smu table
defines for each asic with the same smu ip.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Thu, 30 May 2019 04:14:33 +0000 (23:14 -0500)]
drm/amd/powerplay: introduce smu feature type to handle feature mask for each asic
This patch introduces new smu feature type, it's to handle the different feature
mask defines for each asic with the same smu ip.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Sun, 24 Mar 2019 11:22:07 +0000 (19:22 +0800)]
drm/amd/powerplay: introduce smu clk type to handle ppclk for each asic
This patch introduces new smu clk type, it's to handle the different ppclk
defines for each asic with the same smu ip.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Mon, 1 Apr 2019 07:32:48 +0000 (15:32 +0800)]
drm/amdgpu: enable sw smu driver for navi10 by default
Navi10 will use sw smu driver for dynamic power managment,
while vega20 could also use sw smu driver when amdgpu_dpm is
set to 2
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kenneth Feng [Thu, 28 Mar 2019 09:14:42 +0000 (17:14 +0800)]
drm/amd/powerplay: enable DCEFCLK dpm support
Enabale DCEFCLK dpm on navi10
Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kenneth Feng [Thu, 28 Mar 2019 02:54:16 +0000 (10:54 +0800)]
drm/amd/powerplay: gfxoff-seperate the Vega20 case
seperate the Vega20 case from navi10 for gfxoff so that gfxoff
won't be allowed on Vega20
Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kenneth Feng [Wed, 27 Mar 2019 09:10:09 +0000 (17:10 +0800)]
drm/amd/amdgpu: fw version check with gfxoff
1. check the firmware version when enabling gfxoff
2. overwrite the pptable to make sure gfxoff is really
enabled on navi10
Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kenneth Feng [Wed, 27 Mar 2019 03:46:31 +0000 (11:46 +0800)]
drm/amd: add gfxoff support on navi10
add the gfxoff interface to navi10,it's disabled by default.
Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kevin Wang [Wed, 20 Mar 2019 07:10:29 +0000 (15:10 +0800)]
drm/amd/powerplay: add allowed feature mask for navi10
add smu feature mask:
1.FEATURE_DPM_PREFETCHER_BIT
2.FEATURE_DPM_PREFETCHER_BIT
3.FEATURE_ATHUB_PG
Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kevin Wang [Tue, 19 Mar 2019 09:20:09 +0000 (17:20 +0800)]
drm/amd/powerplay: optimization feature mask function for asic
1.change function return value type: from "unallowed" to "allowed"
2.replace feature mask number with feature macro, the code will clear.
Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kevin Wang [Tue, 19 Mar 2019 03:00:41 +0000 (11:00 +0800)]
drm/amd/powerplay: remove duplicate code from smu hw init
remove duplicate code (un-used) in smu
Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kevin Wang [Fri, 21 Jun 2019 15:49:22 +0000 (10:49 -0500)]
drm/amd/powerplay: implement smc firmware v2.1 for smu11
1.add smc_firmware_header_v2_1 hfirmware support, support more pptable in smc firmware.
2.optimization current pptable load framework.
3.rename read_pptable_from_vbios with setup_pptable.
Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kevin Wang [Mon, 11 Mar 2019 06:15:37 +0000 (14:15 +0800)]
drm/amd/powerplay: add smu11 smu_if_version check for navi10
add smu11 fw version check for navi10
Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kevin Wang [Tue, 5 Mar 2019 07:42:16 +0000 (15:42 +0800)]
drm/amd/powerplay: move the function of is_dpm_running to asic file
the function os is_dpm_running is aisc related function,
so move them to asic file.
Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kevin Wang [Tue, 5 Mar 2019 06:16:12 +0000 (14:16 +0800)]
drm/amd/powerplay: move the function of read_sensor to asic file
The read_sensor functions has asic related parts code,
so move them to asic file to implement.
Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kevin Wang [Thu, 30 May 2019 04:11:28 +0000 (23:11 -0500)]
drm/amd/powerplay: move the function of uvd&vce dpm to asic file
Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kevin Wang [Thu, 30 May 2019 04:09:06 +0000 (23:09 -0500)]
drm/amd/powerplay: move the function of get[set]_power_profile to asic file
The callback of get[set]_power_profile is asic related function,
so move theme into vega20_ppt file.
Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kevin Wang [Mon, 4 Mar 2019 11:50:02 +0000 (19:50 +0800)]
drm/amd/powerplay: move the funciton of conv_profile_to_workload to asic file
the function of conv_profile_to_workload is asic related function,
so move them into vega20_ppt file
Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kenneth Feng [Mon, 11 Mar 2019 08:06:03 +0000 (16:06 +0800)]
drm/amd/powerplay: enable power features
the below smu related power features can be enabled now.
1.Prefetcher
2.GFX DPM
3.SOCCLK DPM
4.MP0CLK DPM
5.LCLK DPM
6.GFX ULV
7.CG
8.PPT
9.TDC
10.GFX EDC
11.VR0HOT
12.Fan Control
13.Thermal Control
14.LED Display
15.MMHub PG
16.ATHub PG
Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Wed, 20 Feb 2019 12:20:00 +0000 (20:20 +0800)]
drm/amd/powerplay: skip od feature on navi10 for the moment
OD feature isn't enabled on navi10 so skip it for the moment.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Wed, 20 Feb 2019 12:17:23 +0000 (20:17 +0800)]
drm/amd/powerplay: modify the feature mask to enable gfx/soc dpm
So far, the gfx/soc dpm is enabled with feature mask set.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Wed, 20 Feb 2019 12:12:22 +0000 (20:12 +0800)]
drm/amd/powerplay: introduce the function to load the soft pptable for navi10 (v2)
Driver is able to load soft pptable from smc bin file with this function. We
stored the soft pptable in the bottom of smc.bin that the version is v2.
v2: remove is_fw_v2_0 flag.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Wed, 20 Feb 2019 12:05:11 +0000 (20:05 +0800)]
drm/amd/powerplay: smu needs to be initialized after rlc in direct mode
For gfx 10, rlc firmware loading relies on smu firmware is loaded firstly, so in
direct type, it has to load smc ucode here before rlc. And meanwhile, the smu
initialization has to move after rlc, otherwise, smu message will get failure
during the handshake with rlc and smu.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Wed, 20 Feb 2019 12:00:21 +0000 (20:00 +0800)]
drm/amdgpu: fix the issue of checking on message mapping
The navi10_message_map[index] scope should be in PPSMC_Message_Count not in
SMU_MSG_MAX_COUNT.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Wed, 20 Feb 2019 11:43:36 +0000 (19:43 +0800)]
drm/amdgpu: bump smc firmware header version to v2 (v2)
This patch bumps smc firmware header version to v2 for storing soft pptable.
v2: fix the typo, and add prints for v2 header
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Wed, 13 Feb 2019 02:44:50 +0000 (10:44 +0800)]
drm/amd/powerplay: update smu11 driver if header for navi10 (v2)
This patch updates smu11 driver if header for navi10 to match 42.09.00 smu
firmware.
v2: clean up comments
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kenneth Feng [Sat, 2 Feb 2019 03:43:12 +0000 (11:43 +0800)]
drm/amd/powerplay: enable backdoor smu fw loading (v2)
enable backdoor smu fw loading on navi10
v2: squash in define fix (Alex)
Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Thu, 31 Jan 2019 13:11:11 +0000 (21:11 +0800)]
drm/amd/powerplay: move bootup value before read pptable from vbios
In navi10, we need read the pp_table_id from bootup value, then decide whether
use load the soft pptable.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Thu, 31 Jan 2019 12:49:59 +0000 (20:49 +0800)]
drm/amd/powerplay: add navi10 smc ucode init and navi10 ppt functions setting
This patch adds navi10 smc ucode init and ppt functions setting.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Thu, 31 Jan 2019 12:32:54 +0000 (20:32 +0800)]
drm/amd/powerplay: set smu v11 funcs for navi10
Naiv10 also uses smu v11 functions.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Thu, 31 Jan 2019 11:46:26 +0000 (19:46 +0800)]
drm/amd/powerplay: introduce the navi10 pptable implementation
This patch introduces the navi10 pptable implementation, so far it is already
has firmware loading, pptable side loading, writing back to smc, and feature
mask enabling.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Thu, 31 Jan 2019 13:03:24 +0000 (21:03 +0800)]
drm/amd/powerplay: fix the mp/smuio header for navi10
SMU11 should use mp11 and smuio11 headers.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Thu, 31 Jan 2019 11:21:25 +0000 (19:21 +0800)]
drm/amd/powerplay: update smu 11 driver if header for navi10
This patch updates smu 11 driver if header for navi10.
UVD/VCE won't be used for navi10. Here, reverve them for vega20.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Thu, 31 Jan 2019 11:19:48 +0000 (19:19 +0800)]
drm/amd/powerplay: update smu v11 ppsmc header
This patch updates smu v11 ppsmc header for navi10.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Wed, 19 Jul 2017 01:45:26 +0000 (09:45 +0800)]
drm/amdgpu: add to set navi ip blocks
Set the IPs for navi10 in early_init like other asics.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Fri, 19 Apr 2019 22:58:21 +0000 (17:58 -0500)]
drm/amdgpu: add Navi10 pci ids
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Philip Cox [Thu, 30 May 2019 04:03:45 +0000 (23:03 -0500)]
drm/amdkfd: Add navi10 support to amdkfd. (v3)
KFD (kernel fusion driver) is the kernel driver
for the compute backend for usermode compute
stack.
v2: squash in updates (Alex)
v3: squash in rebase fixes (Alex)
Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
Signed-off-by: Philip Cox <Philip.Cox@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Fri, 8 Jun 2018 10:10:57 +0000 (18:10 +0800)]
drm/amdgpu: update golden setting programming logic
Since from soc15, make sure only AndMasked bit get changed
when applied or_mask
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Le Ma <Le.Ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
projects / openwrt / staging / blogic.git / log