Haojian Zhuang [Wed, 31 May 2017 04:42:10 +0000 (12:42 +0800)]
hikey: fix uninitialized variable in ddr code
Fix uninitliazed variable in ddr driver code.
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
davidcunado-arm [Tue, 30 May 2017 09:56:47 +0000 (10:56 +0100)]
Merge pull request #949 from antonio-nino-diaz-arm/an/printf-memory
Reduce code size when building with Trusted Board Boot enabled
davidcunado-arm [Thu, 25 May 2017 10:26:22 +0000 (11:26 +0100)]
Merge pull request #950 from danh-arm/hz/hikey
HiKey v3
danh-arm [Wed, 24 May 2017 16:37:50 +0000 (17:37 +0100)]
Merge pull request #951 from dp-arm/dp/compiler-rt-cleanup
compiler-rt: Remove unused int_util.[ch] files
Haojian Zhuang [Wed, 24 May 2017 01:36:49 +0000 (09:36 +0800)]
hikey: add hikey support
Add the description on hikey and how to build.
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Haojian Zhuang [Wed, 24 May 2017 00:49:26 +0000 (08:49 +0800)]
hikey: support BL31
Support BL31 and PSCI. Enable multiple cores in PSCI.
Change-Id: I66c39e1e9c4c45ac41a0142ed2070d79a3ac5ba3
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Signed-off-by: Dan Handley <dan.handley@arm.com>
Haojian Zhuang [Wed, 24 May 2017 00:48:57 +0000 (08:48 +0800)]
Cortex-A53: add some bit definitions
Add some bit definitions of CPUACTLR register in Cortex-A53
CPU library.
Change-Id: I142fd8ac4b06dd651a32e22951e71cdebbea123a
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Signed-off-by: Dan Handley <dan.handley@arm.com>
Haojian Zhuang [Wed, 24 May 2017 00:47:49 +0000 (08:47 +0800)]
hikey: support BL2
BL2 is used to load BL31 and SCP_BL2. In HiKey platform, SCP_BL2
is the mcu firmware that is used to scale cpu frequency and switch
low power mode.
Change-Id: I1621aa65bea989fd125ee8502fd56ef72362bf97
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Signed-off-by: Dan Handley <dan.handley@arm.com>
Haojian Zhuang [Wed, 24 May 2017 00:45:05 +0000 (08:45 +0800)]
hikey: support BL1
Initialize regulators, pins and eMMC in BL1. Only SRAM could be used in BL1.
So BL2 will be loaded from eMMC into SRAM later.
Change-Id: I8e7ef82ffa29a3c647c9d2d2981e8759ee85d833
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Signed-off-by: Dan Handley <dan.handley@arm.com>
dp-arm [Wed, 24 May 2017 14:23:02 +0000 (15:23 +0100)]
compiler-rt: Remove unused int_util.[ch] files
Change-Id: I32fc523e3178b7e50191682241904d52499ff708
Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
danh-arm [Wed, 24 May 2017 13:56:59 +0000 (14:56 +0100)]
Merge pull request #941 from dp-arm/dp/clang
Allow TF to be built using clang or ARM Compiler 6
dp-arm [Mon, 15 May 2017 12:50:51 +0000 (13:50 +0100)]
docs: Add note on how to build TF using clang or armclang
Change-Id: I92fd2fb920fcfc31bfcdadae787d8c84c5ca463b
Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
dp-arm [Wed, 3 May 2017 15:30:32 +0000 (16:30 +0100)]
build: Introduce ARM Compiler 6 support
Only the compiler is switched to ARM Compiler 6. The assembler and linker
are provided by the GCC toolchain.
ARM Compiler 6 is used to build TF when the base name of the path assigned
to `CC` matches the string 'armclang'.
`CROSS_COMPILE` is still needed and should point to the appropriate
GCC toolchain.
Tested with ARM CC 6.7.
Change-Id: Ib359bf9c1e8aeed3f662668e44830864f3fe7b4a
Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
dp-arm [Tue, 2 May 2017 11:00:08 +0000 (12:00 +0100)]
build: Introduce clang support
Only the compiler is switched to clang. The assembler and linker are
provided by the GCC toolchain.
clang is used to build TF when the base name of the path assigned to
`CC` contains the string 'clang'.
`CROSS_COMPILE` is still needed and should point to the appropriate
GCC toolchain.
Tested with clang 3.9.x and 4.0.x.
Change-Id: I53236d64e3c83ad27fc843bae5fcdae30f2e325e
Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
dp-arm [Tue, 2 May 2017 10:09:11 +0000 (11:09 +0100)]
build: Introduce HOSTCC flag
Tools are built using the compiler specified in `HOSTCC` instead of
reusing the `CC` variable. By default, gcc is used.
Change-Id: I83636a375c61f4804b4e80784db9d061fe20af87
Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
dp-arm [Wed, 3 May 2017 15:30:54 +0000 (16:30 +0100)]
Switch default C environment from c99 to gnu99
Since TF uses GCC extensions, switch the C environment
from c99 to gnu99.
This change allows armclang to build TF.
Change-Id: Iaacb2726ba1458af59faf607ae9405d6eedb9962
Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
dp-arm [Wed, 3 May 2017 11:14:10 +0000 (12:14 +0100)]
plat/arm: Compile out impossible conditional for AArch32
Since ARM_DRAM2_BASE is above the 32-bit limit, the condition
is always false. Wrap this condition in an ifndef to avoid
warnings during compilation.
Change-Id: Ideabb6c65de6c62474ed03eb29df4b049d5316be
Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
dp-arm [Tue, 2 May 2017 11:39:19 +0000 (12:39 +0100)]
Remove plat_match_rotpk reference
This function was removed long ago. Remove remaining
pragma reference.
Change-Id: I66c556863d47dc17d2ffdc6c23aa524df6aade80
Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
dp-arm [Tue, 2 May 2017 11:35:24 +0000 (12:35 +0100)]
fvp: Remove unnecessary default case
The default case is impossible to hit as the `power_level`
is already checked earlier. Avoids a clang warning.
Change-Id: I707463c843adc748ee9aa1d2313f9ab7dab3a8ab
Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
dp-arm [Tue, 2 May 2017 10:49:33 +0000 (11:49 +0100)]
Include missing header in arm_bl2_setup.c
Change-Id: I4108ce8d1fe7d3fd51a5a96d43b9134c23b8399b
Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
dp-arm [Fri, 5 May 2017 11:21:03 +0000 (12:21 +0100)]
Use a callee-saved register to be AAPCS-compliant
x8 is not a callee-saved register and can be corrupted.
Use x19 instead to be AAPCS-compliant.
Fixes ARM-software/tf-issues#478
Change-Id: Ib4f114c36f4c11351ae856f953c45dca92b27c3b
Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
danh-arm [Wed, 24 May 2017 13:20:20 +0000 (14:20 +0100)]
Merge pull request #938 from masahir0y/tools_share
Collect headers shared between TF and host-tools into include/tools_share
Antonio Nino Diaz [Wed, 24 May 2017 13:11:07 +0000 (14:11 +0100)]
mbedtls: Use `MBEDTLS_SHA256_SMALLER` in ARM platforms
This options enables an implementation of SHA-256 that has a smaller
code footprint (~1.6 KB less) but is also ~30% slower. For ARM
platforms, code size is currently considered more important than
execution speed in the mbed TLS crypto module.
Added a small note about this option to the documentation of the
authentication framework.
Change-Id: I4c0b221ea5d3466465261316ba07b627fa01b233
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Antonio Nino Diaz [Fri, 19 May 2017 10:37:22 +0000 (11:37 +0100)]
mbedtls: Use `tf_snprintf` instead of `snprintf`
The Trusted Firmware uses a subset of the APIs provided by mbed TLS.
This subset internally uses `snprintf`, but the only format specifier
used is '%d', which is supported by `tf_snprintf`.
This patch makes mbed TLS use `tf_snprintf` instead of `snprintf`,
saving 3 KB in both debug and release builds when TBBR is enabled.
Change-Id: I7f992a21015930d7c0f4660e7a28ceefd60b9597
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Antonio Nino Diaz [Wed, 17 May 2017 14:34:22 +0000 (15:34 +0100)]
Introduce `tf_snprintf`
This is a reduced version of `snprintf` that only supports formats '%d',
'%i' and '%u'. It can be used when the full `snprintf` is not needed in
order to save memory. If it finds an unknown format specifier, it
prints an error message and panics.
Change-Id: I2cb06fcdf74cda2c43caf73ae0762a91499fc04e
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Masahiro Yamada [Tue, 23 May 2017 10:41:36 +0000 (19:41 +0900)]
FVP,Juno: switch FVP and Juno to use generic TBBR OID header
The header tbbr_oid.h contains OIDs obtained by ARM Ltd.
so there is no good reason to use platform_oid.h
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada [Mon, 22 May 2017 03:11:24 +0000 (12:11 +0900)]
cert: move platform_oid.h to include/tools_share for all platforms
Platforms aligned with TBBR are supposed to use their own OIDs, but
defining the same macros with different OIDs does not provide any
value (at least technically).
For easier use of TBBR, this commit allows platforms to reuse the OIDs
obtained by ARM Ltd. This will be useful for non-ARM vendors that
do not need their own extension fields in their certificate files.
The OIDs of ARM Ltd. have been moved to include/tools_share/tbbr_oid.h
Platforms can include <tbbr_oid.h> instead of <platform_oid.h> by
defining USE_TBBR_DEFS as 1. USE_TBBR_DEFS is 0 by default to keep the
backward compatibility.
For clarification, I inserted a blank line between headers from the
include/ directory (#include <...>) and ones from a local directory
(#include "..." ).
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada [Mon, 8 May 2017 09:29:03 +0000 (18:29 +0900)]
fip: move headers shared between TF and fiptool to include/tools_share
Some header files need to be shared between TF and host programs.
For fiptool, two headers are copied to the tools/fiptool directory,
but it looks clumsy.
This commit introduces a new directory, include/tools_share, which
collects headers that should be shared between TF and host programs.
This will clarify the interface exposed to host tools. We should
add new headers to this directory only when we really need to do so.
For clarification, I inserted a blank line between headers from the
include/ directory (#include <...>) and ones from a local directory
(#include "..." ).
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada [Tue, 23 May 2017 14:45:01 +0000 (23:45 +0900)]
Build: fix assert_boolean implementation
The current assert_boolean does not work with variables assigned with
'=' flavor instead of ':='.
For example,
FOO = $(BAR)
BAR := 1
Here, $(value FOO) is evaluated to $(BAR), not 1. This is not what
we expect. While I am here, I simplified the implementation.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
danh-arm [Mon, 22 May 2017 14:31:37 +0000 (15:31 +0100)]
Merge pull request #947 from davidcunado-arm/dc/update_userguide
Migrate to Linaro Release 17.01
danh-arm [Mon, 22 May 2017 14:29:12 +0000 (15:29 +0100)]
Merge pull request #945 from antonio-nino-diaz-arm/an/xlat-dependency
xlat: Fix missing header file dependency
danh-arm [Mon, 22 May 2017 14:28:17 +0000 (15:28 +0100)]
Merge pull request #939 from dp-arm/dp/AArch32_tbbr
Add TBBR and FWU support for AArch32
danh-arm [Mon, 22 May 2017 14:25:53 +0000 (15:25 +0100)]
Merge pull request #944 from danh-arm/jl/spdx-license
Add note about SPDX identifiers in license.md
davidcunado-arm [Fri, 19 May 2017 09:54:23 +0000 (10:54 +0100)]
Merge pull request #936 from antonio-nino-diaz-arm/an/assert-mem
Simplify assert() to reduce memory usage
David Cunado [Fri, 19 May 2017 08:27:19 +0000 (09:27 +0100)]
Migrate to Linaro Release 17.01
This Linaro release updates just the binaries:
Linaro binaries upgraded 16.12 --> 17.01
The toolchain remains at 5.3-2015.05 (gcc 5.3) for both AArch64
and AArch32.
The ARM TF codebase has been tested against these new binaries. This patch
updates the User Guide to reflect that the 17.01 release is now a supported
Linaro Release.
Change-Id: I83c579dabd3fa9861ba0d41507036efbd87abcb5
Signed-off-by: David Cunado <david.cunado@arm.com>
Antonio Nino Diaz [Wed, 17 May 2017 15:25:40 +0000 (16:25 +0100)]
xlat: Fix missing header file dependency
xlat_tables_arch.h uses the platform macro `PLAT_VIRT_ADDR_SPACE_SIZE`.
This macro is defined in xlat_tables_private.h only if the platform
still uses the deprecated `ADDR_SPACE_SIZE`.
Change-Id: I1c3b12ebd96bdfe9bf94b26d440c03bc0f8c0b24
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Jilayne Lovejoy [Tue, 16 May 2017 14:56:09 +0000 (08:56 -0600)]
Add note about SPDX identifiers in license.md
Added note regarding use of SPDX identifiers following this example:
https://github.com/pocoproject/poco/blob/develop/LICENSE
Change-Id: I22a280bce57f9145e4786c5ad32f663c2c9c6545
Signed-off-by: Jilayne Lovejoy <jilayne.lovejoy@arm.com>
Signed-off-by: Dan Handley <dan.handley@arm.com>
danh-arm [Tue, 16 May 2017 17:05:07 +0000 (18:05 +0100)]
Merge pull request #942 from soby-mathew/sm/fix_juno_build_err
Juno: Fix AArch32 sp_min build
Soby Mathew [Tue, 16 May 2017 09:51:39 +0000 (10:51 +0100)]
Juno: Fix AArch32 sp_min build
The commit
abd2aba99ef108e0d0bb5d71c0b6e9c47ca26377 introduced a
regression to the AArch32 sp_min Juno build. This patch fixes that.
Change-Id: I4b141717684d6aee60c761ea17f23170aa6708c3
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
danh-arm [Tue, 16 May 2017 10:00:07 +0000 (11:00 +0100)]
Merge pull request #937 from rockchip-linux/rk3328_assert
rockchip: rk3328: Add assert check in pmu.c
danh-arm [Tue, 16 May 2017 09:57:16 +0000 (10:57 +0100)]
Merge pull request #935 from davidcunado-arm/dc/mbed_api
mbedtls: Namespace update for TF specific macros
danh-arm [Tue, 16 May 2017 09:56:51 +0000 (10:56 +0100)]
Merge pull request #934 from sandrine-bailleux-arm/sb/break-headers-circular-dep
Break circular dependency in FVP and Nvidia header files
Antonio Nino Diaz [Tue, 16 May 2017 08:52:02 +0000 (09:52 +0100)]
Simplify assert() to reduce memory usage
The behaviour of assert() now depends on the value of the new optional
platform define `PLAT_LOG_LEVEL_ASSERT`. This defaults to `LOG_LEVEL` if
not defined by the platform.
- If `PLAT_LOG_LEVEL_ASSERT` >= `LOG_LEVEL_VERBOSE`, it prints the file
name, line and asserted expression.
- If `PLAT_LOG_LEVEL_ASSERT` >= `LOG_LEVEL_INFO`, it prints the file
name and line.
- If not, it doesn't print anything.
Note the old behaviour was to print the function name whereas now it
prints the file name. This reduces memory usage because the file name is
shared between all assert calls in a given file. Also, the default
behaviour in debug builds is to no longer print the asserted expression,
greatly reducing the string usage.
For FVP debug builds this change saves approximately:
No TBBR TBBR
BL1 1.6 KB 2.2 KB
BL2 1.7 KB 2.1 KB
BL31 2.6 KB 3.3 KB
Change-Id: I2947569d593df0b25611dc3c7a6096f42155c115
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
dp-arm [Wed, 10 May 2017 15:28:40 +0000 (16:28 +0100)]
Align tf_printf implementation between AArch32 and AArch64
No need for these wrapper functions anymore. The compiler-rt builtins
provide runtime support for 64-bit division and modulo operations.
Change-Id: Ib785d37c86f0c82ebd34c35023a4c1822c03e7df
Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
Yatharth Kochar [Tue, 22 Nov 2016 11:06:03 +0000 (11:06 +0000)]
AArch32: Add BL2U support
Add support for firmware upgrade on AArch32.
This patch has been tested on the FVP models.
NOTE: Firmware upgrade on Juno AArch32 is not currently supported.
Change-Id: I1ca8078214eaf86b46463edd14740120af930aec
Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
Co-Authored-By: Yatharth Kochar <yatharth.kochar@arm.com>
dp-arm [Wed, 15 Feb 2017 11:07:55 +0000 (11:07 +0000)]
AArch32: Add `TRUSTED_BOARD_BOOT` support
This patch adds `TRUSTED_BOARD_BOOT` support for AArch32 mode.
To build this patch the "mbedtls/include/mbedtls/bignum.h"
needs to be modified to remove `#define MBEDTLS_HAVE_UDBL`
when `MBEDTLS_HAVE_INT32` is defined. This is a workaround
for "https://github.com/ARMmbed/mbedtls/issues/708"
NOTE: TBBR support on Juno AArch32 is not currently supported.
Change-Id: I86d80e30b9139adc4d9663f112801ece42deafcf
Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
Co-Authored-By: Yatharth Kochar <yatharth.kochar@arm.com>
tony.xie [Mon, 15 May 2017 02:36:14 +0000 (10:36 +0800)]
rockchip: rk3328: Add assert check in pmu.c
Add assert() check for cpuson_flags[] and cpuson_entry_point[].
Change-Id: I971fe54c2baa3b4514a3979042341220f5e20901
Signed-off-by: tony.xie <tony.xie@rock-chips.com>
davidcunado-arm [Fri, 12 May 2017 21:48:34 +0000 (22:48 +0100)]
Merge pull request #930 from antonio-nino-diaz-arm/an/fixes-xlat-v2
Minor fixes to the xlat tables lib v2
David Cunado [Tue, 9 May 2017 23:29:54 +0000 (00:29 +0100)]
Migrate ARM platforms to use TF_MBEDTLS_KEY_ALG
A previous patch superseded the MBEDTLS_KEY_ALG. This patch updates
the ARM platforms to use the new TF_MBEDTLS_KEY_ALG define.
Change-Id: Ie0e1bc272e127e879ac58e7cfcbe268751d7688e
Signed-off-by: David Cunado <david.cunado@arm.com>
David Cunado [Mon, 8 May 2017 08:48:34 +0000 (09:48 +0100)]
mbedtls: Complete namespace for TF specific macros
This patch renames MBEDTLS_KEY_ALG to TF_MBEDTLS_KEY_ALG. This
completes the migration of TF specific macros so that they do not
have the MBEDTLS_ suffix (see arm-trusted-firmware#874).
Change-Id: Iad7632477e220b0af987c4db3cf52229fb127d00
Signed-off-by: David Cunado <david.cunado@arm.com>
David Cunado [Wed, 10 May 2017 15:38:44 +0000 (16:38 +0100)]
mbedtls: Namespace for TF specific macros
An earlier patch (arm-trusted-firmware#874) migrated MBEDTLS_ suffixed
macros to have a TBBR_ suffix to avoid any potential clash with future
mbedtls macros.
But on reflection the TBBR_ suffix could be confusing as the macros
are used to drive TF-specific configuration of mbedtls. As such
this patch migrates these macros from TBBR_suffix to TF_MBEDTLS_
suffix which more accurately conveys their use.
Change-Id: Ic87642b653ceeaa03d62f724976abd5e12e867d4
Signed-off-by: David Cunado <david.cunado@arm.com>
Soby Mathew [Thu, 30 Mar 2017 13:42:54 +0000 (14:42 +0100)]
AArch32: Rework SMC context save and restore mechanism
The current SMC context data structure `smc_ctx_t` and related helpers are
optimized for case when SMC call does not result in world switch. This was
the case for SP_MIN and BL1 cold boot flow. But the firmware update usecase
requires world switch as a result of SMC and the current SMC context helpers
were not helping very much in this regard. Therefore this patch does the
following changes to improve this:
1. Add monitor stack pointer, `spmon` to `smc_ctx_t`
The C Runtime stack pointer in monitor mode, `sp_mon` is added to the
SMC context, and the `smc_ctx_t` pointer is cached in `sp_mon` prior
to exit from Monitor mode. This makes is easier to retrieve the
context when the next SMC call happens. As a result of this change,
the SMC context helpers no longer depend on the stack to save and
restore the register.
This aligns it with the context save and restore mechanism in AArch64.
2. Add SCR in `smc_ctx_t`
Adding the SCR register to `smc_ctx_t` makes it easier to manage this
register state when switching between non secure and secure world as a
result of an SMC call.
Change-Id: I5e12a7056107c1701b457b8f7363fdbf892230bf
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
dp-arm [Thu, 4 May 2017 11:15:35 +0000 (12:15 +0100)]
Hook up LLVM compiler-rt in the build system
This patch enables compiler-rt for the AArch32 target. The code is
not used for AArch64 as the architecture supports the 64-bit division
and modulo operations natively.
Change-Id: I1703a92872b0bb56ac0b98c67193830683963b13
Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
dp-arm [Thu, 4 May 2017 11:12:06 +0000 (12:12 +0100)]
Import builtins from LLVM compiler-rt project
These are needed to provide division and modulo operations
for the AArch32 target.
This code is entirely unmodified. Imported from compiler-rt
master branch as of May 4 2017.
Change-Id: I001e1809f2afd4bf8d4cc3d2296798809f607144
Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
Sandrine Bailleux [Thu, 11 May 2017 13:30:20 +0000 (14:30 +0100)]
Tegra: Break circular dependency in platform header files
For SoCs T132 and T210, the header file 'platform_def.h' used to include
'tegra_def.h' and vice versa. This patch breaks this circular dependency
by making 'tegra_def.h' independent.
Change-Id: I45a00a84e6ab8b93d5e9242a9ff65f03e9102a96
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Sandrine Bailleux [Thu, 11 May 2017 13:19:55 +0000 (14:19 +0100)]
FVP: Break circular dependency in platform header files
We used to have the following circular dependency in the FVP platform
header files:
+-> arm_def.h ---> platform_def.h ---> fvp_def.h --+
|__________________________________________________|
This patch breaks it by not including 'arm_def.h' from 'fvp_def.h'.
Change-Id: I280d906559e3343dd38764029e77c0ea768b4fec
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
davidcunado-arm [Thu, 11 May 2017 17:26:02 +0000 (18:26 +0100)]
Merge pull request #933 from davidcunado-arm/dc/add_spdx
Add missing SPDX header
David Cunado [Thu, 11 May 2017 16:30:06 +0000 (17:30 +0100)]
Add missing SPDX header
A new file added as part of arm-trusted-firmware#927 was missing the
SPDX license identifier - this patch adds the missing identifier.
Change-Id: Id1355f2bdca930b7e65bb54eff7e6c764ebb0d96
Signed-off-by: David Cunado <david.cunado@arm.com>
davidcunado-arm [Thu, 11 May 2017 15:05:07 +0000 (16:05 +0100)]
Merge pull request #928 from davidcunado-arm/dc/update_userguide
Update AEM and Cortex Models versions
davidcunado-arm [Thu, 11 May 2017 15:04:52 +0000 (16:04 +0100)]
Merge pull request #927 from jeenu-arm/state-switch
Execution state switch
davidcunado-arm [Thu, 11 May 2017 09:20:31 +0000 (10:20 +0100)]
Merge pull request #932 from dp-arm/dp/spdx-rockchip
Use SPDX license identifiers for remaining files
dp-arm [Wed, 10 May 2017 14:16:15 +0000 (15:16 +0100)]
Use SPDX license identifiers for remaining files
Change-Id: I7f54f45db65f32481cc05e1bd2c9c683b756e19a
Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
davidcunado-arm [Wed, 10 May 2017 11:48:38 +0000 (12:48 +0100)]
Merge pull request #918 from rockchip-linux/rk3328
rockchip: rk3328: support rk3328
davidcunado-arm [Wed, 10 May 2017 11:11:22 +0000 (12:11 +0100)]
Merge pull request #931 from antonio-nino-diaz-arm/an/revert-rockchip
Revert "rockchip: Remove unused rockchip_pd_pwr_down_wfi function"
Antonio Nino Diaz [Wed, 10 May 2017 09:59:22 +0000 (10:59 +0100)]
Revert "rockchip: Remove unused rockchip_pd_pwr_down_wfi function"
This reverts commit
b6dcbf588af442fa87721dc707ff9e54d04ff504.
This function wasn't used when it was removed, but it is needed to
compile the new changes proposed for Rockchip platforms.
Change-Id: Ia5bfe1f8398e08431f96923e2f059a83e5cb78d4
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
tony.xie [Wed, 10 May 2017 02:23:05 +0000 (10:23 +0800)]
rockchip: rk3328: Add a missing paragraph for copyright notice.
Change-Id: I78c7e304d3070f66e2ca3bf838c76ee6a2ae3430
Signed-off-by: tony.xie <tony.xie@rock-chips.com>
Antonio Nino Diaz [Mon, 8 May 2017 15:43:53 +0000 (16:43 +0100)]
Minor fixes to the xlat tables lib v2
- Fix some comments.
- Remove duplicated definition.
- Make xlat_arch_get_max_supported_pa() private in aarch64.
Change-Id: I629237209cfb2ce7b0c4bd539d63dd81d45b2edd
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
davidcunado-arm [Mon, 8 May 2017 22:32:52 +0000 (23:32 +0100)]
Merge pull request #926 from EvanLloyd/win_make_4
Minor makefile fixes
davidcunado-arm [Mon, 8 May 2017 22:23:36 +0000 (23:23 +0100)]
Merge pull request #922 from davidcunado-arm/dc/smc_yielding_spds
Migrate secure payload dispatchers to new SMC terminology
David Cunado [Thu, 4 May 2017 10:35:56 +0000 (11:35 +0100)]
Update AEM and Cortex Models versions
AEMv8-A Model release v8.4 has been made available and Trusted Firmware
has been tested against these versions as part of its CI system. This
patch updates the user guide documentation to reflect the version of AEM
and Cortex Models that Trusted Firmware has been tested against.
Additionally, ARM FVPs FVP_Base_Cortex-A57x1-A53x1 and
FVP_Base_Cortex-A57x2-A53x4 are removed from the list of tested FVPs
as they are currently not being tested with the latest version of ARM
Trusted Firmware.
Also, documentation and links to Linaro pages have been updated to
reflect the changes in the ARM community document hosting.
Change-Id: Idae97303ce0929c82b137017de84ce94678f6f2b
Signed-off-by: David Cunado <david.cunado@arm.com>
davidcunado-arm [Fri, 5 May 2017 08:50:34 +0000 (09:50 +0100)]
Merge pull request #924 from antonio-nino-diaz-arm/an/fix-xn-bit
Fix execute-never permissions in xlat tables libs
David Cunado [Sun, 16 Apr 2017 16:15:08 +0000 (17:15 +0100)]
Migrate secure payload dispatchers to new SMC terminology
Since Issue B (November 2016) of the SMC Calling Convention document
standard SMC calls are renamed to yielding SMC calls to help avoid
confusion with the standard service SMC range, which remains unchanged.
http://infocenter.arm.com/help/topic/com.arm.doc.den0028b/ARM_DEN0028B_SMC_Calling_Convention.pd
A previous patch introduced a new define for yielding SMC call type.
This patch updates the secure payload dispatchers (except the TSPD) to
use this new define and also migrates the code to use the new
terminology.
Change-Id: I3d2437c04e3b21fdbd32019f55c066c87679a5bf
Signed-off-by: David Cunado <david.cunado@arm.com>
davidcunado-arm [Thu, 4 May 2017 15:35:19 +0000 (16:35 +0100)]
Merge pull request #925 from dp-arm/dp/spdx
Use SPDX license identifiers
Jeenu Viswambharan [Thu, 16 Feb 2017 14:55:15 +0000 (14:55 +0000)]
Introduce ARM SiP service to switch execution state
In AArch64, privileged exception levels control the execution state
(a.k.a. register width) of the immediate lower Exception Level; i.e.
whether the lower exception level executes in AArch64 or AArch32 state.
For an exception level to have its execution state changed at run time,
it must request the change by raising a synchronous exception to the
higher exception level.
This patch implements and adds such a provision to the ARM SiP service,
by which an immediate lower exception level can request to switch its
execution state. The execution state is switched if the request is:
- raised from non-secure world;
- raised on the primary CPU, before any secondaries are brought online
with CPU_ON PSCI call;
- raised from an exception level immediately below EL3: EL2, if
implemented; otherwise NS EL1.
If successful, the SMC doesn't return to the caller, but to the entry
point supplied with the call. Otherwise, the caller will observe the SMC
returning with STATE_SW_E_DENIED code. If ARM Trusted Firmware is built
for AArch32, the feature is not supported, and the call will always
fail.
For the ARM SiP service:
- Add SMC function IDs for both AArch32 and AArch64;
- Increment the SiP service minor version to 2;
- Adjust the number of supported SiP service calls.
Add documentation for ARM SiP service.
Fixes ARM-software/tf-issues#436
Change-Id: I4347f2d6232e69fbfbe333b340fcd0caed0a4cea
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
dp-arm [Wed, 3 May 2017 08:38:09 +0000 (09:38 +0100)]
Use SPDX license identifiers
To make software license auditing simpler, use SPDX[0] license
identifiers instead of duplicating the license text in every file.
NOTE: Files that have been imported by FreeBSD have not been modified.
[0]: https://spdx.org/
Change-Id: I80a00e1f641b8cc075ca5a95b10607ed9ed8761a
Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
Evan Lloyd [Tue, 11 Apr 2017 15:52:00 +0000 (16:52 +0100)]
Build: Correct Unix specific echo commands
Some recent changes have added direct use of the echo command without
parameters. This fails on a Windows shell, because echo without
parameters reports the mode ("ECHO is on").
This is corrected using the ECHO_BLANK_LINE macro already provided
for that purpose.
Change-Id: I5fd7192861b4496f6f46b4f096e80a752cd135d6
Signed-off-by: Evan Lloyd <evan.lloyd@arm.com>
Evan Lloyd [Fri, 7 Apr 2017 15:58:57 +0000 (16:58 +0100)]
Build: Fix parallel build
2 problems were found, but are in one change to avoid submitting a patch
that might fail to build. The problems were:
1. The macro MAKE_PREREQ_DIR has a minor bug, in that it is capable of
generating recursive dependencies.
2. The inclusion of BUILD_DIR in TEMP_OBJ_DIRS left no explicit
dependency, BUILD_DIR might not exist when subdirectories are
created by a thread on another CPU.
This fix corrects these with the following changes:
1. MAKE_PREREQ_DIR does nothing for a direct self dependency.
2. BUILD_DIR is built using MAKE_PREREQ_DIR.
3. BUILD_DIR is an explicit prerequisite of all OBJ_DIRS.
Change-Id: I938cddea4a006df225c02a47b9cf759212f27fb7
Signed-off-by: Evan Lloyd <evan.lloyd@arm.com>
davidcunado-arm [Tue, 2 May 2017 15:32:20 +0000 (16:32 +0100)]
Merge pull request #919 from davidcunado-arm/dc/smc_yielding_generic
Update terminology: standard SMC to yielding SMC
Jeenu Viswambharan [Tue, 21 Feb 2017 14:40:44 +0000 (14:40 +0000)]
Add macro to check whether the CPU implements an EL
Replace all instances of checks with the new macro.
Change-Id: I0eec39b9376475a1a9707a3115de9d36f88f8a2a
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
Antonio Nino Diaz [Thu, 27 Apr 2017 12:30:22 +0000 (13:30 +0100)]
Fix execute-never permissions in xlat tables libs
Translation regimes that only support one virtual address space (such as
the ones for EL2 and EL3) can flag memory regions as execute-never by
setting to 1 the XN bit in the Upper Attributes field in the translation
tables descriptors. Translation regimes that support two different
virtual address spaces (such as the one shared by EL1 and EL0) use bits
PXN and UXN instead.
The Trusted Firmware runs at EL3 and EL1, it has to handle translation
tables of both translation regimes, but the previous code handled both
regimes the same way, as if both had only 1 VA range.
When trying to set a descriptor as execute-never it would set the XN
bit correctly in EL3, but it would set the XN bit in EL1 as well. XN is
at the same bit position as UXN, which means that EL0 was being
prevented from executing code at this region, not EL1 as the code
intended. Therefore, the PXN bit was unset to 0 all the time. The result
is that, in AArch64 mode, read-only data sections of BL2 weren't
protected from being executed.
This patch adds support of translation regimes with two virtual address
spaces to both versions of the translation tables library, fixing the
execute-never permissions for translation tables in EL1.
The library currently does not support initializing translation tables
for EL0 software, therefore it does not set/unset the UXN bit. If EL1
software needs to initialize translation tables for EL0 software, it
should use a different library instead.
Change-Id: If27588f9820ff42988851d90dc92801c8ecbe0c9
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
davidcunado-arm [Tue, 2 May 2017 14:32:23 +0000 (15:32 +0100)]
Merge pull request #923 from nmenon/fix_xlat_1
xlat lib: Don't set mmap_attr_t enum to be -1
Nishanth Menon [Mon, 1 May 2017 17:26:34 +0000 (12:26 -0500)]
xlat lib: Don't set mmap_attr_t enum to be -1
-1 is not a defined mmap_attr_t type. Instead of using invalid enum
types, we can either choose to define a INVALID type OR handle the
condition specifically.
Since the usage of mmap_region_attr is limited, it is easier to just
handle the error condition specifically and return 0 or -1 depending
on success or fail.
Fixes: ARM-Software/tf-issues#473
Fixes: 28fa2e9ee8f4 ("xlat lib: Use mmap_attr_t type consistently")
Signed-off-by: Nishanth Menon <nm@ti.com>
davidcunado-arm [Tue, 2 May 2017 10:13:20 +0000 (11:13 +0100)]
Merge pull request #896 from sbranden/tf_issue_461
Move defines in utils.h to utils_def.h to fix shared header compile i…
davidcunado-arm [Tue, 2 May 2017 09:37:30 +0000 (10:37 +0100)]
Merge pull request #913 from vwadekar/tegra-fixes-from-downstream
Tegra fixes from downstream
Varun Wadekar [Tue, 18 Apr 2017 18:22:01 +0000 (11:22 -0700)]
Tegra210: implement 'get_target_pwr_state' handler
This patch implements the handler to calculate the cluster and
system power states for the Tegra210 SoC. The power states
returned by this handler are used by the PSCI library to decide
cache maintenance operations - cluster v cpu.
Change-Id: I93e4139d4cd8a086b51f328e9a76e91428ebcdab
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Varun Wadekar [Wed, 25 Jan 2017 21:35:27 +0000 (13:35 -0800)]
Tegra: fix the NS DRAM address calculation logic
This patch fixes the logic used to calculate the end of NS memory
aperture. The functions allows zero sized NS apertures as that is
a valid requirement for some use cases. e.g. VPR resize.
Change-Id: Ie966e0ea2f9c6888d21c38e734003704094b3720
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Varun Wadekar [Wed, 21 Dec 2016 22:50:18 +0000 (14:50 -0800)]
Tegra: memctrl_v2: zero out NS Video memory carveout region
The video memory carveout has to be re-sized depending on the Video
content. This requires the NS world to send us new base/size values.
Before setting up the new region, we must zero out the previous memory
region, so that the video frames are not leaked to the outside world.
This patch adds the logic to zero out the previous memory carveout
region.
Change-Id: I471167ef7747154440df5c1a5e015fbeb69d9043
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Varun Wadekar [Fri, 7 Apr 2017 00:33:31 +0000 (17:33 -0700)]
Tegra186: calculate proper power state for cluster/system power down
Earlier, we were setting "System Suspend" as the power state for all system
states. This caused incorrect system state during a cluster power down.
This patch fixes this anomaly and sets the correct power state during a
cluster/system power down.
Change-Id: Ibd002930e0ae103e381e0a19670c3c4d057e7cb7
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Steven Kao [Fri, 23 Dec 2016 08:17:18 +0000 (16:17 +0800)]
Tegra186: mce: max retries for ARI requests
This patch adds max retries for all ARI requests and asserts
if the ARI request is still busy.
Change-Id: I454ad9b557bb59e513e4c0c6f071275c87d0e07a
Signed-off-by: Steven Kao <skao@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Steven Kao [Fri, 23 Dec 2016 08:05:13 +0000 (16:05 +0800)]
Tegra: memmap Tegra micro-seconds timer controller
This patch adds the Tegra micro-seconds controller to the
memory map. This allows us to use the delay_timer functionality.
Change-Id: Ia8b148a871949bfede539974cacbe0e93ec7e77c
Signed-off-by: Steven Kao <skao@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Steven Kao [Fri, 21 Oct 2016 06:16:59 +0000 (14:16 +0800)]
Tegra: early init the delay timer
This patch moves the platform delay timer init to early BL31
platform setup, so that platforms can use the udelay/mdelay
routines in the early init code.
Change-Id: I6fe20b76176ea22589539c180c5b6f9d09eda8de
Signed-off-by: Steven Kao <skao@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Scott Branden [Sat, 29 Apr 2017 15:36:12 +0000 (08:36 -0700)]
Merge branch 'integration' into tf_issue_461
Scott Branden [Mon, 10 Apr 2017 18:45:52 +0000 (11:45 -0700)]
Move defines in utils.h to utils_def.h to fix shared header compile issues
utils.h is included in various header files for the defines in it.
Some of the other header files only contain defines. This allows the
header files to be shared between host and target builds for shared defines.
Recently types.h has been included in utils.h as well as some function
prototypes.
Because of the inclusion of types.h conflicts exist building host tools
abd these header files now. To solve this problem,
move the defines to utils_def.h and have this included by utils.h and
change header files to only include utils_def.h and not pick up the new
types.h being introduced.
Fixes ARM-software/tf-issues#461
Signed-off-by: Scott Branden <scott.branden@broadcom.com>
Remove utils_def.h from utils.h
This patch removes utils_def.h from utils.h as it is not required.
And also makes a minor change to ensure Juno platform compiles.
Change-Id: I10cf1fb51e44a8fa6dcec02980354eb9ecc9fa29
davidcunado-arm [Thu, 27 Apr 2017 14:29:28 +0000 (15:29 +0100)]
Merge pull request #920 from vwadekar/asserts-release-nvidia
Asserts release nvidia
Antonio Nino Diaz [Tue, 28 Mar 2017 12:56:21 +0000 (13:56 +0100)]
Tegra: Control inclusion of helper code used for asserts
One assert depends on code that is conditionally compiled based on the
DEBUG define. This patch modifies the conditional inclusion of such code
so that it is based on the ENABLE_ASSERTIONS build option.
Change-Id: Ic5659a3db8632593b9d2e83dac6d30afd87c131d
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Varun Wadekar [Wed, 26 Apr 2017 20:49:52 +0000 (13:49 -0700)]
Tegra: smmu: enable asserts by default
This patch enables the assert in the context save routine
by default, for all flavours of the build.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Varun Wadekar [Wed, 26 Apr 2017 20:48:19 +0000 (13:48 -0700)]
Tegra: enable 'ENABLE_ASSERTIONS' for all builds
This patch changes the platform Makefile to set `ENABLE_ASSERTIONS` to
1 instead of the deprecated option `ASM_ASSERTION`. This also pulls in
C assertions in release mode.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Varun Wadekar [Wed, 26 Apr 2017 20:46:11 +0000 (13:46 -0700)]
Tegra: group platform settings together
This patch groups all the platform configuration macros into
the common platform.mk makefile.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
davidcunado-arm [Wed, 26 Apr 2017 12:48:29 +0000 (13:48 +0100)]
Merge pull request #917 from soby-mathew/sm/sys_susp_css
CSS: Allow system suspend only via PSCI SYSTEM_SUSPEND API
David Cunado [Wed, 5 Apr 2017 10:34:03 +0000 (11:34 +0100)]
Update terminology: standard SMC to yielding SMC
Since Issue B (November 2016) of the SMC Calling Convention document
standard SMC calls are renamed to yielding SMC calls to help avoid
confusion with the standard service SMC range, which remains unchanged.
http://infocenter.arm.com/help/topic/com.arm.doc.den0028b/ARM_DEN0028B_SMC_Calling_Convention.pdf
This patch adds a new define for yielding SMC call type and deprecates
the current standard SMC call type. The tsp is migrated to use this new
terminology and, additionally, the documentation and code comments are
updated to use this new terminology.
Change-Id: I0d7cc0224667ee6c050af976745f18c55906a793
Signed-off-by: David Cunado <david.cunado@arm.com>