From: Daniel Golle Date: Sat, 27 Apr 2024 12:05:30 +0000 (+0100) Subject: generic: v6.1, v6.6: add patch to fix PHY-muxing on MT7530 X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=fe9d2ccbc3d9dc0852df474f0e3cc07f93beae8b;p=openwrt%2Fopenwrt.git generic: v6.1, v6.6: add patch to fix PHY-muxing on MT7530 Move accepted patches to backport folder, re-add previously removed patch which caused havoc on MT7621 and add the (still pending) fix. Fixes: d40691a5fb ("generic: 6.1, 6.6: mt7530: import pending patches") Signed-off-by: Daniel Golle --- diff --git a/target/linux/generic/backport-6.1/790-54-v6.10-net-dsa-mt7530-disable-EEE-abilities-on-failure-on-M.patch b/target/linux/generic/backport-6.1/790-54-v6.10-net-dsa-mt7530-disable-EEE-abilities-on-failure-on-M.patch new file mode 100644 index 0000000000..44cf60cf14 --- /dev/null +++ b/target/linux/generic/backport-6.1/790-54-v6.10-net-dsa-mt7530-disable-EEE-abilities-on-failure-on-M.patch @@ -0,0 +1,88 @@ +From 856e8954a0a88d1a4d2b43e9002b9249131a156f Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= +Date: Mon, 22 Apr 2024 10:15:08 +0300 +Subject: [PATCH 01/15] net: dsa: mt7530: disable EEE abilities on failure on + MT7531 and MT7988 +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +The MT7531_FORCE_EEE1G and MT7531_FORCE_EEE100 bits let the +PMCR_FORCE_EEE1G and PMCR_FORCE_EEE100 bits determine the 1G/100 EEE +abilities of the MAC. If MT7531_FORCE_EEE1G and MT7531_FORCE_EEE100 are +unset, the abilities are left to be determined by PHY auto polling. + +The commit 40b5d2f15c09 ("net: dsa: mt7530: Add support for EEE features") +made it so that the PMCR_FORCE_EEE1G and PMCR_FORCE_EEE100 bits are set on +mt753x_phylink_mac_link_up(). But it did not set the MT7531_FORCE_EEE1G and +MT7531_FORCE_EEE100 bits. Because of this, the EEE abilities will be +determined by PHY auto polling, regardless of the result of phy_init_eee(). + +Define these bits and add them to the MT7531_FORCE_MODE mask which is set +in mt7531_setup_common(). With this, there won't be any EEE abilities set +when phy_init_eee() returns a negative value. + +Thanks to Russell for explaining when phy_init_eee() could return a +negative value below. + +Looking at phy_init_eee(), it could return a negative value when: + +1. phydev->drv is NULL +2. if genphy_c45_eee_is_active() returns negative +3. if genphy_c45_eee_is_active() returns zero, it returns -EPROTONOSUPPORT +4. if phy_set_bits_mmd() fails (e.g. communication error with the PHY) + +If we then look at genphy_c45_eee_is_active(), then: + +genphy_c45_read_eee_adv() and genphy_c45_read_eee_lpa() propagate their +non-zero return values, otherwise this function returns zero or positive +integer. + +If we then look at genphy_c45_read_eee_adv(), then a failure of +phy_read_mmd() would cause a negative value to be returned. + +Looking at genphy_c45_read_eee_lpa(), the same is true. + +So, it can be summarised as: + +- phydev->drv is NULL +- there is a communication error accessing the PHY +- EEE is not active + +otherwise, it returns zero on success. + +If one wishes to determine whether an error occurred vs EEE not being +supported through negotiation for the negotiated speed, if it returns +-EPROTONOSUPPORT in the latter case. Other error codes mean either the +driver has been unloaded or communication error. + +In conclusion, determining the EEE abilities by PHY auto polling shouldn't +result in having any EEE abilities enabled, when one of the last two +situations in the summary happens. And it seems that if phydev->drv is +NULL, there would be bigger problems with the device than a broken link. So +this is not a bugfix. + +Signed-off-by: Arınç ÜNAL +--- + drivers/net/dsa/mt7530.h | 6 +++++- + 1 file changed, 5 insertions(+), 1 deletion(-) + +--- a/drivers/net/dsa/mt7530.h ++++ b/drivers/net/dsa/mt7530.h +@@ -328,11 +328,15 @@ enum mt7530_vlan_port_acc_frm { + #define MT7531_FORCE_DPX BIT(29) + #define MT7531_FORCE_RX_FC BIT(28) + #define MT7531_FORCE_TX_FC BIT(27) ++#define MT7531_FORCE_EEE100 BIT(26) ++#define MT7531_FORCE_EEE1G BIT(25) + #define MT7531_FORCE_MODE (MT7531_FORCE_LNK | \ + MT7531_FORCE_SPD | \ + MT7531_FORCE_DPX | \ + MT7531_FORCE_RX_FC | \ +- MT7531_FORCE_TX_FC) ++ MT7531_FORCE_TX_FC | \ ++ MT7531_FORCE_EEE100 | \ ++ MT7531_FORCE_EEE1G) + #define PMCR_LINK_SETTINGS_MASK (PMCR_TX_EN | PMCR_FORCE_SPEED_1000 | \ + PMCR_RX_EN | PMCR_FORCE_SPEED_100 | \ + PMCR_TX_FC_EN | PMCR_RX_FC_EN | \ diff --git a/target/linux/generic/backport-6.1/790-55-v6.10-net-dsa-mt7530-refactor-MT7530_PMCR_P.patch b/target/linux/generic/backport-6.1/790-55-v6.10-net-dsa-mt7530-refactor-MT7530_PMCR_P.patch new file mode 100644 index 0000000000..3cbd62e929 --- /dev/null +++ b/target/linux/generic/backport-6.1/790-55-v6.10-net-dsa-mt7530-refactor-MT7530_PMCR_P.patch @@ -0,0 +1,200 @@ +From 712ad00d2f43814c81a7abfcbc339690a05fb6a0 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= +Date: Mon, 22 Apr 2024 10:15:09 +0300 +Subject: [PATCH 02/15] net: dsa: mt7530: refactor MT7530_PMCR_P() +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +The MT7530_PMCR_P() registers are on MT7530, MT7531, and the switch on the +MT7988 SoC. Rename the definition for them to MT753X_PMCR_P(). Bit 15 is +for MT7530 only. Add MT7530 prefix to the definition for bit 15. + +Use GENMASK and FIELD_PREP for PMCR_IFG_XMIT(). + +Rename PMCR_TX_EN and PMCR_RX_EN to PMCR_MAC_TX_EN and PMCR_MAC_TX_EN to +follow the naming on the "MT7621 Giga Switch Programming Guide v0.3", +"MT7531 Reference Manual for Development Board v1.0", and "MT7988A Wi-Fi 7 +Generation Router Platform: Datasheet (Open Version) v0.1" documents. + +These documents show that PMCR_RX_FC_EN is at bit 5. Correct this along +with renaming it to PMCR_FORCE_RX_FC_EN, and the same for PMCR_TX_FC_EN. + +Remove PMCR_SPEED_MASK which doesn't have a use. + +Rename the force mode definitions for MT7531 to FORCE_MODE. Add MASK at the +end for the mask that includes all force mode definitions. + +Signed-off-by: Arınç ÜNAL +--- + drivers/net/dsa/mt7530.c | 24 ++++++++--------- + drivers/net/dsa/mt7530.h | 58 +++++++++++++++++++++------------------- + 2 files changed, 42 insertions(+), 40 deletions(-) + +--- a/drivers/net/dsa/mt7530.c ++++ b/drivers/net/dsa/mt7530.c +@@ -889,7 +889,7 @@ static void mt7530_setup_port5(struct ds + val &= ~MHWTRAP_P5_MAC_SEL & ~MHWTRAP_P5_DIS; + + /* Setup the MAC by default for the cpu port */ +- mt7530_write(priv, MT7530_PMCR_P(5), 0x56300); ++ mt7530_write(priv, MT753X_PMCR_P(5), 0x56300); + break; + case P5_INTF_SEL_GMAC5: + /* MT7530_P5_MODE_GMAC: P5 -> External phy or 2nd GMAC */ +@@ -2435,8 +2435,8 @@ mt7530_setup(struct dsa_switch *ds) + /* Clear link settings and enable force mode to force link down + * on all ports until they're enabled later. + */ +- mt7530_rmw(priv, MT7530_PMCR_P(i), PMCR_LINK_SETTINGS_MASK | +- PMCR_FORCE_MODE, PMCR_FORCE_MODE); ++ mt7530_rmw(priv, MT753X_PMCR_P(i), PMCR_LINK_SETTINGS_MASK | ++ MT7530_FORCE_MODE, MT7530_FORCE_MODE); + + /* Disable forwarding by default on all ports */ + mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK, +@@ -2546,8 +2546,8 @@ mt7531_setup_common(struct dsa_switch *d + /* Clear link settings and enable force mode to force link down + * on all ports until they're enabled later. + */ +- mt7530_rmw(priv, MT7530_PMCR_P(i), PMCR_LINK_SETTINGS_MASK | +- MT7531_FORCE_MODE, MT7531_FORCE_MODE); ++ mt7530_rmw(priv, MT753X_PMCR_P(i), PMCR_LINK_SETTINGS_MASK | ++ MT7531_FORCE_MODE_MASK, MT7531_FORCE_MODE_MASK); + + /* Disable forwarding by default on all ports */ + mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK, +@@ -2630,7 +2630,7 @@ mt7531_setup(struct dsa_switch *ds) + + /* Force link down on all ports before internal reset */ + for (i = 0; i < MT7530_NUM_PORTS; i++) +- mt7530_write(priv, MT7530_PMCR_P(i), MT7531_FORCE_LNK); ++ mt7530_write(priv, MT753X_PMCR_P(i), MT7531_FORCE_MODE_LNK); + + /* Reset the switch through internal reset */ + mt7530_write(priv, MT7530_SYS_CTRL, SYS_CTRL_SW_RST | SYS_CTRL_REG_RST); +@@ -2872,7 +2872,7 @@ mt753x_phylink_mac_config(struct phylink + + /* Are we connected to external phy */ + if (port == 5 && dsa_is_user_port(ds, 5)) +- mt7530_set(priv, MT7530_PMCR_P(port), PMCR_EXT_PHY); ++ mt7530_set(priv, MT753X_PMCR_P(port), PMCR_EXT_PHY); + } + + static void mt753x_phylink_mac_link_down(struct phylink_config *config, +@@ -2882,7 +2882,7 @@ static void mt753x_phylink_mac_link_down + struct dsa_port *dp = dsa_phylink_to_port(config); + struct mt7530_priv *priv = dp->ds->priv; + +- mt7530_clear(priv, MT7530_PMCR_P(dp->index), PMCR_LINK_SETTINGS_MASK); ++ mt7530_clear(priv, MT753X_PMCR_P(dp->index), PMCR_LINK_SETTINGS_MASK); + } + + static void mt753x_phylink_mac_link_up(struct phylink_config *config, +@@ -2896,7 +2896,7 @@ static void mt753x_phylink_mac_link_up(s + struct mt7530_priv *priv = dp->ds->priv; + u32 mcr; + +- mcr = PMCR_RX_EN | PMCR_TX_EN | PMCR_FORCE_LNK; ++ mcr = PMCR_MAC_RX_EN | PMCR_MAC_TX_EN | PMCR_FORCE_LNK; + + switch (speed) { + case SPEED_1000: +@@ -2911,9 +2911,9 @@ static void mt753x_phylink_mac_link_up(s + if (duplex == DUPLEX_FULL) { + mcr |= PMCR_FORCE_FDX; + if (tx_pause) +- mcr |= PMCR_TX_FC_EN; ++ mcr |= PMCR_FORCE_TX_FC_EN; + if (rx_pause) +- mcr |= PMCR_RX_FC_EN; ++ mcr |= PMCR_FORCE_RX_FC_EN; + } + + if (mode == MLO_AN_PHY && phydev && phy_init_eee(phydev, false) >= 0) { +@@ -2928,7 +2928,7 @@ static void mt753x_phylink_mac_link_up(s + } + } + +- mt7530_set(priv, MT7530_PMCR_P(dp->index), mcr); ++ mt7530_set(priv, MT753X_PMCR_P(dp->index), mcr); + } + + static void mt753x_phylink_get_caps(struct dsa_switch *ds, int port, +--- a/drivers/net/dsa/mt7530.h ++++ b/drivers/net/dsa/mt7530.h +@@ -304,44 +304,46 @@ enum mt7530_vlan_port_acc_frm { + #define G0_PORT_VID_DEF G0_PORT_VID(0) + + /* Register for port MAC control register */ +-#define MT7530_PMCR_P(x) (0x3000 + ((x) * 0x100)) +-#define PMCR_IFG_XMIT(x) (((x) & 0x3) << 18) ++#define MT753X_PMCR_P(x) (0x3000 + ((x) * 0x100)) ++#define PMCR_IFG_XMIT_MASK GENMASK(19, 18) ++#define PMCR_IFG_XMIT(x) FIELD_PREP(PMCR_IFG_XMIT_MASK, x) + #define PMCR_EXT_PHY BIT(17) + #define PMCR_MAC_MODE BIT(16) +-#define PMCR_FORCE_MODE BIT(15) +-#define PMCR_TX_EN BIT(14) +-#define PMCR_RX_EN BIT(13) ++#define MT7530_FORCE_MODE BIT(15) ++#define PMCR_MAC_TX_EN BIT(14) ++#define PMCR_MAC_RX_EN BIT(13) + #define PMCR_BACKOFF_EN BIT(9) + #define PMCR_BACKPR_EN BIT(8) + #define PMCR_FORCE_EEE1G BIT(7) + #define PMCR_FORCE_EEE100 BIT(6) +-#define PMCR_TX_FC_EN BIT(5) +-#define PMCR_RX_FC_EN BIT(4) ++#define PMCR_FORCE_RX_FC_EN BIT(5) ++#define PMCR_FORCE_TX_FC_EN BIT(4) + #define PMCR_FORCE_SPEED_1000 BIT(3) + #define PMCR_FORCE_SPEED_100 BIT(2) + #define PMCR_FORCE_FDX BIT(1) + #define PMCR_FORCE_LNK BIT(0) +-#define PMCR_SPEED_MASK (PMCR_FORCE_SPEED_100 | \ +- PMCR_FORCE_SPEED_1000) +-#define MT7531_FORCE_LNK BIT(31) +-#define MT7531_FORCE_SPD BIT(30) +-#define MT7531_FORCE_DPX BIT(29) +-#define MT7531_FORCE_RX_FC BIT(28) +-#define MT7531_FORCE_TX_FC BIT(27) +-#define MT7531_FORCE_EEE100 BIT(26) +-#define MT7531_FORCE_EEE1G BIT(25) +-#define MT7531_FORCE_MODE (MT7531_FORCE_LNK | \ +- MT7531_FORCE_SPD | \ +- MT7531_FORCE_DPX | \ +- MT7531_FORCE_RX_FC | \ +- MT7531_FORCE_TX_FC | \ +- MT7531_FORCE_EEE100 | \ +- MT7531_FORCE_EEE1G) +-#define PMCR_LINK_SETTINGS_MASK (PMCR_TX_EN | PMCR_FORCE_SPEED_1000 | \ +- PMCR_RX_EN | PMCR_FORCE_SPEED_100 | \ +- PMCR_TX_FC_EN | PMCR_RX_FC_EN | \ +- PMCR_FORCE_FDX | PMCR_FORCE_LNK | \ +- PMCR_FORCE_EEE1G | PMCR_FORCE_EEE100) ++#define MT7531_FORCE_MODE_LNK BIT(31) ++#define MT7531_FORCE_MODE_SPD BIT(30) ++#define MT7531_FORCE_MODE_DPX BIT(29) ++#define MT7531_FORCE_MODE_RX_FC BIT(28) ++#define MT7531_FORCE_MODE_TX_FC BIT(27) ++#define MT7531_FORCE_MODE_EEE100 BIT(26) ++#define MT7531_FORCE_MODE_EEE1G BIT(25) ++#define MT7531_FORCE_MODE_MASK (MT7531_FORCE_MODE_LNK | \ ++ MT7531_FORCE_MODE_SPD | \ ++ MT7531_FORCE_MODE_DPX | \ ++ MT7531_FORCE_MODE_RX_FC | \ ++ MT7531_FORCE_MODE_TX_FC | \ ++ MT7531_FORCE_MODE_EEE100 | \ ++ MT7531_FORCE_MODE_EEE1G) ++#define PMCR_LINK_SETTINGS_MASK (PMCR_MAC_TX_EN | PMCR_MAC_RX_EN | \ ++ PMCR_FORCE_EEE1G | \ ++ PMCR_FORCE_EEE100 | \ ++ PMCR_FORCE_RX_FC_EN | \ ++ PMCR_FORCE_TX_FC_EN | \ ++ PMCR_FORCE_SPEED_1000 | \ ++ PMCR_FORCE_SPEED_100 | \ ++ PMCR_FORCE_FDX | PMCR_FORCE_LNK) + + #define MT7530_PMEEECR_P(x) (0x3004 + (x) * 0x100) + #define WAKEUP_TIME_1000(x) (((x) & 0xFF) << 24) diff --git a/target/linux/generic/backport-6.1/790-56-v6.10-net-dsa-mt7530-rename-p5_intf_sel-and-use-only-for-M.patch b/target/linux/generic/backport-6.1/790-56-v6.10-net-dsa-mt7530-rename-p5_intf_sel-and-use-only-for-M.patch new file mode 100644 index 0000000000..9697e7eb4f --- /dev/null +++ b/target/linux/generic/backport-6.1/790-56-v6.10-net-dsa-mt7530-rename-p5_intf_sel-and-use-only-for-M.patch @@ -0,0 +1,185 @@ +From 875ec5b67ab88e969b171e6e9ea803e3ed759614 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= +Date: Mon, 22 Apr 2024 10:15:10 +0300 +Subject: [PATCH 03/15] net: dsa: mt7530: rename p5_intf_sel and use only for + MT7530 switch +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +The p5_intf_sel pointer is used to store the information of whether PHY +muxing is used or not. PHY muxing is a feature specific to port 5 of the +MT7530 switch. Do not use it for other switch models. + +Rename the pointer to p5_mode to store the mode the port is being used in. +Rename the p5_interface_select enum to mt7530_p5_mode, the string +representation to mt7530_p5_mode_str, and the enum elements. + +If PHY muxing is not detected, the default mode, GMAC5, will be used. + +Signed-off-by: Arınç ÜNAL +--- + drivers/net/dsa/mt7530.c | 62 +++++++++++++++++----------------------- + drivers/net/dsa/mt7530.h | 15 +++++----- + 2 files changed, 33 insertions(+), 44 deletions(-) + +--- a/drivers/net/dsa/mt7530.c ++++ b/drivers/net/dsa/mt7530.c +@@ -850,19 +850,15 @@ mt7530_set_ageing_time(struct dsa_switch + return 0; + } + +-static const char *p5_intf_modes(unsigned int p5_interface) ++static const char *mt7530_p5_mode_str(unsigned int mode) + { +- switch (p5_interface) { +- case P5_DISABLED: +- return "DISABLED"; +- case P5_INTF_SEL_PHY_P0: +- return "PHY P0"; +- case P5_INTF_SEL_PHY_P4: +- return "PHY P4"; +- case P5_INTF_SEL_GMAC5: +- return "GMAC5"; ++ switch (mode) { ++ case MUX_PHY_P0: ++ return "MUX PHY P0"; ++ case MUX_PHY_P4: ++ return "MUX PHY P4"; + default: +- return "unknown"; ++ return "GMAC5"; + } + } + +@@ -879,23 +875,23 @@ static void mt7530_setup_port5(struct ds + val |= MHWTRAP_MANUAL | MHWTRAP_P5_MAC_SEL | MHWTRAP_P5_DIS; + val &= ~MHWTRAP_P5_RGMII_MODE & ~MHWTRAP_PHY0_SEL; + +- switch (priv->p5_intf_sel) { +- case P5_INTF_SEL_PHY_P0: +- /* MT7530_P5_MODE_GPHY_P0: 2nd GMAC -> P5 -> P0 */ ++ switch (priv->p5_mode) { ++ /* MUX_PHY_P0: P0 -> P5 -> SoC MAC */ ++ case MUX_PHY_P0: + val |= MHWTRAP_PHY0_SEL; + fallthrough; +- case P5_INTF_SEL_PHY_P4: +- /* MT7530_P5_MODE_GPHY_P4: 2nd GMAC -> P5 -> P4 */ ++ ++ /* MUX_PHY_P4: P4 -> P5 -> SoC MAC */ ++ case MUX_PHY_P4: + val &= ~MHWTRAP_P5_MAC_SEL & ~MHWTRAP_P5_DIS; + + /* Setup the MAC by default for the cpu port */ + mt7530_write(priv, MT753X_PMCR_P(5), 0x56300); + break; +- case P5_INTF_SEL_GMAC5: +- /* MT7530_P5_MODE_GMAC: P5 -> External phy or 2nd GMAC */ +- val &= ~MHWTRAP_P5_DIS; +- break; ++ ++ /* GMAC5: P5 -> SoC MAC or external PHY */ + default: ++ val &= ~MHWTRAP_P5_DIS; + break; + } + +@@ -923,8 +919,8 @@ static void mt7530_setup_port5(struct ds + + mt7530_write(priv, MT7530_MHWTRAP, val); + +- dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, intf_sel=%s, phy-mode=%s\n", +- val, p5_intf_modes(priv->p5_intf_sel), phy_modes(interface)); ++ dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, mode=%s, phy-mode=%s\n", val, ++ mt7530_p5_mode_str(priv->p5_mode), phy_modes(interface)); + + mutex_unlock(&priv->reg_mutex); + } +@@ -2467,13 +2463,11 @@ mt7530_setup(struct dsa_switch *ds) + if (ret) + return ret; + +- /* Setup port 5 */ +- if (!dsa_is_unused_port(ds, 5)) { +- priv->p5_intf_sel = P5_INTF_SEL_GMAC5; +- } else { ++ /* Check for PHY muxing on port 5 */ ++ if (dsa_is_unused_port(ds, 5)) { + /* Scan the ethernet nodes. Look for GMAC1, lookup the used PHY. +- * Set priv->p5_intf_sel to the appropriate value if PHY muxing +- * is detected. ++ * Set priv->p5_mode to the appropriate value if PHY muxing is ++ * detected. + */ + for_each_child_of_node(dn, mac_np) { + if (!of_device_is_compatible(mac_np, +@@ -2497,17 +2491,16 @@ mt7530_setup(struct dsa_switch *ds) + } + id = of_mdio_parse_addr(ds->dev, phy_node); + if (id == 0) +- priv->p5_intf_sel = P5_INTF_SEL_PHY_P0; ++ priv->p5_mode = MUX_PHY_P0; + if (id == 4) +- priv->p5_intf_sel = P5_INTF_SEL_PHY_P4; ++ priv->p5_mode = MUX_PHY_P4; + } + of_node_put(mac_np); + of_node_put(phy_node); + break; + } + +- if (priv->p5_intf_sel == P5_INTF_SEL_PHY_P0 || +- priv->p5_intf_sel == P5_INTF_SEL_PHY_P4) ++ if (priv->p5_mode == MUX_PHY_P0 || priv->p5_mode == MUX_PHY_P4) + mt7530_setup_port5(ds, interface); + } + +@@ -2645,9 +2638,6 @@ mt7531_setup(struct dsa_switch *ds) + MT7531_EXT_P_MDIO_12); + } + +- if (!dsa_is_unused_port(ds, 5)) +- priv->p5_intf_sel = P5_INTF_SEL_GMAC5; +- + mt7530_rmw(priv, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK, + MT7531_GPIO0_INTERRUPT); + +--- a/drivers/net/dsa/mt7530.h ++++ b/drivers/net/dsa/mt7530.h +@@ -708,12 +708,11 @@ struct mt7530_port { + struct phylink_pcs *sgmii_pcs; + }; + +-/* Port 5 interface select definitions */ +-enum p5_interface_select { +- P5_DISABLED, +- P5_INTF_SEL_PHY_P0, +- P5_INTF_SEL_PHY_P4, +- P5_INTF_SEL_GMAC5, ++/* Port 5 mode definitions of the MT7530 switch */ ++enum mt7530_p5_mode { ++ GMAC5, ++ MUX_PHY_P0, ++ MUX_PHY_P4, + }; + + struct mt7530_priv; +@@ -769,7 +768,7 @@ struct mt753x_info { + * @ports: Holding the state among ports + * @reg_mutex: The lock for protecting among process accessing + * registers +- * @p5_intf_sel: Holding the current port 5 interface select ++ * @p5_mode: Holding the current mode of port 5 of the MT7530 switch + * @p5_sgmii: Flag for distinguishing if port 5 of the MT7531 switch + * has got SGMII + * @irq: IRQ number of the switch +@@ -791,7 +790,7 @@ struct mt7530_priv { + const struct mt753x_info *info; + unsigned int id; + bool mcm; +- enum p5_interface_select p5_intf_sel; ++ enum mt7530_p5_mode p5_mode; + bool p5_sgmii; + u8 mirror_rx; + u8 mirror_tx; diff --git a/target/linux/generic/backport-6.1/790-57-v6.10-net-dsa-mt7530-rename-mt753x_bpdu_port_fw-enum-to-mt.patch b/target/linux/generic/backport-6.1/790-57-v6.10-net-dsa-mt7530-rename-mt753x_bpdu_port_fw-enum-to-mt.patch new file mode 100644 index 0000000000..77a2df8586 --- /dev/null +++ b/target/linux/generic/backport-6.1/790-57-v6.10-net-dsa-mt7530-rename-mt753x_bpdu_port_fw-enum-to-mt.patch @@ -0,0 +1,169 @@ +From 83fe3df057e641cd0e88425e579d7a5a370ca430 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= +Date: Mon, 22 Apr 2024 10:15:11 +0300 +Subject: [PATCH 04/15] net: dsa: mt7530: rename mt753x_bpdu_port_fw enum to + mt753x_to_cpu_fw +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +The mt753x_bpdu_port_fw enum is globally used for manipulating the process +of deciding the forwardable ports, specifically concerning the CPU port(s). +Therefore, rename it and the values in it to mt753x_to_cpu_fw. + +Change FOLLOW_MFC to SYSTEM_DEFAULT to be on par with the switch documents. + +Signed-off-by: Arınç ÜNAL +--- + drivers/net/dsa/mt7530.c | 44 ++++++++++------------- + drivers/net/dsa/mt7530.h | 76 ++++++++++++++++++++-------------------- + 2 files changed, 56 insertions(+), 64 deletions(-) + +--- a/drivers/net/dsa/mt7530.c ++++ b/drivers/net/dsa/mt7530.c +@@ -1100,42 +1100,34 @@ mt753x_trap_frames(struct mt7530_priv *p + * VLAN-untagged. + */ + mt7530_rmw(priv, MT753X_BPC, +- MT753X_PAE_BPDU_FR | MT753X_PAE_EG_TAG_MASK | +- MT753X_PAE_PORT_FW_MASK | MT753X_BPDU_EG_TAG_MASK | +- MT753X_BPDU_PORT_FW_MASK, +- MT753X_PAE_BPDU_FR | +- MT753X_PAE_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | +- MT753X_PAE_PORT_FW(MT753X_BPDU_CPU_ONLY) | +- MT753X_BPDU_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | +- MT753X_BPDU_CPU_ONLY); ++ PAE_BPDU_FR | PAE_EG_TAG_MASK | PAE_PORT_FW_MASK | ++ BPDU_EG_TAG_MASK | BPDU_PORT_FW_MASK, ++ PAE_BPDU_FR | PAE_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | ++ PAE_PORT_FW(TO_CPU_FW_CPU_ONLY) | ++ BPDU_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | ++ TO_CPU_FW_CPU_ONLY); + + /* Trap frames with :01 and :02 MAC DAs to the CPU port(s) and egress + * them VLAN-untagged. + */ + mt7530_rmw(priv, MT753X_RGAC1, +- MT753X_R02_BPDU_FR | MT753X_R02_EG_TAG_MASK | +- MT753X_R02_PORT_FW_MASK | MT753X_R01_BPDU_FR | +- MT753X_R01_EG_TAG_MASK | MT753X_R01_PORT_FW_MASK, +- MT753X_R02_BPDU_FR | +- MT753X_R02_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | +- MT753X_R02_PORT_FW(MT753X_BPDU_CPU_ONLY) | +- MT753X_R01_BPDU_FR | +- MT753X_R01_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | +- MT753X_BPDU_CPU_ONLY); ++ R02_BPDU_FR | R02_EG_TAG_MASK | R02_PORT_FW_MASK | ++ R01_BPDU_FR | R01_EG_TAG_MASK | R01_PORT_FW_MASK, ++ R02_BPDU_FR | R02_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | ++ R02_PORT_FW(TO_CPU_FW_CPU_ONLY) | R01_BPDU_FR | ++ R01_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | ++ TO_CPU_FW_CPU_ONLY); + + /* Trap frames with :03 and :0E MAC DAs to the CPU port(s) and egress + * them VLAN-untagged. + */ + mt7530_rmw(priv, MT753X_RGAC2, +- MT753X_R0E_BPDU_FR | MT753X_R0E_EG_TAG_MASK | +- MT753X_R0E_PORT_FW_MASK | MT753X_R03_BPDU_FR | +- MT753X_R03_EG_TAG_MASK | MT753X_R03_PORT_FW_MASK, +- MT753X_R0E_BPDU_FR | +- MT753X_R0E_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | +- MT753X_R0E_PORT_FW(MT753X_BPDU_CPU_ONLY) | +- MT753X_R03_BPDU_FR | +- MT753X_R03_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | +- MT753X_BPDU_CPU_ONLY); ++ R0E_BPDU_FR | R0E_EG_TAG_MASK | R0E_PORT_FW_MASK | ++ R03_BPDU_FR | R03_EG_TAG_MASK | R03_PORT_FW_MASK, ++ R0E_BPDU_FR | R0E_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | ++ R0E_PORT_FW(TO_CPU_FW_CPU_ONLY) | R03_BPDU_FR | ++ R03_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | ++ TO_CPU_FW_CPU_ONLY); + } + + static void +--- a/drivers/net/dsa/mt7530.h ++++ b/drivers/net/dsa/mt7530.h +@@ -67,47 +67,47 @@ enum mt753x_id { + #define MT753X_MIRROR_MASK(id) ((((id) == ID_MT7531) || ((id) == ID_MT7988)) ? \ + MT7531_MIRROR_MASK : MIRROR_MASK) + +-/* Registers for BPDU and PAE frame control*/ ++/* Register for BPDU and PAE frame control */ + #define MT753X_BPC 0x24 +-#define MT753X_PAE_BPDU_FR BIT(25) +-#define MT753X_PAE_EG_TAG_MASK GENMASK(24, 22) +-#define MT753X_PAE_EG_TAG(x) FIELD_PREP(MT753X_PAE_EG_TAG_MASK, x) +-#define MT753X_PAE_PORT_FW_MASK GENMASK(18, 16) +-#define MT753X_PAE_PORT_FW(x) FIELD_PREP(MT753X_PAE_PORT_FW_MASK, x) +-#define MT753X_BPDU_EG_TAG_MASK GENMASK(8, 6) +-#define MT753X_BPDU_EG_TAG(x) FIELD_PREP(MT753X_BPDU_EG_TAG_MASK, x) +-#define MT753X_BPDU_PORT_FW_MASK GENMASK(2, 0) ++#define PAE_BPDU_FR BIT(25) ++#define PAE_EG_TAG_MASK GENMASK(24, 22) ++#define PAE_EG_TAG(x) FIELD_PREP(PAE_EG_TAG_MASK, x) ++#define PAE_PORT_FW_MASK GENMASK(18, 16) ++#define PAE_PORT_FW(x) FIELD_PREP(PAE_PORT_FW_MASK, x) ++#define BPDU_EG_TAG_MASK GENMASK(8, 6) ++#define BPDU_EG_TAG(x) FIELD_PREP(BPDU_EG_TAG_MASK, x) ++#define BPDU_PORT_FW_MASK GENMASK(2, 0) + +-/* Register for :01 and :02 MAC DA frame control */ ++/* Register for 01-80-C2-00-00-[01,02] MAC DA frame control */ + #define MT753X_RGAC1 0x28 +-#define MT753X_R02_BPDU_FR BIT(25) +-#define MT753X_R02_EG_TAG_MASK GENMASK(24, 22) +-#define MT753X_R02_EG_TAG(x) FIELD_PREP(MT753X_R02_EG_TAG_MASK, x) +-#define MT753X_R02_PORT_FW_MASK GENMASK(18, 16) +-#define MT753X_R02_PORT_FW(x) FIELD_PREP(MT753X_R02_PORT_FW_MASK, x) +-#define MT753X_R01_BPDU_FR BIT(9) +-#define MT753X_R01_EG_TAG_MASK GENMASK(8, 6) +-#define MT753X_R01_EG_TAG(x) FIELD_PREP(MT753X_R01_EG_TAG_MASK, x) +-#define MT753X_R01_PORT_FW_MASK GENMASK(2, 0) ++#define R02_BPDU_FR BIT(25) ++#define R02_EG_TAG_MASK GENMASK(24, 22) ++#define R02_EG_TAG(x) FIELD_PREP(R02_EG_TAG_MASK, x) ++#define R02_PORT_FW_MASK GENMASK(18, 16) ++#define R02_PORT_FW(x) FIELD_PREP(R02_PORT_FW_MASK, x) ++#define R01_BPDU_FR BIT(9) ++#define R01_EG_TAG_MASK GENMASK(8, 6) ++#define R01_EG_TAG(x) FIELD_PREP(R01_EG_TAG_MASK, x) ++#define R01_PORT_FW_MASK GENMASK(2, 0) + +-/* Register for :03 and :0E MAC DA frame control */ ++/* Register for 01-80-C2-00-00-[03,0E] MAC DA frame control */ + #define MT753X_RGAC2 0x2c +-#define MT753X_R0E_BPDU_FR BIT(25) +-#define MT753X_R0E_EG_TAG_MASK GENMASK(24, 22) +-#define MT753X_R0E_EG_TAG(x) FIELD_PREP(MT753X_R0E_EG_TAG_MASK, x) +-#define MT753X_R0E_PORT_FW_MASK GENMASK(18, 16) +-#define MT753X_R0E_PORT_FW(x) FIELD_PREP(MT753X_R0E_PORT_FW_MASK, x) +-#define MT753X_R03_BPDU_FR BIT(9) +-#define MT753X_R03_EG_TAG_MASK GENMASK(8, 6) +-#define MT753X_R03_EG_TAG(x) FIELD_PREP(MT753X_R03_EG_TAG_MASK, x) +-#define MT753X_R03_PORT_FW_MASK GENMASK(2, 0) ++#define R0E_BPDU_FR BIT(25) ++#define R0E_EG_TAG_MASK GENMASK(24, 22) ++#define R0E_EG_TAG(x) FIELD_PREP(R0E_EG_TAG_MASK, x) ++#define R0E_PORT_FW_MASK GENMASK(18, 16) ++#define R0E_PORT_FW(x) FIELD_PREP(R0E_PORT_FW_MASK, x) ++#define R03_BPDU_FR BIT(9) ++#define R03_EG_TAG_MASK GENMASK(8, 6) ++#define R03_EG_TAG(x) FIELD_PREP(R03_EG_TAG_MASK, x) ++#define R03_PORT_FW_MASK GENMASK(2, 0) + +-enum mt753x_bpdu_port_fw { +- MT753X_BPDU_FOLLOW_MFC, +- MT753X_BPDU_CPU_EXCLUDE = 4, +- MT753X_BPDU_CPU_INCLUDE = 5, +- MT753X_BPDU_CPU_ONLY = 6, +- MT753X_BPDU_DROP = 7, ++enum mt753x_to_cpu_fw { ++ TO_CPU_FW_SYSTEM_DEFAULT, ++ TO_CPU_FW_CPU_EXCLUDE = 4, ++ TO_CPU_FW_CPU_INCLUDE = 5, ++ TO_CPU_FW_CPU_ONLY = 6, ++ TO_CPU_FW_DROP = 7, + }; + + /* Registers for address table access */ diff --git a/target/linux/generic/backport-6.1/790-58-v6.10-net-dsa-mt7530-refactor-MT7530_MFC-and-MT7531_CFC-ad.patch b/target/linux/generic/backport-6.1/790-58-v6.10-net-dsa-mt7530-refactor-MT7530_MFC-and-MT7531_CFC-ad.patch new file mode 100644 index 0000000000..95cdfac02e --- /dev/null +++ b/target/linux/generic/backport-6.1/790-58-v6.10-net-dsa-mt7530-refactor-MT7530_MFC-and-MT7531_CFC-ad.patch @@ -0,0 +1,201 @@ +From 1dbc1bdc2869e6d2929235c70d64e393aa5a5fa2 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= +Date: Mon, 22 Apr 2024 10:15:12 +0300 +Subject: [PATCH 05/15] net: dsa: mt7530: refactor MT7530_MFC and MT7531_CFC, + add MT7531_QRY_FFP +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +The MT7530_MFC register is on MT7530, MT7531, and the switch on the MT7988 +SoC. Rename it to MT753X_MFC. Bit 7 to 0 differs between MT7530 and +MT7531/MT7988. Add MT7530 prefix to these definitions, and define the +IGMP/MLD Query Frame Flooding Ports mask for MT7531. + +Rename the cases of MIRROR_MASK to MIRROR_PORT_MASK. + +Move mt753x_mirror_port_get() and mt753x_port_mirror_set() to mt7530.h as +macros. + +Signed-off-by: Arınç ÜNAL +--- + drivers/net/dsa/mt7530.c | 38 ++++++++-------------- + drivers/net/dsa/mt7530.h | 69 +++++++++++++++++++++++++--------------- + 2 files changed, 57 insertions(+), 50 deletions(-) + +--- a/drivers/net/dsa/mt7530.c ++++ b/drivers/net/dsa/mt7530.c +@@ -1140,7 +1140,7 @@ mt753x_cpu_port_enable(struct dsa_switch + PORT_SPEC_TAG); + + /* Enable flooding on the CPU port */ +- mt7530_set(priv, MT7530_MFC, BC_FFP(BIT(port)) | UNM_FFP(BIT(port)) | ++ mt7530_set(priv, MT753X_MFC, BC_FFP(BIT(port)) | UNM_FFP(BIT(port)) | + UNU_FFP(BIT(port))); + + /* Add the CPU port to the CPU port bitmap for MT7531 and the switch on +@@ -1304,15 +1304,15 @@ mt7530_port_bridge_flags(struct dsa_swit + flags.val & BR_LEARNING ? 0 : SA_DIS); + + if (flags.mask & BR_FLOOD) +- mt7530_rmw(priv, MT7530_MFC, UNU_FFP(BIT(port)), ++ mt7530_rmw(priv, MT753X_MFC, UNU_FFP(BIT(port)), + flags.val & BR_FLOOD ? UNU_FFP(BIT(port)) : 0); + + if (flags.mask & BR_MCAST_FLOOD) +- mt7530_rmw(priv, MT7530_MFC, UNM_FFP(BIT(port)), ++ mt7530_rmw(priv, MT753X_MFC, UNM_FFP(BIT(port)), + flags.val & BR_MCAST_FLOOD ? UNM_FFP(BIT(port)) : 0); + + if (flags.mask & BR_BCAST_FLOOD) +- mt7530_rmw(priv, MT7530_MFC, BC_FFP(BIT(port)), ++ mt7530_rmw(priv, MT753X_MFC, BC_FFP(BIT(port)), + flags.val & BR_BCAST_FLOOD ? BC_FFP(BIT(port)) : 0); + + return 0; +@@ -1848,20 +1848,6 @@ mt7530_port_vlan_del(struct dsa_switch * + return 0; + } + +-static int mt753x_mirror_port_get(unsigned int id, u32 val) +-{ +- return (id == ID_MT7531 || id == ID_MT7988) ? +- MT7531_MIRROR_PORT_GET(val) : +- MIRROR_PORT(val); +-} +- +-static int mt753x_mirror_port_set(unsigned int id, u32 val) +-{ +- return (id == ID_MT7531 || id == ID_MT7988) ? +- MT7531_MIRROR_PORT_SET(val) : +- MIRROR_PORT(val); +-} +- + static int mt753x_port_mirror_add(struct dsa_switch *ds, int port, + struct dsa_mall_mirror_tc_entry *mirror, + bool ingress, struct netlink_ext_ack *extack) +@@ -1877,14 +1863,14 @@ static int mt753x_port_mirror_add(struct + val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id)); + + /* MT7530 only supports one monitor port */ +- monitor_port = mt753x_mirror_port_get(priv->id, val); ++ monitor_port = MT753X_MIRROR_PORT_GET(priv->id, val); + if (val & MT753X_MIRROR_EN(priv->id) && + monitor_port != mirror->to_local_port) + return -EEXIST; + + val |= MT753X_MIRROR_EN(priv->id); +- val &= ~MT753X_MIRROR_MASK(priv->id); +- val |= mt753x_mirror_port_set(priv->id, mirror->to_local_port); ++ val &= ~MT753X_MIRROR_PORT_MASK(priv->id); ++ val |= MT753X_MIRROR_PORT_SET(priv->id, mirror->to_local_port); + mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val); + + val = mt7530_read(priv, MT7530_PCR_P(port)); +@@ -2524,7 +2510,7 @@ mt7531_setup_common(struct dsa_switch *d + mt7530_mib_reset(ds); + + /* Disable flooding on all ports */ +- mt7530_clear(priv, MT7530_MFC, BC_FFP_MASK | UNM_FFP_MASK | ++ mt7530_clear(priv, MT753X_MFC, BC_FFP_MASK | UNM_FFP_MASK | + UNU_FFP_MASK); + + for (i = 0; i < MT7530_NUM_PORTS; i++) { +@@ -3086,10 +3072,12 @@ mt753x_conduit_state_change(struct dsa_s + else + priv->active_cpu_ports &= ~mask; + +- if (priv->active_cpu_ports) +- val = CPU_EN | CPU_PORT(__ffs(priv->active_cpu_ports)); ++ if (priv->active_cpu_ports) { ++ val = MT7530_CPU_EN | ++ MT7530_CPU_PORT(__ffs(priv->active_cpu_ports)); ++ } + +- mt7530_rmw(priv, MT7530_MFC, CPU_EN | CPU_PORT_MASK, val); ++ mt7530_rmw(priv, MT753X_MFC, MT7530_CPU_EN | MT7530_CPU_PORT_MASK, val); + } + + static int mt7988_setup(struct dsa_switch *ds) +--- a/drivers/net/dsa/mt7530.h ++++ b/drivers/net/dsa/mt7530.h +@@ -36,36 +36,55 @@ enum mt753x_id { + #define MT753X_AGC 0xc + #define LOCAL_EN BIT(7) + +-/* Registers to mac forward control for unknown frames */ +-#define MT7530_MFC 0x10 +-#define BC_FFP(x) (((x) & 0xff) << 24) +-#define BC_FFP_MASK BC_FFP(~0) +-#define UNM_FFP(x) (((x) & 0xff) << 16) +-#define UNM_FFP_MASK UNM_FFP(~0) +-#define UNU_FFP(x) (((x) & 0xff) << 8) +-#define UNU_FFP_MASK UNU_FFP(~0) +-#define CPU_EN BIT(7) +-#define CPU_PORT_MASK GENMASK(6, 4) +-#define CPU_PORT(x) FIELD_PREP(CPU_PORT_MASK, x) +-#define MIRROR_EN BIT(3) +-#define MIRROR_PORT(x) ((x) & 0x7) +-#define MIRROR_MASK 0x7 ++/* Register for MAC forward control */ ++#define MT753X_MFC 0x10 ++#define BC_FFP_MASK GENMASK(31, 24) ++#define BC_FFP(x) FIELD_PREP(BC_FFP_MASK, x) ++#define UNM_FFP_MASK GENMASK(23, 16) ++#define UNM_FFP(x) FIELD_PREP(UNM_FFP_MASK, x) ++#define UNU_FFP_MASK GENMASK(15, 8) ++#define UNU_FFP(x) FIELD_PREP(UNU_FFP_MASK, x) ++#define MT7530_CPU_EN BIT(7) ++#define MT7530_CPU_PORT_MASK GENMASK(6, 4) ++#define MT7530_CPU_PORT(x) FIELD_PREP(MT7530_CPU_PORT_MASK, x) ++#define MT7530_MIRROR_EN BIT(3) ++#define MT7530_MIRROR_PORT_MASK GENMASK(2, 0) ++#define MT7530_MIRROR_PORT_GET(x) FIELD_GET(MT7530_MIRROR_PORT_MASK, x) ++#define MT7530_MIRROR_PORT_SET(x) FIELD_PREP(MT7530_MIRROR_PORT_MASK, x) ++#define MT7531_QRY_FFP_MASK GENMASK(7, 0) ++#define MT7531_QRY_FFP(x) FIELD_PREP(MT7531_QRY_FFP_MASK, x) + +-/* Registers for CPU forward control */ ++/* Register for CPU forward control */ + #define MT7531_CFC 0x4 + #define MT7531_MIRROR_EN BIT(19) +-#define MT7531_MIRROR_MASK (MIRROR_MASK << 16) +-#define MT7531_MIRROR_PORT_GET(x) (((x) >> 16) & MIRROR_MASK) +-#define MT7531_MIRROR_PORT_SET(x) (((x) & MIRROR_MASK) << 16) ++#define MT7531_MIRROR_PORT_MASK GENMASK(18, 16) ++#define MT7531_MIRROR_PORT_GET(x) FIELD_GET(MT7531_MIRROR_PORT_MASK, x) ++#define MT7531_MIRROR_PORT_SET(x) FIELD_PREP(MT7531_MIRROR_PORT_MASK, x) + #define MT7531_CPU_PMAP_MASK GENMASK(7, 0) + #define MT7531_CPU_PMAP(x) FIELD_PREP(MT7531_CPU_PMAP_MASK, x) + +-#define MT753X_MIRROR_REG(id) ((((id) == ID_MT7531) || ((id) == ID_MT7988)) ? \ +- MT7531_CFC : MT7530_MFC) +-#define MT753X_MIRROR_EN(id) ((((id) == ID_MT7531) || ((id) == ID_MT7988)) ? \ +- MT7531_MIRROR_EN : MIRROR_EN) +-#define MT753X_MIRROR_MASK(id) ((((id) == ID_MT7531) || ((id) == ID_MT7988)) ? \ +- MT7531_MIRROR_MASK : MIRROR_MASK) ++#define MT753X_MIRROR_REG(id) ((id == ID_MT7531 || \ ++ id == ID_MT7988) ? \ ++ MT7531_CFC : MT753X_MFC) ++ ++#define MT753X_MIRROR_EN(id) ((id == ID_MT7531 || \ ++ id == ID_MT7988) ? \ ++ MT7531_MIRROR_EN : MT7530_MIRROR_EN) ++ ++#define MT753X_MIRROR_PORT_MASK(id) ((id == ID_MT7531 || \ ++ id == ID_MT7988) ? \ ++ MT7531_MIRROR_PORT_MASK : \ ++ MT7530_MIRROR_PORT_MASK) ++ ++#define MT753X_MIRROR_PORT_GET(id, val) ((id == ID_MT7531 || \ ++ id == ID_MT7988) ? \ ++ MT7531_MIRROR_PORT_GET(val) : \ ++ MT7530_MIRROR_PORT_GET(val)) ++ ++#define MT753X_MIRROR_PORT_SET(id, val) ((id == ID_MT7531 || \ ++ id == ID_MT7988) ? \ ++ MT7531_MIRROR_PORT_SET(val) : \ ++ MT7530_MIRROR_PORT_SET(val)) + + /* Register for BPDU and PAE frame control */ + #define MT753X_BPC 0x24 diff --git a/target/linux/generic/backport-6.1/790-59-v6.10-net-dsa-mt7530-refactor-MT7530_HWTRAP-and-MT7530_MHW.patch b/target/linux/generic/backport-6.1/790-59-v6.10-net-dsa-mt7530-refactor-MT7530_HWTRAP-and-MT7530_MHW.patch new file mode 100644 index 0000000000..d2497d5c90 --- /dev/null +++ b/target/linux/generic/backport-6.1/790-59-v6.10-net-dsa-mt7530-refactor-MT7530_HWTRAP-and-MT7530_MHW.patch @@ -0,0 +1,257 @@ +From 3ccf67597d35c06a7319e407b1c42f78a7966779 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= +Date: Mon, 22 Apr 2024 10:15:13 +0300 +Subject: [PATCH 06/15] net: dsa: mt7530: refactor MT7530_HWTRAP and + MT7530_MHWTRAP +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +The MT7530_HWTRAP and MT7530_MHWTRAP registers are on MT7530 and MT7531. +It's called hardware trap on MT7530, software trap on MT7531. That's +because some bits of the trap on MT7530 cannot be modified by software +whilst all bits of the trap on MT7531 can. Rename the definitions for them +to MT753X_TRAP and MT753X_MTRAP. Add MT7530 and MT7531 prefixes to the +definitions specific to the switch model. + +Remove the extra parentheses from MT7530_XTAL_40MHZ and MT7530_XTAL_20MHZ. + +Rename MHWTRAP_PHY0_SEL, MHWTRAP_MANUAL, and MHWTRAP_PHY_ACCESS to be on +par with the "MT7621 Giga Switch Programming Guide v0.3" document. + +Make an enumaration for the XTAL frequency. Set the data type of the xtal +variable on mt7531_pll_setup() to it. + +Signed-off-by: Arınç ÜNAL +--- + drivers/net/dsa/mt7530.c | 59 ++++++++++++++++++++-------------------- + drivers/net/dsa/mt7530.h | 50 ++++++++++++++++------------------ + 2 files changed, 54 insertions(+), 55 deletions(-) + +--- a/drivers/net/dsa/mt7530.c ++++ b/drivers/net/dsa/mt7530.c +@@ -403,23 +403,23 @@ mt7530_setup_port6(struct dsa_switch *ds + + mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK, P6_INTF_MODE(1)); + +- xtal = mt7530_read(priv, MT7530_MHWTRAP) & HWTRAP_XTAL_MASK; ++ xtal = mt7530_read(priv, MT753X_MTRAP) & MT7530_XTAL_MASK; + +- if (xtal == HWTRAP_XTAL_25MHZ) ++ if (xtal == MT7530_XTAL_25MHZ) + ssc_delta = 0x57; + else + ssc_delta = 0x87; + + if (priv->id == ID_MT7621) { + /* PLL frequency: 125MHz: 1.0GBit */ +- if (xtal == HWTRAP_XTAL_40MHZ) ++ if (xtal == MT7530_XTAL_40MHZ) + ncpo1 = 0x0640; +- if (xtal == HWTRAP_XTAL_25MHZ) ++ if (xtal == MT7530_XTAL_25MHZ) + ncpo1 = 0x0a00; + } else { /* PLL frequency: 250MHz: 2.0Gbit */ +- if (xtal == HWTRAP_XTAL_40MHZ) ++ if (xtal == MT7530_XTAL_40MHZ) + ncpo1 = 0x0c80; +- if (xtal == HWTRAP_XTAL_25MHZ) ++ if (xtal == MT7530_XTAL_25MHZ) + ncpo1 = 0x1400; + } + +@@ -442,19 +442,20 @@ mt7530_setup_port6(struct dsa_switch *ds + static void + mt7531_pll_setup(struct mt7530_priv *priv) + { ++ enum mt7531_xtal_fsel xtal; + u32 top_sig; + u32 hwstrap; +- u32 xtal; + u32 val; + + val = mt7530_read(priv, MT7531_CREV); + top_sig = mt7530_read(priv, MT7531_TOP_SIG_SR); +- hwstrap = mt7530_read(priv, MT7531_HWTRAP); ++ hwstrap = mt7530_read(priv, MT753X_TRAP); + if ((val & CHIP_REV_M) > 0) +- xtal = (top_sig & PAD_MCM_SMI_EN) ? HWTRAP_XTAL_FSEL_40MHZ : +- HWTRAP_XTAL_FSEL_25MHZ; ++ xtal = (top_sig & PAD_MCM_SMI_EN) ? MT7531_XTAL_FSEL_40MHZ : ++ MT7531_XTAL_FSEL_25MHZ; + else +- xtal = hwstrap & HWTRAP_XTAL_FSEL_MASK; ++ xtal = (hwstrap & MT7531_XTAL25) ? MT7531_XTAL_FSEL_25MHZ : ++ MT7531_XTAL_FSEL_40MHZ; + + /* Step 1 : Disable MT7531 COREPLL */ + val = mt7530_read(priv, MT7531_PLLGP_EN); +@@ -483,13 +484,13 @@ mt7531_pll_setup(struct mt7530_priv *pri + usleep_range(25, 35); + + switch (xtal) { +- case HWTRAP_XTAL_FSEL_25MHZ: ++ case MT7531_XTAL_FSEL_25MHZ: + val = mt7530_read(priv, MT7531_PLLGP_CR0); + val &= ~RG_COREPLL_SDM_PCW_M; + val |= 0x140000 << RG_COREPLL_SDM_PCW_S; + mt7530_write(priv, MT7531_PLLGP_CR0, val); + break; +- case HWTRAP_XTAL_FSEL_40MHZ: ++ case MT7531_XTAL_FSEL_40MHZ: + val = mt7530_read(priv, MT7531_PLLGP_CR0); + val &= ~RG_COREPLL_SDM_PCW_M; + val |= 0x190000 << RG_COREPLL_SDM_PCW_S; +@@ -870,20 +871,20 @@ static void mt7530_setup_port5(struct ds + + mutex_lock(&priv->reg_mutex); + +- val = mt7530_read(priv, MT7530_MHWTRAP); ++ val = mt7530_read(priv, MT753X_MTRAP); + +- val |= MHWTRAP_MANUAL | MHWTRAP_P5_MAC_SEL | MHWTRAP_P5_DIS; +- val &= ~MHWTRAP_P5_RGMII_MODE & ~MHWTRAP_PHY0_SEL; ++ val |= MT7530_CHG_TRAP | MT7530_P5_MAC_SEL | MT7530_P5_DIS; ++ val &= ~MT7530_P5_RGMII_MODE & ~MT7530_P5_PHY0_SEL; + + switch (priv->p5_mode) { + /* MUX_PHY_P0: P0 -> P5 -> SoC MAC */ + case MUX_PHY_P0: +- val |= MHWTRAP_PHY0_SEL; ++ val |= MT7530_P5_PHY0_SEL; + fallthrough; + + /* MUX_PHY_P4: P4 -> P5 -> SoC MAC */ + case MUX_PHY_P4: +- val &= ~MHWTRAP_P5_MAC_SEL & ~MHWTRAP_P5_DIS; ++ val &= ~MT7530_P5_MAC_SEL & ~MT7530_P5_DIS; + + /* Setup the MAC by default for the cpu port */ + mt7530_write(priv, MT753X_PMCR_P(5), 0x56300); +@@ -891,13 +892,13 @@ static void mt7530_setup_port5(struct ds + + /* GMAC5: P5 -> SoC MAC or external PHY */ + default: +- val &= ~MHWTRAP_P5_DIS; ++ val &= ~MT7530_P5_DIS; + break; + } + + /* Setup RGMII settings */ + if (phy_interface_mode_is_rgmii(interface)) { +- val |= MHWTRAP_P5_RGMII_MODE; ++ val |= MT7530_P5_RGMII_MODE; + + /* P5 RGMII RX Clock Control: delay setting for 1000M */ + mt7530_write(priv, MT7530_P5RGMIIRXCR, CSR_RGMII_EDGE_ALIGN); +@@ -917,7 +918,7 @@ static void mt7530_setup_port5(struct ds + P5_IO_CLK_DRV(1) | P5_IO_DATA_DRV(1)); + } + +- mt7530_write(priv, MT7530_MHWTRAP, val); ++ mt7530_write(priv, MT753X_MTRAP, val); + + dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, mode=%s, phy-mode=%s\n", val, + mt7530_p5_mode_str(priv->p5_mode), phy_modes(interface)); +@@ -2356,7 +2357,7 @@ mt7530_setup(struct dsa_switch *ds) + } + + /* Waiting for MT7530 got to stable */ +- INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP); ++ INIT_MT7530_DUMMY_POLL(&p, priv, MT753X_TRAP); + ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0, + 20, 1000000); + if (ret < 0) { +@@ -2371,7 +2372,7 @@ mt7530_setup(struct dsa_switch *ds) + return -ENODEV; + } + +- if ((val & HWTRAP_XTAL_MASK) == HWTRAP_XTAL_20MHZ) { ++ if ((val & MT7530_XTAL_MASK) == MT7530_XTAL_20MHZ) { + dev_err(priv->dev, + "MT7530 with a 20MHz XTAL is not supported!\n"); + return -EINVAL; +@@ -2392,12 +2393,12 @@ mt7530_setup(struct dsa_switch *ds) + RD_TAP_MASK, RD_TAP(16)); + + /* Enable port 6 */ +- val = mt7530_read(priv, MT7530_MHWTRAP); +- val &= ~MHWTRAP_P6_DIS & ~MHWTRAP_PHY_ACCESS; +- val |= MHWTRAP_MANUAL; +- mt7530_write(priv, MT7530_MHWTRAP, val); ++ val = mt7530_read(priv, MT753X_MTRAP); ++ val &= ~MT7530_P6_DIS & ~MT7530_PHY_INDIRECT_ACCESS; ++ val |= MT7530_CHG_TRAP; ++ mt7530_write(priv, MT753X_MTRAP, val); + +- if ((val & HWTRAP_XTAL_MASK) == HWTRAP_XTAL_40MHZ) ++ if ((val & MT7530_XTAL_MASK) == MT7530_XTAL_40MHZ) + mt7530_pll_setup(priv); + + mt753x_trap_frames(priv); +@@ -2577,7 +2578,7 @@ mt7531_setup(struct dsa_switch *ds) + } + + /* Waiting for MT7530 got to stable */ +- INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP); ++ INIT_MT7530_DUMMY_POLL(&p, priv, MT753X_TRAP); + ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0, + 20, 1000000); + if (ret < 0) { +--- a/drivers/net/dsa/mt7530.h ++++ b/drivers/net/dsa/mt7530.h +@@ -495,32 +495,30 @@ enum mt7531_clk_skew { + MT7531_CLK_SKEW_REVERSE = 3, + }; + +-/* Register for hw trap status */ +-#define MT7530_HWTRAP 0x7800 +-#define HWTRAP_XTAL_MASK (BIT(10) | BIT(9)) +-#define HWTRAP_XTAL_25MHZ (BIT(10) | BIT(9)) +-#define HWTRAP_XTAL_40MHZ (BIT(10)) +-#define HWTRAP_XTAL_20MHZ (BIT(9)) ++/* Register for trap status */ ++#define MT753X_TRAP 0x7800 ++#define MT7530_XTAL_MASK (BIT(10) | BIT(9)) ++#define MT7530_XTAL_25MHZ (BIT(10) | BIT(9)) ++#define MT7530_XTAL_40MHZ BIT(10) ++#define MT7530_XTAL_20MHZ BIT(9) ++#define MT7531_XTAL25 BIT(7) + +-#define MT7531_HWTRAP 0x7800 +-#define HWTRAP_XTAL_FSEL_MASK BIT(7) +-#define HWTRAP_XTAL_FSEL_25MHZ BIT(7) +-#define HWTRAP_XTAL_FSEL_40MHZ 0 +-/* Unique fields of (M)HWSTRAP for MT7531 */ +-#define XTAL_FSEL_S 7 +-#define XTAL_FSEL_M BIT(7) +-#define PHY_EN BIT(6) +-#define CHG_STRAP BIT(8) ++/* Register for trap modification */ ++#define MT753X_MTRAP 0x7804 ++#define MT7530_P5_PHY0_SEL BIT(20) ++#define MT7530_CHG_TRAP BIT(16) ++#define MT7530_P5_MAC_SEL BIT(13) ++#define MT7530_P6_DIS BIT(8) ++#define MT7530_P5_RGMII_MODE BIT(7) ++#define MT7530_P5_DIS BIT(6) ++#define MT7530_PHY_INDIRECT_ACCESS BIT(5) ++#define MT7531_CHG_STRAP BIT(8) ++#define MT7531_PHY_EN BIT(6) + +-/* Register for hw trap modification */ +-#define MT7530_MHWTRAP 0x7804 +-#define MHWTRAP_PHY0_SEL BIT(20) +-#define MHWTRAP_MANUAL BIT(16) +-#define MHWTRAP_P5_MAC_SEL BIT(13) +-#define MHWTRAP_P6_DIS BIT(8) +-#define MHWTRAP_P5_RGMII_MODE BIT(7) +-#define MHWTRAP_P5_DIS BIT(6) +-#define MHWTRAP_PHY_ACCESS BIT(5) ++enum mt7531_xtal_fsel { ++ MT7531_XTAL_FSEL_25MHZ, ++ MT7531_XTAL_FSEL_40MHZ, ++}; + + /* Register for TOP signal control */ + #define MT7530_TOP_SIG_CTRL 0x7808 diff --git a/target/linux/generic/backport-6.1/790-60-v6.10-net-dsa-mt7530-move-MT753X_MTRAP-operations-for-MT75.patch b/target/linux/generic/backport-6.1/790-60-v6.10-net-dsa-mt7530-move-MT753X_MTRAP-operations-for-MT75.patch new file mode 100644 index 0000000000..e7da939588 --- /dev/null +++ b/target/linux/generic/backport-6.1/790-60-v6.10-net-dsa-mt7530-move-MT753X_MTRAP-operations-for-MT75.patch @@ -0,0 +1,117 @@ +From 2982f395c9a513b168f1e685588f70013cba2f5f Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= +Date: Mon, 22 Apr 2024 10:15:14 +0300 +Subject: [PATCH 07/15] net: dsa: mt7530: move MT753X_MTRAP operations for + MT7530 +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +On MT7530, the media-independent interfaces of port 5 and 6 are controlled +by the MT7530_P5_DIS and MT7530_P6_DIS bits of the hardware trap. Deal with +these bits only when the relevant port is being enabled or disabled. This +ensures that these ports will be disabled when they are not in use. + +Do not set MT7530_CHG_TRAP on mt7530_setup_port5() as that's already being +done on mt7530_setup(). + +Instead of globally setting MT7530_P5_MAC_SEL, clear it, then set it only +on the appropriate case. + +If PHY muxing is detected, clear MT7530_P5_DIS before calling +mt7530_setup_port5(). + +Signed-off-by: Arınç ÜNAL +--- + drivers/net/dsa/mt7530.c | 38 +++++++++++++++++++++++++++----------- + 1 file changed, 27 insertions(+), 11 deletions(-) + +--- a/drivers/net/dsa/mt7530.c ++++ b/drivers/net/dsa/mt7530.c +@@ -873,8 +873,7 @@ static void mt7530_setup_port5(struct ds + + val = mt7530_read(priv, MT753X_MTRAP); + +- val |= MT7530_CHG_TRAP | MT7530_P5_MAC_SEL | MT7530_P5_DIS; +- val &= ~MT7530_P5_RGMII_MODE & ~MT7530_P5_PHY0_SEL; ++ val &= ~MT7530_P5_PHY0_SEL & ~MT7530_P5_MAC_SEL & ~MT7530_P5_RGMII_MODE; + + switch (priv->p5_mode) { + /* MUX_PHY_P0: P0 -> P5 -> SoC MAC */ +@@ -884,15 +883,13 @@ static void mt7530_setup_port5(struct ds + + /* MUX_PHY_P4: P4 -> P5 -> SoC MAC */ + case MUX_PHY_P4: +- val &= ~MT7530_P5_MAC_SEL & ~MT7530_P5_DIS; +- + /* Setup the MAC by default for the cpu port */ + mt7530_write(priv, MT753X_PMCR_P(5), 0x56300); + break; + + /* GMAC5: P5 -> SoC MAC or external PHY */ + default: +- val &= ~MT7530_P5_DIS; ++ val |= MT7530_P5_MAC_SEL; + break; + } + +@@ -1186,6 +1183,14 @@ mt7530_port_enable(struct dsa_switch *ds + + mutex_unlock(&priv->reg_mutex); + ++ if (priv->id != ID_MT7530 && priv->id != ID_MT7621) ++ return 0; ++ ++ if (port == 5) ++ mt7530_clear(priv, MT753X_MTRAP, MT7530_P5_DIS); ++ else if (port == 6) ++ mt7530_clear(priv, MT753X_MTRAP, MT7530_P6_DIS); ++ + return 0; + } + +@@ -1204,6 +1209,14 @@ mt7530_port_disable(struct dsa_switch *d + PCR_MATRIX_CLR); + + mutex_unlock(&priv->reg_mutex); ++ ++ if (priv->id != ID_MT7530 && priv->id != ID_MT7621) ++ return; ++ ++ if (port == 5) ++ mt7530_set(priv, MT753X_MTRAP, MT7530_P5_DIS); ++ else if (port == 6) ++ mt7530_set(priv, MT753X_MTRAP, MT7530_P6_DIS); + } + + static int +@@ -2392,11 +2405,11 @@ mt7530_setup(struct dsa_switch *ds) + mt7530_rmw(priv, MT7530_TRGMII_RD(i), + RD_TAP_MASK, RD_TAP(16)); + +- /* Enable port 6 */ +- val = mt7530_read(priv, MT753X_MTRAP); +- val &= ~MT7530_P6_DIS & ~MT7530_PHY_INDIRECT_ACCESS; +- val |= MT7530_CHG_TRAP; +- mt7530_write(priv, MT753X_MTRAP, val); ++ /* Allow modifying the trap and directly access PHY registers via the ++ * MDIO bus the switch is on. ++ */ ++ mt7530_rmw(priv, MT753X_MTRAP, MT7530_CHG_TRAP | ++ MT7530_PHY_INDIRECT_ACCESS, MT7530_CHG_TRAP); + + if ((val & MT7530_XTAL_MASK) == MT7530_XTAL_40MHZ) + mt7530_pll_setup(priv); +@@ -2479,8 +2492,11 @@ mt7530_setup(struct dsa_switch *ds) + break; + } + +- if (priv->p5_mode == MUX_PHY_P0 || priv->p5_mode == MUX_PHY_P4) ++ if (priv->p5_mode == MUX_PHY_P0 || ++ priv->p5_mode == MUX_PHY_P4) { ++ mt7530_clear(priv, MT753X_MTRAP, MT7530_P5_DIS); + mt7530_setup_port5(ds, interface); ++ } + } + + #ifdef CONFIG_GPIOLIB diff --git a/target/linux/generic/backport-6.1/790-61-v6.10-net-dsa-mt7530-return-mt7530_setup_mdio-mt7531_setup.patch b/target/linux/generic/backport-6.1/790-61-v6.10-net-dsa-mt7530-return-mt7530_setup_mdio-mt7531_setup.patch new file mode 100644 index 0000000000..7cc145327c --- /dev/null +++ b/target/linux/generic/backport-6.1/790-61-v6.10-net-dsa-mt7530-return-mt7530_setup_mdio-mt7531_setup.patch @@ -0,0 +1,39 @@ +From 1f5669efca65564c7533704917f79003c6b36c9c Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= +Date: Mon, 22 Apr 2024 10:15:15 +0300 +Subject: [PATCH 08/15] net: dsa: mt7530: return mt7530_setup_mdio & + mt7531_setup_common on error +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +The mt7530_setup_mdio() and mt7531_setup_common() functions should be +checked for errors. Return if the functions return a non-zero value. + +Signed-off-by: Arınç ÜNAL +--- + drivers/net/dsa/mt7530.c | 6 +++++- + 1 file changed, 5 insertions(+), 1 deletion(-) + +--- a/drivers/net/dsa/mt7530.c ++++ b/drivers/net/dsa/mt7530.c +@@ -2658,7 +2658,9 @@ mt7531_setup(struct dsa_switch *ds) + 0); + } + +- mt7531_setup_common(ds); ++ ret = mt7531_setup_common(ds); ++ if (ret) ++ return ret; + + /* Setup VLAN ID 0 for VLAN-unaware bridges */ + ret = mt7530_setup_vlan0(priv); +@@ -3017,6 +3019,8 @@ mt753x_setup(struct dsa_switch *ds) + ret = mt7530_setup_mdio(priv); + if (ret && priv->irq) + mt7530_free_irq_common(priv); ++ if (ret) ++ return ret; + + /* Initialise the PCS devices */ + for (i = 0; i < priv->ds->num_ports; i++) { diff --git a/target/linux/generic/backport-6.1/790-62-v6.10-net-dsa-mt7530-define-MAC-speed-capabilities-per-swi.patch b/target/linux/generic/backport-6.1/790-62-v6.10-net-dsa-mt7530-define-MAC-speed-capabilities-per-swi.patch new file mode 100644 index 0000000000..f4d19db274 --- /dev/null +++ b/target/linux/generic/backport-6.1/790-62-v6.10-net-dsa-mt7530-define-MAC-speed-capabilities-per-swi.patch @@ -0,0 +1,75 @@ +From 6cc2d4ccd77509df74b7b8ef46bbc6ba0a571318 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= +Date: Mon, 22 Apr 2024 10:15:16 +0300 +Subject: [PATCH 09/15] net: dsa: mt7530: define MAC speed capabilities per + switch model +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +With the support of the MT7988 SoC switch, the MAC speed capabilities +defined on mt753x_phylink_get_caps() won't apply to all switch models +anymore. Move them to more appropriate locations instead of overwriting +config->mac_capabilities. + +Remove the comment on mt753x_phylink_get_caps() as it's become invalid with +the support of MT7531 and MT7988 SoC switch. + +Add break to case 6 of mt7988_mac_port_get_caps() to be explicit. + +Signed-off-by: Arınç ÜNAL +--- + drivers/net/dsa/mt7530.c | 15 ++++++++++----- + 1 file changed, 10 insertions(+), 5 deletions(-) + +--- a/drivers/net/dsa/mt7530.c ++++ b/drivers/net/dsa/mt7530.c +@@ -2676,6 +2676,8 @@ mt7531_setup(struct dsa_switch *ds) + static void mt7530_mac_port_get_caps(struct dsa_switch *ds, int port, + struct phylink_config *config) + { ++ config->mac_capabilities |= MAC_10 | MAC_100 | MAC_1000FD; ++ + switch (port) { + /* Ports which are connected to switch PHYs. There is no MII pinout. */ + case 0 ... 4: +@@ -2707,6 +2709,8 @@ static void mt7531_mac_port_get_caps(str + { + struct mt7530_priv *priv = ds->priv; + ++ config->mac_capabilities |= MAC_10 | MAC_100 | MAC_1000FD; ++ + switch (port) { + /* Ports which are connected to switch PHYs. There is no MII pinout. */ + case 0 ... 4: +@@ -2746,14 +2750,17 @@ static void mt7988_mac_port_get_caps(str + case 0 ... 3: + __set_bit(PHY_INTERFACE_MODE_INTERNAL, + config->supported_interfaces); ++ ++ config->mac_capabilities |= MAC_10 | MAC_100 | MAC_1000FD; + break; + + /* Port 6 is connected to SoC's XGMII MAC. There is no MII pinout. */ + case 6: + __set_bit(PHY_INTERFACE_MODE_INTERNAL, + config->supported_interfaces); +- config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | +- MAC_10000FD; ++ ++ config->mac_capabilities |= MAC_10000FD; ++ break; + } + } + +@@ -2923,9 +2930,7 @@ static void mt753x_phylink_get_caps(stru + { + struct mt7530_priv *priv = ds->priv; + +- /* This switch only supports full-duplex at 1Gbps */ +- config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | +- MAC_10 | MAC_100 | MAC_1000FD; ++ config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE; + + /* This driver does not make use of the speed, duplex, pause or the + * advertisement in its mac_config, so it is safe to mark this driver diff --git a/target/linux/generic/backport-6.1/790-63-v6.10-net-dsa-mt7530-get-rid-of-function-sanity-check.patch b/target/linux/generic/backport-6.1/790-63-v6.10-net-dsa-mt7530-get-rid-of-function-sanity-check.patch new file mode 100644 index 0000000000..5bb7756c51 --- /dev/null +++ b/target/linux/generic/backport-6.1/790-63-v6.10-net-dsa-mt7530-get-rid-of-function-sanity-check.patch @@ -0,0 +1,33 @@ +From dd0f15fc877c10567699190bce0f55e96f4ad6b5 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= +Date: Mon, 22 Apr 2024 10:15:17 +0300 +Subject: [PATCH 10/15] net: dsa: mt7530: get rid of function sanity check +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Get rid of checking whether functions are filled properly. priv->info which +is an mt753x_info structure is filled and checked for before this check. +It's unnecessary checking whether it's filled properly. + +Signed-off-by: Arınç ÜNAL +--- + drivers/net/dsa/mt7530.c | 7 ------- + 1 file changed, 7 deletions(-) + +--- a/drivers/net/dsa/mt7530.c ++++ b/drivers/net/dsa/mt7530.c +@@ -3220,13 +3220,6 @@ mt7530_probe_common(struct mt7530_priv * + if (!priv->info) + return -EINVAL; + +- /* Sanity check if these required device operations are filled +- * properly. +- */ +- if (!priv->info->sw_setup || !priv->info->phy_read || +- !priv->info->phy_write || !priv->info->mac_port_get_caps) +- return -EINVAL; +- + priv->id = priv->info->id; + priv->dev = dev; + priv->ds->priv = priv; diff --git a/target/linux/generic/backport-6.1/790-64-v6.10-net-dsa-mt7530-refactor-MT7530_PMEEECR_P.patch b/target/linux/generic/backport-6.1/790-64-v6.10-net-dsa-mt7530-refactor-MT7530_PMEEECR_P.patch new file mode 100644 index 0000000000..f8147b6412 --- /dev/null +++ b/target/linux/generic/backport-6.1/790-64-v6.10-net-dsa-mt7530-refactor-MT7530_PMEEECR_P.patch @@ -0,0 +1,71 @@ +From 2dff9759602b069f97ccc939e15a47ca051b2983 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= +Date: Mon, 22 Apr 2024 10:15:18 +0300 +Subject: [PATCH 11/15] net: dsa: mt7530: refactor MT7530_PMEEECR_P() +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +The MT7530_PMEEECR_P() register is on MT7530, MT7531, and the switch on the +MT7988 SoC. Rename the definition for them to MT753X_PMEEECR_P(). Use the +FIELD_PREP and FIELD_GET macros. Rename GET_LPI_THRESH() and +SET_LPI_THRESH() to LPI_THRESH_GET() and LPI_THRESH_SET(). + +Signed-off-by: Arınç ÜNAL +--- + drivers/net/dsa/mt7530.c | 8 ++++---- + drivers/net/dsa/mt7530.h | 13 +++++++------ + 2 files changed, 11 insertions(+), 10 deletions(-) + +--- a/drivers/net/dsa/mt7530.c ++++ b/drivers/net/dsa/mt7530.c +@@ -3048,10 +3048,10 @@ static int mt753x_get_mac_eee(struct dsa + struct ethtool_eee *e) + { + struct mt7530_priv *priv = ds->priv; +- u32 eeecr = mt7530_read(priv, MT7530_PMEEECR_P(port)); ++ u32 eeecr = mt7530_read(priv, MT753X_PMEEECR_P(port)); + + e->tx_lpi_enabled = !(eeecr & LPI_MODE_EN); +- e->tx_lpi_timer = GET_LPI_THRESH(eeecr); ++ e->tx_lpi_timer = LPI_THRESH_GET(eeecr); + + return 0; + } +@@ -3065,11 +3065,11 @@ static int mt753x_set_mac_eee(struct dsa + if (e->tx_lpi_timer > 0xFFF) + return -EINVAL; + +- set = SET_LPI_THRESH(e->tx_lpi_timer); ++ set = LPI_THRESH_SET(e->tx_lpi_timer); + if (!e->tx_lpi_enabled) + /* Force LPI Mode without a delay */ + set |= LPI_MODE_EN; +- mt7530_rmw(priv, MT7530_PMEEECR_P(port), mask, set); ++ mt7530_rmw(priv, MT753X_PMEEECR_P(port), mask, set); + + return 0; + } +--- a/drivers/net/dsa/mt7530.h ++++ b/drivers/net/dsa/mt7530.h +@@ -364,13 +364,14 @@ enum mt7530_vlan_port_acc_frm { + PMCR_FORCE_SPEED_100 | \ + PMCR_FORCE_FDX | PMCR_FORCE_LNK) + +-#define MT7530_PMEEECR_P(x) (0x3004 + (x) * 0x100) +-#define WAKEUP_TIME_1000(x) (((x) & 0xFF) << 24) +-#define WAKEUP_TIME_100(x) (((x) & 0xFF) << 16) ++#define MT753X_PMEEECR_P(x) (0x3004 + (x) * 0x100) ++#define WAKEUP_TIME_1000_MASK GENMASK(31, 24) ++#define WAKEUP_TIME_1000(x) FIELD_PREP(WAKEUP_TIME_1000_MASK, x) ++#define WAKEUP_TIME_100_MASK GENMASK(23, 16) ++#define WAKEUP_TIME_100(x) FIELD_PREP(WAKEUP_TIME_100_MASK, x) + #define LPI_THRESH_MASK GENMASK(15, 4) +-#define LPI_THRESH_SHT 4 +-#define SET_LPI_THRESH(x) (((x) << LPI_THRESH_SHT) & LPI_THRESH_MASK) +-#define GET_LPI_THRESH(x) (((x) & LPI_THRESH_MASK) >> LPI_THRESH_SHT) ++#define LPI_THRESH_GET(x) FIELD_GET(LPI_THRESH_MASK, x) ++#define LPI_THRESH_SET(x) FIELD_PREP(LPI_THRESH_MASK, x) + #define LPI_MODE_EN BIT(0) + + #define MT7530_PMSR_P(x) (0x3008 + (x) * 0x100) diff --git a/target/linux/generic/backport-6.1/790-65-v6.10-net-dsa-mt7530-get-rid-of-mac_port_validate-member-o.patch b/target/linux/generic/backport-6.1/790-65-v6.10-net-dsa-mt7530-get-rid-of-mac_port_validate-member-o.patch new file mode 100644 index 0000000000..7ce2d4c04e --- /dev/null +++ b/target/linux/generic/backport-6.1/790-65-v6.10-net-dsa-mt7530-get-rid-of-mac_port_validate-member-o.patch @@ -0,0 +1,46 @@ +From 21d67c2fabfe40baf33202d3287b67b6c16f8382 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= +Date: Mon, 22 Apr 2024 10:15:19 +0300 +Subject: [PATCH 12/15] net: dsa: mt7530: get rid of mac_port_validate member + of mt753x_info +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +The mac_port_validate member of the mt753x_info structure is not being +used, remove it. Improve the member description section in the process. + +Signed-off-by: Arınç ÜNAL +--- + drivers/net/dsa/mt7530.h | 10 +++------- + 1 file changed, 3 insertions(+), 7 deletions(-) + +--- a/drivers/net/dsa/mt7530.h ++++ b/drivers/net/dsa/mt7530.h +@@ -743,13 +743,12 @@ struct mt753x_pcs { + + /* struct mt753x_info - This is the main data structure for holding the specific + * part for each supported device ++ * @id: Holding the identifier to a switch model ++ * @pcs_ops: Holding the pointer to the MAC PCS operations structure + * @sw_setup: Holding the handler to a device initialization + * @phy_read: Holding the way reading PHY port + * @phy_write: Holding the way writing PHY port +- * @phy_mode_supported: Check if the PHY type is being supported on a certain +- * port +- * @mac_port_validate: Holding the way to set addition validate type for a +- * certan MAC port ++ * @mac_port_get_caps: Holding the handler that provides MAC capabilities + * @mac_port_config: Holding the way setting up the PHY attribute to a + * certain MAC port + */ +@@ -763,9 +762,6 @@ struct mt753x_info { + int (*phy_write)(struct mt7530_priv *priv, int port, int regnum, u16 val); + void (*mac_port_get_caps)(struct dsa_switch *ds, int port, + struct phylink_config *config); +- void (*mac_port_validate)(struct dsa_switch *ds, int port, +- phy_interface_t interface, +- unsigned long *supported); + void (*mac_port_config)(struct dsa_switch *ds, int port, + unsigned int mode, + phy_interface_t interface); diff --git a/target/linux/generic/backport-6.1/790-66-v6.10-net-dsa-mt7530-use-priv-ds-num_ports-instead-of-MT75.patch b/target/linux/generic/backport-6.1/790-66-v6.10-net-dsa-mt7530-use-priv-ds-num_ports-instead-of-MT75.patch new file mode 100644 index 0000000000..0037f97499 --- /dev/null +++ b/target/linux/generic/backport-6.1/790-66-v6.10-net-dsa-mt7530-use-priv-ds-num_ports-instead-of-MT75.patch @@ -0,0 +1,57 @@ +From 6efc8ae3eb0363328f479191a0cf0dc12a16e090 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= +Date: Mon, 22 Apr 2024 10:15:20 +0300 +Subject: [PATCH 13/15] net: dsa: mt7530: use priv->ds->num_ports instead of + MT7530_NUM_PORTS +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Use priv->ds->num_ports on all for loops which configure the switch +registers. In the future, the value of MT7530_NUM_PORTS will depend on +priv->id. Therefore, this change prepares the subdriver for a simpler +implementation. + +Signed-off-by: Arınç ÜNAL +--- + drivers/net/dsa/mt7530.c | 8 ++++---- + 1 file changed, 4 insertions(+), 4 deletions(-) + +--- a/drivers/net/dsa/mt7530.c ++++ b/drivers/net/dsa/mt7530.c +@@ -1404,7 +1404,7 @@ mt7530_port_set_vlan_unaware(struct dsa_ + mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, + G0_PORT_VID_DEF); + +- for (i = 0; i < MT7530_NUM_PORTS; i++) { ++ for (i = 0; i < priv->ds->num_ports; i++) { + if (dsa_is_user_port(ds, i) && + dsa_port_is_vlan_filtering(dsa_to_port(ds, i))) { + all_user_ports_removed = false; +@@ -2419,7 +2419,7 @@ mt7530_setup(struct dsa_switch *ds) + /* Enable and reset MIB counters */ + mt7530_mib_reset(ds); + +- for (i = 0; i < MT7530_NUM_PORTS; i++) { ++ for (i = 0; i < priv->ds->num_ports; i++) { + /* Clear link settings and enable force mode to force link down + * on all ports until they're enabled later. + */ +@@ -2530,7 +2530,7 @@ mt7531_setup_common(struct dsa_switch *d + mt7530_clear(priv, MT753X_MFC, BC_FFP_MASK | UNM_FFP_MASK | + UNU_FFP_MASK); + +- for (i = 0; i < MT7530_NUM_PORTS; i++) { ++ for (i = 0; i < priv->ds->num_ports; i++) { + /* Clear link settings and enable force mode to force link down + * on all ports until they're enabled later. + */ +@@ -2617,7 +2617,7 @@ mt7531_setup(struct dsa_switch *ds) + priv->p5_sgmii = !!(val & PAD_DUAL_SGMII_EN); + + /* Force link down on all ports before internal reset */ +- for (i = 0; i < MT7530_NUM_PORTS; i++) ++ for (i = 0; i < priv->ds->num_ports; i++) + mt7530_write(priv, MT753X_PMCR_P(i), MT7531_FORCE_MODE_LNK); + + /* Reset the switch through internal reset */ diff --git a/target/linux/generic/backport-6.1/790-67-v6.10-net-dsa-mt7530-do-not-pass-port-variable-to-mt7531_r.patch b/target/linux/generic/backport-6.1/790-67-v6.10-net-dsa-mt7530-do-not-pass-port-variable-to-mt7531_r.patch new file mode 100644 index 0000000000..ee8e13ea70 --- /dev/null +++ b/target/linux/generic/backport-6.1/790-67-v6.10-net-dsa-mt7530-do-not-pass-port-variable-to-mt7531_r.patch @@ -0,0 +1,37 @@ +From 4794c12e3aefe05dd0063c2b6b0101854b143bac Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= +Date: Mon, 22 Apr 2024 10:15:21 +0300 +Subject: [PATCH 14/15] net: dsa: mt7530: do not pass port variable to + mt7531_rgmii_setup() +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +The mt7531_rgmii_setup() function does not use the port variable, do not +pass the variable to it. + +Signed-off-by: Arınç ÜNAL +--- + drivers/net/dsa/mt7530.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/net/dsa/mt7530.c ++++ b/drivers/net/dsa/mt7530.c +@@ -2776,7 +2776,7 @@ mt7530_mac_config(struct dsa_switch *ds, + mt7530_setup_port6(priv->ds, interface); + } + +-static void mt7531_rgmii_setup(struct mt7530_priv *priv, u32 port, ++static void mt7531_rgmii_setup(struct mt7530_priv *priv, + phy_interface_t interface, + struct phy_device *phydev) + { +@@ -2827,7 +2827,7 @@ mt7531_mac_config(struct dsa_switch *ds, + if (phy_interface_mode_is_rgmii(interface)) { + dp = dsa_to_port(ds, port); + phydev = dp->slave->phydev; +- mt7531_rgmii_setup(priv, port, interface, phydev); ++ mt7531_rgmii_setup(priv, interface, phydev); + } + } + diff --git a/target/linux/generic/backport-6.1/790-68-v6.10-net-dsa-mt7530-explain-exposing-MDIO-bus-of-MT7531AE.patch b/target/linux/generic/backport-6.1/790-68-v6.10-net-dsa-mt7530-explain-exposing-MDIO-bus-of-MT7531AE.patch new file mode 100644 index 0000000000..666bcb75e8 --- /dev/null +++ b/target/linux/generic/backport-6.1/790-68-v6.10-net-dsa-mt7530-explain-exposing-MDIO-bus-of-MT7531AE.patch @@ -0,0 +1,33 @@ +From c45832fe783f468aaaace09ae95a30cbf0acf724 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= +Date: Mon, 22 Apr 2024 10:15:22 +0300 +Subject: [PATCH 15/15] net: dsa: mt7530: explain exposing MDIO bus of MT7531AE + better +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Unlike MT7531BE, the GPIO 6-12 pins are not used for RGMII on MT7531AE. +Therefore, the GPIO 11-12 pins are set to function as MDC and MDIO to +expose the MDIO bus of the switch. Replace the comment with a better +explanation. + +Signed-off-by: Arınç ÜNAL +--- + drivers/net/dsa/mt7530.c | 5 ++++- + 1 file changed, 4 insertions(+), 1 deletion(-) + +--- a/drivers/net/dsa/mt7530.c ++++ b/drivers/net/dsa/mt7530.c +@@ -2626,7 +2626,10 @@ mt7531_setup(struct dsa_switch *ds) + if (!priv->p5_sgmii) { + mt7531_pll_setup(priv); + } else { +- /* Let ds->slave_mii_bus be able to access external phy. */ ++ /* Unlike MT7531BE, the GPIO 6-12 pins are not used for RGMII on ++ * MT7531AE. Set the GPIO 11-12 pins to function as MDC and MDIO ++ * to expose the MDIO bus of the switch. ++ */ + mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO11_RG_RXD2_MASK, + MT7531_EXT_P_MDC_11); + mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO12_RG_RXD3_MASK, diff --git a/target/linux/generic/backport-6.6/790-38-v6.10-net-dsa-mt7530-disable-EEE-abilities-on-failure-on-M.patch b/target/linux/generic/backport-6.6/790-38-v6.10-net-dsa-mt7530-disable-EEE-abilities-on-failure-on-M.patch new file mode 100644 index 0000000000..44cf60cf14 --- /dev/null +++ b/target/linux/generic/backport-6.6/790-38-v6.10-net-dsa-mt7530-disable-EEE-abilities-on-failure-on-M.patch @@ -0,0 +1,88 @@ +From 856e8954a0a88d1a4d2b43e9002b9249131a156f Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= +Date: Mon, 22 Apr 2024 10:15:08 +0300 +Subject: [PATCH 01/15] net: dsa: mt7530: disable EEE abilities on failure on + MT7531 and MT7988 +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +The MT7531_FORCE_EEE1G and MT7531_FORCE_EEE100 bits let the +PMCR_FORCE_EEE1G and PMCR_FORCE_EEE100 bits determine the 1G/100 EEE +abilities of the MAC. If MT7531_FORCE_EEE1G and MT7531_FORCE_EEE100 are +unset, the abilities are left to be determined by PHY auto polling. + +The commit 40b5d2f15c09 ("net: dsa: mt7530: Add support for EEE features") +made it so that the PMCR_FORCE_EEE1G and PMCR_FORCE_EEE100 bits are set on +mt753x_phylink_mac_link_up(). But it did not set the MT7531_FORCE_EEE1G and +MT7531_FORCE_EEE100 bits. Because of this, the EEE abilities will be +determined by PHY auto polling, regardless of the result of phy_init_eee(). + +Define these bits and add them to the MT7531_FORCE_MODE mask which is set +in mt7531_setup_common(). With this, there won't be any EEE abilities set +when phy_init_eee() returns a negative value. + +Thanks to Russell for explaining when phy_init_eee() could return a +negative value below. + +Looking at phy_init_eee(), it could return a negative value when: + +1. phydev->drv is NULL +2. if genphy_c45_eee_is_active() returns negative +3. if genphy_c45_eee_is_active() returns zero, it returns -EPROTONOSUPPORT +4. if phy_set_bits_mmd() fails (e.g. communication error with the PHY) + +If we then look at genphy_c45_eee_is_active(), then: + +genphy_c45_read_eee_adv() and genphy_c45_read_eee_lpa() propagate their +non-zero return values, otherwise this function returns zero or positive +integer. + +If we then look at genphy_c45_read_eee_adv(), then a failure of +phy_read_mmd() would cause a negative value to be returned. + +Looking at genphy_c45_read_eee_lpa(), the same is true. + +So, it can be summarised as: + +- phydev->drv is NULL +- there is a communication error accessing the PHY +- EEE is not active + +otherwise, it returns zero on success. + +If one wishes to determine whether an error occurred vs EEE not being +supported through negotiation for the negotiated speed, if it returns +-EPROTONOSUPPORT in the latter case. Other error codes mean either the +driver has been unloaded or communication error. + +In conclusion, determining the EEE abilities by PHY auto polling shouldn't +result in having any EEE abilities enabled, when one of the last two +situations in the summary happens. And it seems that if phydev->drv is +NULL, there would be bigger problems with the device than a broken link. So +this is not a bugfix. + +Signed-off-by: Arınç ÜNAL +--- + drivers/net/dsa/mt7530.h | 6 +++++- + 1 file changed, 5 insertions(+), 1 deletion(-) + +--- a/drivers/net/dsa/mt7530.h ++++ b/drivers/net/dsa/mt7530.h +@@ -328,11 +328,15 @@ enum mt7530_vlan_port_acc_frm { + #define MT7531_FORCE_DPX BIT(29) + #define MT7531_FORCE_RX_FC BIT(28) + #define MT7531_FORCE_TX_FC BIT(27) ++#define MT7531_FORCE_EEE100 BIT(26) ++#define MT7531_FORCE_EEE1G BIT(25) + #define MT7531_FORCE_MODE (MT7531_FORCE_LNK | \ + MT7531_FORCE_SPD | \ + MT7531_FORCE_DPX | \ + MT7531_FORCE_RX_FC | \ +- MT7531_FORCE_TX_FC) ++ MT7531_FORCE_TX_FC | \ ++ MT7531_FORCE_EEE100 | \ ++ MT7531_FORCE_EEE1G) + #define PMCR_LINK_SETTINGS_MASK (PMCR_TX_EN | PMCR_FORCE_SPEED_1000 | \ + PMCR_RX_EN | PMCR_FORCE_SPEED_100 | \ + PMCR_TX_FC_EN | PMCR_RX_FC_EN | \ diff --git a/target/linux/generic/backport-6.6/790-39-v6.10-net-dsa-mt7530-refactor-MT7530_PMCR_P.patch b/target/linux/generic/backport-6.6/790-39-v6.10-net-dsa-mt7530-refactor-MT7530_PMCR_P.patch new file mode 100644 index 0000000000..89fad45dd5 --- /dev/null +++ b/target/linux/generic/backport-6.6/790-39-v6.10-net-dsa-mt7530-refactor-MT7530_PMCR_P.patch @@ -0,0 +1,200 @@ +From 712ad00d2f43814c81a7abfcbc339690a05fb6a0 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= +Date: Mon, 22 Apr 2024 10:15:09 +0300 +Subject: [PATCH 02/15] net: dsa: mt7530: refactor MT7530_PMCR_P() +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +The MT7530_PMCR_P() registers are on MT7530, MT7531, and the switch on the +MT7988 SoC. Rename the definition for them to MT753X_PMCR_P(). Bit 15 is +for MT7530 only. Add MT7530 prefix to the definition for bit 15. + +Use GENMASK and FIELD_PREP for PMCR_IFG_XMIT(). + +Rename PMCR_TX_EN and PMCR_RX_EN to PMCR_MAC_TX_EN and PMCR_MAC_TX_EN to +follow the naming on the "MT7621 Giga Switch Programming Guide v0.3", +"MT7531 Reference Manual for Development Board v1.0", and "MT7988A Wi-Fi 7 +Generation Router Platform: Datasheet (Open Version) v0.1" documents. + +These documents show that PMCR_RX_FC_EN is at bit 5. Correct this along +with renaming it to PMCR_FORCE_RX_FC_EN, and the same for PMCR_TX_FC_EN. + +Remove PMCR_SPEED_MASK which doesn't have a use. + +Rename the force mode definitions for MT7531 to FORCE_MODE. Add MASK at the +end for the mask that includes all force mode definitions. + +Signed-off-by: Arınç ÜNAL +--- + drivers/net/dsa/mt7530.c | 24 ++++++++--------- + drivers/net/dsa/mt7530.h | 58 +++++++++++++++++++++------------------- + 2 files changed, 42 insertions(+), 40 deletions(-) + +--- a/drivers/net/dsa/mt7530.c ++++ b/drivers/net/dsa/mt7530.c +@@ -896,7 +896,7 @@ static void mt7530_setup_port5(struct ds + val &= ~MHWTRAP_P5_MAC_SEL & ~MHWTRAP_P5_DIS; + + /* Setup the MAC by default for the cpu port */ +- mt7530_write(priv, MT7530_PMCR_P(5), 0x56300); ++ mt7530_write(priv, MT753X_PMCR_P(5), 0x56300); + break; + case P5_INTF_SEL_GMAC5: + /* MT7530_P5_MODE_GMAC: P5 -> External phy or 2nd GMAC */ +@@ -2444,8 +2444,8 @@ mt7530_setup(struct dsa_switch *ds) + /* Clear link settings and enable force mode to force link down + * on all ports until they're enabled later. + */ +- mt7530_rmw(priv, MT7530_PMCR_P(i), PMCR_LINK_SETTINGS_MASK | +- PMCR_FORCE_MODE, PMCR_FORCE_MODE); ++ mt7530_rmw(priv, MT753X_PMCR_P(i), PMCR_LINK_SETTINGS_MASK | ++ MT7530_FORCE_MODE, MT7530_FORCE_MODE); + + /* Disable forwarding by default on all ports */ + mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK, +@@ -2555,8 +2555,8 @@ mt7531_setup_common(struct dsa_switch *d + /* Clear link settings and enable force mode to force link down + * on all ports until they're enabled later. + */ +- mt7530_rmw(priv, MT7530_PMCR_P(i), PMCR_LINK_SETTINGS_MASK | +- MT7531_FORCE_MODE, MT7531_FORCE_MODE); ++ mt7530_rmw(priv, MT753X_PMCR_P(i), PMCR_LINK_SETTINGS_MASK | ++ MT7531_FORCE_MODE_MASK, MT7531_FORCE_MODE_MASK); + + /* Disable forwarding by default on all ports */ + mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK, +@@ -2639,7 +2639,7 @@ mt7531_setup(struct dsa_switch *ds) + + /* Force link down on all ports before internal reset */ + for (i = 0; i < MT7530_NUM_PORTS; i++) +- mt7530_write(priv, MT7530_PMCR_P(i), MT7531_FORCE_LNK); ++ mt7530_write(priv, MT753X_PMCR_P(i), MT7531_FORCE_MODE_LNK); + + /* Reset the switch through internal reset */ + mt7530_write(priv, MT7530_SYS_CTRL, SYS_CTRL_SW_RST | SYS_CTRL_REG_RST); +@@ -2881,7 +2881,7 @@ mt753x_phylink_mac_config(struct phylink + + /* Are we connected to external phy */ + if (port == 5 && dsa_is_user_port(ds, 5)) +- mt7530_set(priv, MT7530_PMCR_P(port), PMCR_EXT_PHY); ++ mt7530_set(priv, MT753X_PMCR_P(port), PMCR_EXT_PHY); + } + + static void mt753x_phylink_mac_link_down(struct phylink_config *config, +@@ -2891,7 +2891,7 @@ static void mt753x_phylink_mac_link_down + struct dsa_port *dp = dsa_phylink_to_port(config); + struct mt7530_priv *priv = dp->ds->priv; + +- mt7530_clear(priv, MT7530_PMCR_P(dp->index), PMCR_LINK_SETTINGS_MASK); ++ mt7530_clear(priv, MT753X_PMCR_P(dp->index), PMCR_LINK_SETTINGS_MASK); + } + + static void mt753x_phylink_mac_link_up(struct phylink_config *config, +@@ -2905,7 +2905,7 @@ static void mt753x_phylink_mac_link_up(s + struct mt7530_priv *priv = dp->ds->priv; + u32 mcr; + +- mcr = PMCR_RX_EN | PMCR_TX_EN | PMCR_FORCE_LNK; ++ mcr = PMCR_MAC_RX_EN | PMCR_MAC_TX_EN | PMCR_FORCE_LNK; + + switch (speed) { + case SPEED_1000: +@@ -2920,9 +2920,9 @@ static void mt753x_phylink_mac_link_up(s + if (duplex == DUPLEX_FULL) { + mcr |= PMCR_FORCE_FDX; + if (tx_pause) +- mcr |= PMCR_TX_FC_EN; ++ mcr |= PMCR_FORCE_TX_FC_EN; + if (rx_pause) +- mcr |= PMCR_RX_FC_EN; ++ mcr |= PMCR_FORCE_RX_FC_EN; + } + + if (mode == MLO_AN_PHY && phydev && phy_init_eee(phydev, false) >= 0) { +@@ -2937,7 +2937,7 @@ static void mt753x_phylink_mac_link_up(s + } + } + +- mt7530_set(priv, MT7530_PMCR_P(dp->index), mcr); ++ mt7530_set(priv, MT753X_PMCR_P(dp->index), mcr); + } + + static void mt753x_phylink_get_caps(struct dsa_switch *ds, int port, +--- a/drivers/net/dsa/mt7530.h ++++ b/drivers/net/dsa/mt7530.h +@@ -304,44 +304,46 @@ enum mt7530_vlan_port_acc_frm { + #define G0_PORT_VID_DEF G0_PORT_VID(0) + + /* Register for port MAC control register */ +-#define MT7530_PMCR_P(x) (0x3000 + ((x) * 0x100)) +-#define PMCR_IFG_XMIT(x) (((x) & 0x3) << 18) ++#define MT753X_PMCR_P(x) (0x3000 + ((x) * 0x100)) ++#define PMCR_IFG_XMIT_MASK GENMASK(19, 18) ++#define PMCR_IFG_XMIT(x) FIELD_PREP(PMCR_IFG_XMIT_MASK, x) + #define PMCR_EXT_PHY BIT(17) + #define PMCR_MAC_MODE BIT(16) +-#define PMCR_FORCE_MODE BIT(15) +-#define PMCR_TX_EN BIT(14) +-#define PMCR_RX_EN BIT(13) ++#define MT7530_FORCE_MODE BIT(15) ++#define PMCR_MAC_TX_EN BIT(14) ++#define PMCR_MAC_RX_EN BIT(13) + #define PMCR_BACKOFF_EN BIT(9) + #define PMCR_BACKPR_EN BIT(8) + #define PMCR_FORCE_EEE1G BIT(7) + #define PMCR_FORCE_EEE100 BIT(6) +-#define PMCR_TX_FC_EN BIT(5) +-#define PMCR_RX_FC_EN BIT(4) ++#define PMCR_FORCE_RX_FC_EN BIT(5) ++#define PMCR_FORCE_TX_FC_EN BIT(4) + #define PMCR_FORCE_SPEED_1000 BIT(3) + #define PMCR_FORCE_SPEED_100 BIT(2) + #define PMCR_FORCE_FDX BIT(1) + #define PMCR_FORCE_LNK BIT(0) +-#define PMCR_SPEED_MASK (PMCR_FORCE_SPEED_100 | \ +- PMCR_FORCE_SPEED_1000) +-#define MT7531_FORCE_LNK BIT(31) +-#define MT7531_FORCE_SPD BIT(30) +-#define MT7531_FORCE_DPX BIT(29) +-#define MT7531_FORCE_RX_FC BIT(28) +-#define MT7531_FORCE_TX_FC BIT(27) +-#define MT7531_FORCE_EEE100 BIT(26) +-#define MT7531_FORCE_EEE1G BIT(25) +-#define MT7531_FORCE_MODE (MT7531_FORCE_LNK | \ +- MT7531_FORCE_SPD | \ +- MT7531_FORCE_DPX | \ +- MT7531_FORCE_RX_FC | \ +- MT7531_FORCE_TX_FC | \ +- MT7531_FORCE_EEE100 | \ +- MT7531_FORCE_EEE1G) +-#define PMCR_LINK_SETTINGS_MASK (PMCR_TX_EN | PMCR_FORCE_SPEED_1000 | \ +- PMCR_RX_EN | PMCR_FORCE_SPEED_100 | \ +- PMCR_TX_FC_EN | PMCR_RX_FC_EN | \ +- PMCR_FORCE_FDX | PMCR_FORCE_LNK | \ +- PMCR_FORCE_EEE1G | PMCR_FORCE_EEE100) ++#define MT7531_FORCE_MODE_LNK BIT(31) ++#define MT7531_FORCE_MODE_SPD BIT(30) ++#define MT7531_FORCE_MODE_DPX BIT(29) ++#define MT7531_FORCE_MODE_RX_FC BIT(28) ++#define MT7531_FORCE_MODE_TX_FC BIT(27) ++#define MT7531_FORCE_MODE_EEE100 BIT(26) ++#define MT7531_FORCE_MODE_EEE1G BIT(25) ++#define MT7531_FORCE_MODE_MASK (MT7531_FORCE_MODE_LNK | \ ++ MT7531_FORCE_MODE_SPD | \ ++ MT7531_FORCE_MODE_DPX | \ ++ MT7531_FORCE_MODE_RX_FC | \ ++ MT7531_FORCE_MODE_TX_FC | \ ++ MT7531_FORCE_MODE_EEE100 | \ ++ MT7531_FORCE_MODE_EEE1G) ++#define PMCR_LINK_SETTINGS_MASK (PMCR_MAC_TX_EN | PMCR_MAC_RX_EN | \ ++ PMCR_FORCE_EEE1G | \ ++ PMCR_FORCE_EEE100 | \ ++ PMCR_FORCE_RX_FC_EN | \ ++ PMCR_FORCE_TX_FC_EN | \ ++ PMCR_FORCE_SPEED_1000 | \ ++ PMCR_FORCE_SPEED_100 | \ ++ PMCR_FORCE_FDX | PMCR_FORCE_LNK) + + #define MT7530_PMEEECR_P(x) (0x3004 + (x) * 0x100) + #define WAKEUP_TIME_1000(x) (((x) & 0xFF) << 24) diff --git a/target/linux/generic/backport-6.6/790-40-v6.10-net-dsa-mt7530-rename-p5_intf_sel-and-use-only-for-M.patch b/target/linux/generic/backport-6.6/790-40-v6.10-net-dsa-mt7530-rename-p5_intf_sel-and-use-only-for-M.patch new file mode 100644 index 0000000000..601171a594 --- /dev/null +++ b/target/linux/generic/backport-6.6/790-40-v6.10-net-dsa-mt7530-rename-p5_intf_sel-and-use-only-for-M.patch @@ -0,0 +1,185 @@ +From 875ec5b67ab88e969b171e6e9ea803e3ed759614 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= +Date: Mon, 22 Apr 2024 10:15:10 +0300 +Subject: [PATCH 03/15] net: dsa: mt7530: rename p5_intf_sel and use only for + MT7530 switch +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +The p5_intf_sel pointer is used to store the information of whether PHY +muxing is used or not. PHY muxing is a feature specific to port 5 of the +MT7530 switch. Do not use it for other switch models. + +Rename the pointer to p5_mode to store the mode the port is being used in. +Rename the p5_interface_select enum to mt7530_p5_mode, the string +representation to mt7530_p5_mode_str, and the enum elements. + +If PHY muxing is not detected, the default mode, GMAC5, will be used. + +Signed-off-by: Arınç ÜNAL +--- + drivers/net/dsa/mt7530.c | 62 +++++++++++++++++----------------------- + drivers/net/dsa/mt7530.h | 15 +++++----- + 2 files changed, 33 insertions(+), 44 deletions(-) + +--- a/drivers/net/dsa/mt7530.c ++++ b/drivers/net/dsa/mt7530.c +@@ -857,19 +857,15 @@ mt7530_set_ageing_time(struct dsa_switch + return 0; + } + +-static const char *p5_intf_modes(unsigned int p5_interface) ++static const char *mt7530_p5_mode_str(unsigned int mode) + { +- switch (p5_interface) { +- case P5_DISABLED: +- return "DISABLED"; +- case P5_INTF_SEL_PHY_P0: +- return "PHY P0"; +- case P5_INTF_SEL_PHY_P4: +- return "PHY P4"; +- case P5_INTF_SEL_GMAC5: +- return "GMAC5"; ++ switch (mode) { ++ case MUX_PHY_P0: ++ return "MUX PHY P0"; ++ case MUX_PHY_P4: ++ return "MUX PHY P4"; + default: +- return "unknown"; ++ return "GMAC5"; + } + } + +@@ -886,23 +882,23 @@ static void mt7530_setup_port5(struct ds + val |= MHWTRAP_MANUAL | MHWTRAP_P5_MAC_SEL | MHWTRAP_P5_DIS; + val &= ~MHWTRAP_P5_RGMII_MODE & ~MHWTRAP_PHY0_SEL; + +- switch (priv->p5_intf_sel) { +- case P5_INTF_SEL_PHY_P0: +- /* MT7530_P5_MODE_GPHY_P0: 2nd GMAC -> P5 -> P0 */ ++ switch (priv->p5_mode) { ++ /* MUX_PHY_P0: P0 -> P5 -> SoC MAC */ ++ case MUX_PHY_P0: + val |= MHWTRAP_PHY0_SEL; + fallthrough; +- case P5_INTF_SEL_PHY_P4: +- /* MT7530_P5_MODE_GPHY_P4: 2nd GMAC -> P5 -> P4 */ ++ ++ /* MUX_PHY_P4: P4 -> P5 -> SoC MAC */ ++ case MUX_PHY_P4: + val &= ~MHWTRAP_P5_MAC_SEL & ~MHWTRAP_P5_DIS; + + /* Setup the MAC by default for the cpu port */ + mt7530_write(priv, MT753X_PMCR_P(5), 0x56300); + break; +- case P5_INTF_SEL_GMAC5: +- /* MT7530_P5_MODE_GMAC: P5 -> External phy or 2nd GMAC */ +- val &= ~MHWTRAP_P5_DIS; +- break; ++ ++ /* GMAC5: P5 -> SoC MAC or external PHY */ + default: ++ val &= ~MHWTRAP_P5_DIS; + break; + } + +@@ -930,8 +926,8 @@ static void mt7530_setup_port5(struct ds + + mt7530_write(priv, MT7530_MHWTRAP, val); + +- dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, intf_sel=%s, phy-mode=%s\n", +- val, p5_intf_modes(priv->p5_intf_sel), phy_modes(interface)); ++ dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, mode=%s, phy-mode=%s\n", val, ++ mt7530_p5_mode_str(priv->p5_mode), phy_modes(interface)); + + mutex_unlock(&priv->reg_mutex); + } +@@ -2476,13 +2472,11 @@ mt7530_setup(struct dsa_switch *ds) + if (ret) + return ret; + +- /* Setup port 5 */ +- if (!dsa_is_unused_port(ds, 5)) { +- priv->p5_intf_sel = P5_INTF_SEL_GMAC5; +- } else { ++ /* Check for PHY muxing on port 5 */ ++ if (dsa_is_unused_port(ds, 5)) { + /* Scan the ethernet nodes. Look for GMAC1, lookup the used PHY. +- * Set priv->p5_intf_sel to the appropriate value if PHY muxing +- * is detected. ++ * Set priv->p5_mode to the appropriate value if PHY muxing is ++ * detected. + */ + for_each_child_of_node(dn, mac_np) { + if (!of_device_is_compatible(mac_np, +@@ -2506,17 +2500,16 @@ mt7530_setup(struct dsa_switch *ds) + } + id = of_mdio_parse_addr(ds->dev, phy_node); + if (id == 0) +- priv->p5_intf_sel = P5_INTF_SEL_PHY_P0; ++ priv->p5_mode = MUX_PHY_P0; + if (id == 4) +- priv->p5_intf_sel = P5_INTF_SEL_PHY_P4; ++ priv->p5_mode = MUX_PHY_P4; + } + of_node_put(mac_np); + of_node_put(phy_node); + break; + } + +- if (priv->p5_intf_sel == P5_INTF_SEL_PHY_P0 || +- priv->p5_intf_sel == P5_INTF_SEL_PHY_P4) ++ if (priv->p5_mode == MUX_PHY_P0 || priv->p5_mode == MUX_PHY_P4) + mt7530_setup_port5(ds, interface); + } + +@@ -2654,9 +2647,6 @@ mt7531_setup(struct dsa_switch *ds) + MT7531_EXT_P_MDIO_12); + } + +- if (!dsa_is_unused_port(ds, 5)) +- priv->p5_intf_sel = P5_INTF_SEL_GMAC5; +- + mt7530_rmw(priv, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK, + MT7531_GPIO0_INTERRUPT); + +--- a/drivers/net/dsa/mt7530.h ++++ b/drivers/net/dsa/mt7530.h +@@ -708,12 +708,11 @@ struct mt7530_port { + struct phylink_pcs *sgmii_pcs; + }; + +-/* Port 5 interface select definitions */ +-enum p5_interface_select { +- P5_DISABLED, +- P5_INTF_SEL_PHY_P0, +- P5_INTF_SEL_PHY_P4, +- P5_INTF_SEL_GMAC5, ++/* Port 5 mode definitions of the MT7530 switch */ ++enum mt7530_p5_mode { ++ GMAC5, ++ MUX_PHY_P0, ++ MUX_PHY_P4, + }; + + struct mt7530_priv; +@@ -776,7 +775,7 @@ struct mt753x_info { + * @ports: Holding the state among ports + * @reg_mutex: The lock for protecting among process accessing + * registers +- * @p5_intf_sel: Holding the current port 5 interface select ++ * @p5_mode: Holding the current mode of port 5 of the MT7530 switch + * @p5_sgmii: Flag for distinguishing if port 5 of the MT7531 switch + * has got SGMII + * @irq: IRQ number of the switch +@@ -798,7 +797,7 @@ struct mt7530_priv { + const struct mt753x_info *info; + unsigned int id; + bool mcm; +- enum p5_interface_select p5_intf_sel; ++ enum mt7530_p5_mode p5_mode; + bool p5_sgmii; + u8 mirror_rx; + u8 mirror_tx; diff --git a/target/linux/generic/backport-6.6/790-41-v6.10-net-dsa-mt7530-rename-mt753x_bpdu_port_fw-enum-to-mt.patch b/target/linux/generic/backport-6.6/790-41-v6.10-net-dsa-mt7530-rename-mt753x_bpdu_port_fw-enum-to-mt.patch new file mode 100644 index 0000000000..948baf58d0 --- /dev/null +++ b/target/linux/generic/backport-6.6/790-41-v6.10-net-dsa-mt7530-rename-mt753x_bpdu_port_fw-enum-to-mt.patch @@ -0,0 +1,169 @@ +From 83fe3df057e641cd0e88425e579d7a5a370ca430 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= +Date: Mon, 22 Apr 2024 10:15:11 +0300 +Subject: [PATCH 04/15] net: dsa: mt7530: rename mt753x_bpdu_port_fw enum to + mt753x_to_cpu_fw +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +The mt753x_bpdu_port_fw enum is globally used for manipulating the process +of deciding the forwardable ports, specifically concerning the CPU port(s). +Therefore, rename it and the values in it to mt753x_to_cpu_fw. + +Change FOLLOW_MFC to SYSTEM_DEFAULT to be on par with the switch documents. + +Signed-off-by: Arınç ÜNAL +--- + drivers/net/dsa/mt7530.c | 44 ++++++++++------------- + drivers/net/dsa/mt7530.h | 76 ++++++++++++++++++++-------------------- + 2 files changed, 56 insertions(+), 64 deletions(-) + +--- a/drivers/net/dsa/mt7530.c ++++ b/drivers/net/dsa/mt7530.c +@@ -1107,42 +1107,34 @@ mt753x_trap_frames(struct mt7530_priv *p + * VLAN-untagged. + */ + mt7530_rmw(priv, MT753X_BPC, +- MT753X_PAE_BPDU_FR | MT753X_PAE_EG_TAG_MASK | +- MT753X_PAE_PORT_FW_MASK | MT753X_BPDU_EG_TAG_MASK | +- MT753X_BPDU_PORT_FW_MASK, +- MT753X_PAE_BPDU_FR | +- MT753X_PAE_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | +- MT753X_PAE_PORT_FW(MT753X_BPDU_CPU_ONLY) | +- MT753X_BPDU_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | +- MT753X_BPDU_CPU_ONLY); ++ PAE_BPDU_FR | PAE_EG_TAG_MASK | PAE_PORT_FW_MASK | ++ BPDU_EG_TAG_MASK | BPDU_PORT_FW_MASK, ++ PAE_BPDU_FR | PAE_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | ++ PAE_PORT_FW(TO_CPU_FW_CPU_ONLY) | ++ BPDU_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | ++ TO_CPU_FW_CPU_ONLY); + + /* Trap frames with :01 and :02 MAC DAs to the CPU port(s) and egress + * them VLAN-untagged. + */ + mt7530_rmw(priv, MT753X_RGAC1, +- MT753X_R02_BPDU_FR | MT753X_R02_EG_TAG_MASK | +- MT753X_R02_PORT_FW_MASK | MT753X_R01_BPDU_FR | +- MT753X_R01_EG_TAG_MASK | MT753X_R01_PORT_FW_MASK, +- MT753X_R02_BPDU_FR | +- MT753X_R02_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | +- MT753X_R02_PORT_FW(MT753X_BPDU_CPU_ONLY) | +- MT753X_R01_BPDU_FR | +- MT753X_R01_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | +- MT753X_BPDU_CPU_ONLY); ++ R02_BPDU_FR | R02_EG_TAG_MASK | R02_PORT_FW_MASK | ++ R01_BPDU_FR | R01_EG_TAG_MASK | R01_PORT_FW_MASK, ++ R02_BPDU_FR | R02_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | ++ R02_PORT_FW(TO_CPU_FW_CPU_ONLY) | R01_BPDU_FR | ++ R01_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | ++ TO_CPU_FW_CPU_ONLY); + + /* Trap frames with :03 and :0E MAC DAs to the CPU port(s) and egress + * them VLAN-untagged. + */ + mt7530_rmw(priv, MT753X_RGAC2, +- MT753X_R0E_BPDU_FR | MT753X_R0E_EG_TAG_MASK | +- MT753X_R0E_PORT_FW_MASK | MT753X_R03_BPDU_FR | +- MT753X_R03_EG_TAG_MASK | MT753X_R03_PORT_FW_MASK, +- MT753X_R0E_BPDU_FR | +- MT753X_R0E_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | +- MT753X_R0E_PORT_FW(MT753X_BPDU_CPU_ONLY) | +- MT753X_R03_BPDU_FR | +- MT753X_R03_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | +- MT753X_BPDU_CPU_ONLY); ++ R0E_BPDU_FR | R0E_EG_TAG_MASK | R0E_PORT_FW_MASK | ++ R03_BPDU_FR | R03_EG_TAG_MASK | R03_PORT_FW_MASK, ++ R0E_BPDU_FR | R0E_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | ++ R0E_PORT_FW(TO_CPU_FW_CPU_ONLY) | R03_BPDU_FR | ++ R03_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | ++ TO_CPU_FW_CPU_ONLY); + } + + static void +--- a/drivers/net/dsa/mt7530.h ++++ b/drivers/net/dsa/mt7530.h +@@ -67,47 +67,47 @@ enum mt753x_id { + #define MT753X_MIRROR_MASK(id) ((((id) == ID_MT7531) || ((id) == ID_MT7988)) ? \ + MT7531_MIRROR_MASK : MIRROR_MASK) + +-/* Registers for BPDU and PAE frame control*/ ++/* Register for BPDU and PAE frame control */ + #define MT753X_BPC 0x24 +-#define MT753X_PAE_BPDU_FR BIT(25) +-#define MT753X_PAE_EG_TAG_MASK GENMASK(24, 22) +-#define MT753X_PAE_EG_TAG(x) FIELD_PREP(MT753X_PAE_EG_TAG_MASK, x) +-#define MT753X_PAE_PORT_FW_MASK GENMASK(18, 16) +-#define MT753X_PAE_PORT_FW(x) FIELD_PREP(MT753X_PAE_PORT_FW_MASK, x) +-#define MT753X_BPDU_EG_TAG_MASK GENMASK(8, 6) +-#define MT753X_BPDU_EG_TAG(x) FIELD_PREP(MT753X_BPDU_EG_TAG_MASK, x) +-#define MT753X_BPDU_PORT_FW_MASK GENMASK(2, 0) ++#define PAE_BPDU_FR BIT(25) ++#define PAE_EG_TAG_MASK GENMASK(24, 22) ++#define PAE_EG_TAG(x) FIELD_PREP(PAE_EG_TAG_MASK, x) ++#define PAE_PORT_FW_MASK GENMASK(18, 16) ++#define PAE_PORT_FW(x) FIELD_PREP(PAE_PORT_FW_MASK, x) ++#define BPDU_EG_TAG_MASK GENMASK(8, 6) ++#define BPDU_EG_TAG(x) FIELD_PREP(BPDU_EG_TAG_MASK, x) ++#define BPDU_PORT_FW_MASK GENMASK(2, 0) + +-/* Register for :01 and :02 MAC DA frame control */ ++/* Register for 01-80-C2-00-00-[01,02] MAC DA frame control */ + #define MT753X_RGAC1 0x28 +-#define MT753X_R02_BPDU_FR BIT(25) +-#define MT753X_R02_EG_TAG_MASK GENMASK(24, 22) +-#define MT753X_R02_EG_TAG(x) FIELD_PREP(MT753X_R02_EG_TAG_MASK, x) +-#define MT753X_R02_PORT_FW_MASK GENMASK(18, 16) +-#define MT753X_R02_PORT_FW(x) FIELD_PREP(MT753X_R02_PORT_FW_MASK, x) +-#define MT753X_R01_BPDU_FR BIT(9) +-#define MT753X_R01_EG_TAG_MASK GENMASK(8, 6) +-#define MT753X_R01_EG_TAG(x) FIELD_PREP(MT753X_R01_EG_TAG_MASK, x) +-#define MT753X_R01_PORT_FW_MASK GENMASK(2, 0) ++#define R02_BPDU_FR BIT(25) ++#define R02_EG_TAG_MASK GENMASK(24, 22) ++#define R02_EG_TAG(x) FIELD_PREP(R02_EG_TAG_MASK, x) ++#define R02_PORT_FW_MASK GENMASK(18, 16) ++#define R02_PORT_FW(x) FIELD_PREP(R02_PORT_FW_MASK, x) ++#define R01_BPDU_FR BIT(9) ++#define R01_EG_TAG_MASK GENMASK(8, 6) ++#define R01_EG_TAG(x) FIELD_PREP(R01_EG_TAG_MASK, x) ++#define R01_PORT_FW_MASK GENMASK(2, 0) + +-/* Register for :03 and :0E MAC DA frame control */ ++/* Register for 01-80-C2-00-00-[03,0E] MAC DA frame control */ + #define MT753X_RGAC2 0x2c +-#define MT753X_R0E_BPDU_FR BIT(25) +-#define MT753X_R0E_EG_TAG_MASK GENMASK(24, 22) +-#define MT753X_R0E_EG_TAG(x) FIELD_PREP(MT753X_R0E_EG_TAG_MASK, x) +-#define MT753X_R0E_PORT_FW_MASK GENMASK(18, 16) +-#define MT753X_R0E_PORT_FW(x) FIELD_PREP(MT753X_R0E_PORT_FW_MASK, x) +-#define MT753X_R03_BPDU_FR BIT(9) +-#define MT753X_R03_EG_TAG_MASK GENMASK(8, 6) +-#define MT753X_R03_EG_TAG(x) FIELD_PREP(MT753X_R03_EG_TAG_MASK, x) +-#define MT753X_R03_PORT_FW_MASK GENMASK(2, 0) ++#define R0E_BPDU_FR BIT(25) ++#define R0E_EG_TAG_MASK GENMASK(24, 22) ++#define R0E_EG_TAG(x) FIELD_PREP(R0E_EG_TAG_MASK, x) ++#define R0E_PORT_FW_MASK GENMASK(18, 16) ++#define R0E_PORT_FW(x) FIELD_PREP(R0E_PORT_FW_MASK, x) ++#define R03_BPDU_FR BIT(9) ++#define R03_EG_TAG_MASK GENMASK(8, 6) ++#define R03_EG_TAG(x) FIELD_PREP(R03_EG_TAG_MASK, x) ++#define R03_PORT_FW_MASK GENMASK(2, 0) + +-enum mt753x_bpdu_port_fw { +- MT753X_BPDU_FOLLOW_MFC, +- MT753X_BPDU_CPU_EXCLUDE = 4, +- MT753X_BPDU_CPU_INCLUDE = 5, +- MT753X_BPDU_CPU_ONLY = 6, +- MT753X_BPDU_DROP = 7, ++enum mt753x_to_cpu_fw { ++ TO_CPU_FW_SYSTEM_DEFAULT, ++ TO_CPU_FW_CPU_EXCLUDE = 4, ++ TO_CPU_FW_CPU_INCLUDE = 5, ++ TO_CPU_FW_CPU_ONLY = 6, ++ TO_CPU_FW_DROP = 7, + }; + + /* Registers for address table access */ diff --git a/target/linux/generic/backport-6.6/790-42-v6.10-net-dsa-mt7530-refactor-MT7530_MFC-and-MT7531_CFC-ad.patch b/target/linux/generic/backport-6.6/790-42-v6.10-net-dsa-mt7530-refactor-MT7530_MFC-and-MT7531_CFC-ad.patch new file mode 100644 index 0000000000..a5d293b509 --- /dev/null +++ b/target/linux/generic/backport-6.6/790-42-v6.10-net-dsa-mt7530-refactor-MT7530_MFC-and-MT7531_CFC-ad.patch @@ -0,0 +1,201 @@ +From 1dbc1bdc2869e6d2929235c70d64e393aa5a5fa2 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= +Date: Mon, 22 Apr 2024 10:15:12 +0300 +Subject: [PATCH 05/15] net: dsa: mt7530: refactor MT7530_MFC and MT7531_CFC, + add MT7531_QRY_FFP +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +The MT7530_MFC register is on MT7530, MT7531, and the switch on the MT7988 +SoC. Rename it to MT753X_MFC. Bit 7 to 0 differs between MT7530 and +MT7531/MT7988. Add MT7530 prefix to these definitions, and define the +IGMP/MLD Query Frame Flooding Ports mask for MT7531. + +Rename the cases of MIRROR_MASK to MIRROR_PORT_MASK. + +Move mt753x_mirror_port_get() and mt753x_port_mirror_set() to mt7530.h as +macros. + +Signed-off-by: Arınç ÜNAL +--- + drivers/net/dsa/mt7530.c | 38 ++++++++-------------- + drivers/net/dsa/mt7530.h | 69 +++++++++++++++++++++++++--------------- + 2 files changed, 57 insertions(+), 50 deletions(-) + +--- a/drivers/net/dsa/mt7530.c ++++ b/drivers/net/dsa/mt7530.c +@@ -1147,7 +1147,7 @@ mt753x_cpu_port_enable(struct dsa_switch + PORT_SPEC_TAG); + + /* Enable flooding on the CPU port */ +- mt7530_set(priv, MT7530_MFC, BC_FFP(BIT(port)) | UNM_FFP(BIT(port)) | ++ mt7530_set(priv, MT753X_MFC, BC_FFP(BIT(port)) | UNM_FFP(BIT(port)) | + UNU_FFP(BIT(port))); + + /* Add the CPU port to the CPU port bitmap for MT7531 and the switch on +@@ -1311,15 +1311,15 @@ mt7530_port_bridge_flags(struct dsa_swit + flags.val & BR_LEARNING ? 0 : SA_DIS); + + if (flags.mask & BR_FLOOD) +- mt7530_rmw(priv, MT7530_MFC, UNU_FFP(BIT(port)), ++ mt7530_rmw(priv, MT753X_MFC, UNU_FFP(BIT(port)), + flags.val & BR_FLOOD ? UNU_FFP(BIT(port)) : 0); + + if (flags.mask & BR_MCAST_FLOOD) +- mt7530_rmw(priv, MT7530_MFC, UNM_FFP(BIT(port)), ++ mt7530_rmw(priv, MT753X_MFC, UNM_FFP(BIT(port)), + flags.val & BR_MCAST_FLOOD ? UNM_FFP(BIT(port)) : 0); + + if (flags.mask & BR_BCAST_FLOOD) +- mt7530_rmw(priv, MT7530_MFC, BC_FFP(BIT(port)), ++ mt7530_rmw(priv, MT753X_MFC, BC_FFP(BIT(port)), + flags.val & BR_BCAST_FLOOD ? BC_FFP(BIT(port)) : 0); + + return 0; +@@ -1855,20 +1855,6 @@ mt7530_port_vlan_del(struct dsa_switch * + return 0; + } + +-static int mt753x_mirror_port_get(unsigned int id, u32 val) +-{ +- return (id == ID_MT7531 || id == ID_MT7988) ? +- MT7531_MIRROR_PORT_GET(val) : +- MIRROR_PORT(val); +-} +- +-static int mt753x_mirror_port_set(unsigned int id, u32 val) +-{ +- return (id == ID_MT7531 || id == ID_MT7988) ? +- MT7531_MIRROR_PORT_SET(val) : +- MIRROR_PORT(val); +-} +- + static int mt753x_port_mirror_add(struct dsa_switch *ds, int port, + struct dsa_mall_mirror_tc_entry *mirror, + bool ingress, struct netlink_ext_ack *extack) +@@ -1884,14 +1870,14 @@ static int mt753x_port_mirror_add(struct + val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id)); + + /* MT7530 only supports one monitor port */ +- monitor_port = mt753x_mirror_port_get(priv->id, val); ++ monitor_port = MT753X_MIRROR_PORT_GET(priv->id, val); + if (val & MT753X_MIRROR_EN(priv->id) && + monitor_port != mirror->to_local_port) + return -EEXIST; + + val |= MT753X_MIRROR_EN(priv->id); +- val &= ~MT753X_MIRROR_MASK(priv->id); +- val |= mt753x_mirror_port_set(priv->id, mirror->to_local_port); ++ val &= ~MT753X_MIRROR_PORT_MASK(priv->id); ++ val |= MT753X_MIRROR_PORT_SET(priv->id, mirror->to_local_port); + mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val); + + val = mt7530_read(priv, MT7530_PCR_P(port)); +@@ -2533,7 +2519,7 @@ mt7531_setup_common(struct dsa_switch *d + mt7530_mib_reset(ds); + + /* Disable flooding on all ports */ +- mt7530_clear(priv, MT7530_MFC, BC_FFP_MASK | UNM_FFP_MASK | ++ mt7530_clear(priv, MT753X_MFC, BC_FFP_MASK | UNM_FFP_MASK | + UNU_FFP_MASK); + + for (i = 0; i < MT7530_NUM_PORTS; i++) { +@@ -3089,10 +3075,12 @@ mt753x_conduit_state_change(struct dsa_s + else + priv->active_cpu_ports &= ~mask; + +- if (priv->active_cpu_ports) +- val = CPU_EN | CPU_PORT(__ffs(priv->active_cpu_ports)); ++ if (priv->active_cpu_ports) { ++ val = MT7530_CPU_EN | ++ MT7530_CPU_PORT(__ffs(priv->active_cpu_ports)); ++ } + +- mt7530_rmw(priv, MT7530_MFC, CPU_EN | CPU_PORT_MASK, val); ++ mt7530_rmw(priv, MT753X_MFC, MT7530_CPU_EN | MT7530_CPU_PORT_MASK, val); + } + + static int mt7988_setup(struct dsa_switch *ds) +--- a/drivers/net/dsa/mt7530.h ++++ b/drivers/net/dsa/mt7530.h +@@ -36,36 +36,55 @@ enum mt753x_id { + #define MT753X_AGC 0xc + #define LOCAL_EN BIT(7) + +-/* Registers to mac forward control for unknown frames */ +-#define MT7530_MFC 0x10 +-#define BC_FFP(x) (((x) & 0xff) << 24) +-#define BC_FFP_MASK BC_FFP(~0) +-#define UNM_FFP(x) (((x) & 0xff) << 16) +-#define UNM_FFP_MASK UNM_FFP(~0) +-#define UNU_FFP(x) (((x) & 0xff) << 8) +-#define UNU_FFP_MASK UNU_FFP(~0) +-#define CPU_EN BIT(7) +-#define CPU_PORT_MASK GENMASK(6, 4) +-#define CPU_PORT(x) FIELD_PREP(CPU_PORT_MASK, x) +-#define MIRROR_EN BIT(3) +-#define MIRROR_PORT(x) ((x) & 0x7) +-#define MIRROR_MASK 0x7 ++/* Register for MAC forward control */ ++#define MT753X_MFC 0x10 ++#define BC_FFP_MASK GENMASK(31, 24) ++#define BC_FFP(x) FIELD_PREP(BC_FFP_MASK, x) ++#define UNM_FFP_MASK GENMASK(23, 16) ++#define UNM_FFP(x) FIELD_PREP(UNM_FFP_MASK, x) ++#define UNU_FFP_MASK GENMASK(15, 8) ++#define UNU_FFP(x) FIELD_PREP(UNU_FFP_MASK, x) ++#define MT7530_CPU_EN BIT(7) ++#define MT7530_CPU_PORT_MASK GENMASK(6, 4) ++#define MT7530_CPU_PORT(x) FIELD_PREP(MT7530_CPU_PORT_MASK, x) ++#define MT7530_MIRROR_EN BIT(3) ++#define MT7530_MIRROR_PORT_MASK GENMASK(2, 0) ++#define MT7530_MIRROR_PORT_GET(x) FIELD_GET(MT7530_MIRROR_PORT_MASK, x) ++#define MT7530_MIRROR_PORT_SET(x) FIELD_PREP(MT7530_MIRROR_PORT_MASK, x) ++#define MT7531_QRY_FFP_MASK GENMASK(7, 0) ++#define MT7531_QRY_FFP(x) FIELD_PREP(MT7531_QRY_FFP_MASK, x) + +-/* Registers for CPU forward control */ ++/* Register for CPU forward control */ + #define MT7531_CFC 0x4 + #define MT7531_MIRROR_EN BIT(19) +-#define MT7531_MIRROR_MASK (MIRROR_MASK << 16) +-#define MT7531_MIRROR_PORT_GET(x) (((x) >> 16) & MIRROR_MASK) +-#define MT7531_MIRROR_PORT_SET(x) (((x) & MIRROR_MASK) << 16) ++#define MT7531_MIRROR_PORT_MASK GENMASK(18, 16) ++#define MT7531_MIRROR_PORT_GET(x) FIELD_GET(MT7531_MIRROR_PORT_MASK, x) ++#define MT7531_MIRROR_PORT_SET(x) FIELD_PREP(MT7531_MIRROR_PORT_MASK, x) + #define MT7531_CPU_PMAP_MASK GENMASK(7, 0) + #define MT7531_CPU_PMAP(x) FIELD_PREP(MT7531_CPU_PMAP_MASK, x) + +-#define MT753X_MIRROR_REG(id) ((((id) == ID_MT7531) || ((id) == ID_MT7988)) ? \ +- MT7531_CFC : MT7530_MFC) +-#define MT753X_MIRROR_EN(id) ((((id) == ID_MT7531) || ((id) == ID_MT7988)) ? \ +- MT7531_MIRROR_EN : MIRROR_EN) +-#define MT753X_MIRROR_MASK(id) ((((id) == ID_MT7531) || ((id) == ID_MT7988)) ? \ +- MT7531_MIRROR_MASK : MIRROR_MASK) ++#define MT753X_MIRROR_REG(id) ((id == ID_MT7531 || \ ++ id == ID_MT7988) ? \ ++ MT7531_CFC : MT753X_MFC) ++ ++#define MT753X_MIRROR_EN(id) ((id == ID_MT7531 || \ ++ id == ID_MT7988) ? \ ++ MT7531_MIRROR_EN : MT7530_MIRROR_EN) ++ ++#define MT753X_MIRROR_PORT_MASK(id) ((id == ID_MT7531 || \ ++ id == ID_MT7988) ? \ ++ MT7531_MIRROR_PORT_MASK : \ ++ MT7530_MIRROR_PORT_MASK) ++ ++#define MT753X_MIRROR_PORT_GET(id, val) ((id == ID_MT7531 || \ ++ id == ID_MT7988) ? \ ++ MT7531_MIRROR_PORT_GET(val) : \ ++ MT7530_MIRROR_PORT_GET(val)) ++ ++#define MT753X_MIRROR_PORT_SET(id, val) ((id == ID_MT7531 || \ ++ id == ID_MT7988) ? \ ++ MT7531_MIRROR_PORT_SET(val) : \ ++ MT7530_MIRROR_PORT_SET(val)) + + /* Register for BPDU and PAE frame control */ + #define MT753X_BPC 0x24 diff --git a/target/linux/generic/backport-6.6/790-43-v6.10-net-dsa-mt7530-refactor-MT7530_HWTRAP-and-MT7530_MHW.patch b/target/linux/generic/backport-6.6/790-43-v6.10-net-dsa-mt7530-refactor-MT7530_HWTRAP-and-MT7530_MHW.patch new file mode 100644 index 0000000000..1f66575f02 --- /dev/null +++ b/target/linux/generic/backport-6.6/790-43-v6.10-net-dsa-mt7530-refactor-MT7530_HWTRAP-and-MT7530_MHW.patch @@ -0,0 +1,257 @@ +From 3ccf67597d35c06a7319e407b1c42f78a7966779 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= +Date: Mon, 22 Apr 2024 10:15:13 +0300 +Subject: [PATCH 06/15] net: dsa: mt7530: refactor MT7530_HWTRAP and + MT7530_MHWTRAP +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +The MT7530_HWTRAP and MT7530_MHWTRAP registers are on MT7530 and MT7531. +It's called hardware trap on MT7530, software trap on MT7531. That's +because some bits of the trap on MT7530 cannot be modified by software +whilst all bits of the trap on MT7531 can. Rename the definitions for them +to MT753X_TRAP and MT753X_MTRAP. Add MT7530 and MT7531 prefixes to the +definitions specific to the switch model. + +Remove the extra parentheses from MT7530_XTAL_40MHZ and MT7530_XTAL_20MHZ. + +Rename MHWTRAP_PHY0_SEL, MHWTRAP_MANUAL, and MHWTRAP_PHY_ACCESS to be on +par with the "MT7621 Giga Switch Programming Guide v0.3" document. + +Make an enumaration for the XTAL frequency. Set the data type of the xtal +variable on mt7531_pll_setup() to it. + +Signed-off-by: Arınç ÜNAL +--- + drivers/net/dsa/mt7530.c | 59 ++++++++++++++++++++-------------------- + drivers/net/dsa/mt7530.h | 50 ++++++++++++++++------------------ + 2 files changed, 54 insertions(+), 55 deletions(-) + +--- a/drivers/net/dsa/mt7530.c ++++ b/drivers/net/dsa/mt7530.c +@@ -417,23 +417,23 @@ mt7530_setup_port6(struct dsa_switch *ds + + mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK, P6_INTF_MODE(1)); + +- xtal = mt7530_read(priv, MT7530_MHWTRAP) & HWTRAP_XTAL_MASK; ++ xtal = mt7530_read(priv, MT753X_MTRAP) & MT7530_XTAL_MASK; + +- if (xtal == HWTRAP_XTAL_25MHZ) ++ if (xtal == MT7530_XTAL_25MHZ) + ssc_delta = 0x57; + else + ssc_delta = 0x87; + + if (priv->id == ID_MT7621) { + /* PLL frequency: 125MHz: 1.0GBit */ +- if (xtal == HWTRAP_XTAL_40MHZ) ++ if (xtal == MT7530_XTAL_40MHZ) + ncpo1 = 0x0640; +- if (xtal == HWTRAP_XTAL_25MHZ) ++ if (xtal == MT7530_XTAL_25MHZ) + ncpo1 = 0x0a00; + } else { /* PLL frequency: 250MHz: 2.0Gbit */ +- if (xtal == HWTRAP_XTAL_40MHZ) ++ if (xtal == MT7530_XTAL_40MHZ) + ncpo1 = 0x0c80; +- if (xtal == HWTRAP_XTAL_25MHZ) ++ if (xtal == MT7530_XTAL_25MHZ) + ncpo1 = 0x1400; + } + +@@ -456,19 +456,20 @@ mt7530_setup_port6(struct dsa_switch *ds + static void + mt7531_pll_setup(struct mt7530_priv *priv) + { ++ enum mt7531_xtal_fsel xtal; + u32 top_sig; + u32 hwstrap; +- u32 xtal; + u32 val; + + val = mt7530_read(priv, MT7531_CREV); + top_sig = mt7530_read(priv, MT7531_TOP_SIG_SR); +- hwstrap = mt7530_read(priv, MT7531_HWTRAP); ++ hwstrap = mt7530_read(priv, MT753X_TRAP); + if ((val & CHIP_REV_M) > 0) +- xtal = (top_sig & PAD_MCM_SMI_EN) ? HWTRAP_XTAL_FSEL_40MHZ : +- HWTRAP_XTAL_FSEL_25MHZ; ++ xtal = (top_sig & PAD_MCM_SMI_EN) ? MT7531_XTAL_FSEL_40MHZ : ++ MT7531_XTAL_FSEL_25MHZ; + else +- xtal = hwstrap & HWTRAP_XTAL_FSEL_MASK; ++ xtal = (hwstrap & MT7531_XTAL25) ? MT7531_XTAL_FSEL_25MHZ : ++ MT7531_XTAL_FSEL_40MHZ; + + /* Step 1 : Disable MT7531 COREPLL */ + val = mt7530_read(priv, MT7531_PLLGP_EN); +@@ -497,13 +498,13 @@ mt7531_pll_setup(struct mt7530_priv *pri + usleep_range(25, 35); + + switch (xtal) { +- case HWTRAP_XTAL_FSEL_25MHZ: ++ case MT7531_XTAL_FSEL_25MHZ: + val = mt7530_read(priv, MT7531_PLLGP_CR0); + val &= ~RG_COREPLL_SDM_PCW_M; + val |= 0x140000 << RG_COREPLL_SDM_PCW_S; + mt7530_write(priv, MT7531_PLLGP_CR0, val); + break; +- case HWTRAP_XTAL_FSEL_40MHZ: ++ case MT7531_XTAL_FSEL_40MHZ: + val = mt7530_read(priv, MT7531_PLLGP_CR0); + val &= ~RG_COREPLL_SDM_PCW_M; + val |= 0x190000 << RG_COREPLL_SDM_PCW_S; +@@ -877,20 +878,20 @@ static void mt7530_setup_port5(struct ds + + mutex_lock(&priv->reg_mutex); + +- val = mt7530_read(priv, MT7530_MHWTRAP); ++ val = mt7530_read(priv, MT753X_MTRAP); + +- val |= MHWTRAP_MANUAL | MHWTRAP_P5_MAC_SEL | MHWTRAP_P5_DIS; +- val &= ~MHWTRAP_P5_RGMII_MODE & ~MHWTRAP_PHY0_SEL; ++ val |= MT7530_CHG_TRAP | MT7530_P5_MAC_SEL | MT7530_P5_DIS; ++ val &= ~MT7530_P5_RGMII_MODE & ~MT7530_P5_PHY0_SEL; + + switch (priv->p5_mode) { + /* MUX_PHY_P0: P0 -> P5 -> SoC MAC */ + case MUX_PHY_P0: +- val |= MHWTRAP_PHY0_SEL; ++ val |= MT7530_P5_PHY0_SEL; + fallthrough; + + /* MUX_PHY_P4: P4 -> P5 -> SoC MAC */ + case MUX_PHY_P4: +- val &= ~MHWTRAP_P5_MAC_SEL & ~MHWTRAP_P5_DIS; ++ val &= ~MT7530_P5_MAC_SEL & ~MT7530_P5_DIS; + + /* Setup the MAC by default for the cpu port */ + mt7530_write(priv, MT753X_PMCR_P(5), 0x56300); +@@ -898,13 +899,13 @@ static void mt7530_setup_port5(struct ds + + /* GMAC5: P5 -> SoC MAC or external PHY */ + default: +- val &= ~MHWTRAP_P5_DIS; ++ val &= ~MT7530_P5_DIS; + break; + } + + /* Setup RGMII settings */ + if (phy_interface_mode_is_rgmii(interface)) { +- val |= MHWTRAP_P5_RGMII_MODE; ++ val |= MT7530_P5_RGMII_MODE; + + /* P5 RGMII RX Clock Control: delay setting for 1000M */ + mt7530_write(priv, MT7530_P5RGMIIRXCR, CSR_RGMII_EDGE_ALIGN); +@@ -924,7 +925,7 @@ static void mt7530_setup_port5(struct ds + P5_IO_CLK_DRV(1) | P5_IO_DATA_DRV(1)); + } + +- mt7530_write(priv, MT7530_MHWTRAP, val); ++ mt7530_write(priv, MT753X_MTRAP, val); + + dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, mode=%s, phy-mode=%s\n", val, + mt7530_p5_mode_str(priv->p5_mode), phy_modes(interface)); +@@ -2365,7 +2366,7 @@ mt7530_setup(struct dsa_switch *ds) + } + + /* Waiting for MT7530 got to stable */ +- INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP); ++ INIT_MT7530_DUMMY_POLL(&p, priv, MT753X_TRAP); + ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0, + 20, 1000000); + if (ret < 0) { +@@ -2380,7 +2381,7 @@ mt7530_setup(struct dsa_switch *ds) + return -ENODEV; + } + +- if ((val & HWTRAP_XTAL_MASK) == HWTRAP_XTAL_20MHZ) { ++ if ((val & MT7530_XTAL_MASK) == MT7530_XTAL_20MHZ) { + dev_err(priv->dev, + "MT7530 with a 20MHz XTAL is not supported!\n"); + return -EINVAL; +@@ -2401,12 +2402,12 @@ mt7530_setup(struct dsa_switch *ds) + RD_TAP_MASK, RD_TAP(16)); + + /* Enable port 6 */ +- val = mt7530_read(priv, MT7530_MHWTRAP); +- val &= ~MHWTRAP_P6_DIS & ~MHWTRAP_PHY_ACCESS; +- val |= MHWTRAP_MANUAL; +- mt7530_write(priv, MT7530_MHWTRAP, val); ++ val = mt7530_read(priv, MT753X_MTRAP); ++ val &= ~MT7530_P6_DIS & ~MT7530_PHY_INDIRECT_ACCESS; ++ val |= MT7530_CHG_TRAP; ++ mt7530_write(priv, MT753X_MTRAP, val); + +- if ((val & HWTRAP_XTAL_MASK) == HWTRAP_XTAL_40MHZ) ++ if ((val & MT7530_XTAL_MASK) == MT7530_XTAL_40MHZ) + mt7530_pll_setup(priv); + + mt753x_trap_frames(priv); +@@ -2586,7 +2587,7 @@ mt7531_setup(struct dsa_switch *ds) + } + + /* Waiting for MT7530 got to stable */ +- INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP); ++ INIT_MT7530_DUMMY_POLL(&p, priv, MT753X_TRAP); + ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0, + 20, 1000000); + if (ret < 0) { +--- a/drivers/net/dsa/mt7530.h ++++ b/drivers/net/dsa/mt7530.h +@@ -495,32 +495,30 @@ enum mt7531_clk_skew { + MT7531_CLK_SKEW_REVERSE = 3, + }; + +-/* Register for hw trap status */ +-#define MT7530_HWTRAP 0x7800 +-#define HWTRAP_XTAL_MASK (BIT(10) | BIT(9)) +-#define HWTRAP_XTAL_25MHZ (BIT(10) | BIT(9)) +-#define HWTRAP_XTAL_40MHZ (BIT(10)) +-#define HWTRAP_XTAL_20MHZ (BIT(9)) ++/* Register for trap status */ ++#define MT753X_TRAP 0x7800 ++#define MT7530_XTAL_MASK (BIT(10) | BIT(9)) ++#define MT7530_XTAL_25MHZ (BIT(10) | BIT(9)) ++#define MT7530_XTAL_40MHZ BIT(10) ++#define MT7530_XTAL_20MHZ BIT(9) ++#define MT7531_XTAL25 BIT(7) + +-#define MT7531_HWTRAP 0x7800 +-#define HWTRAP_XTAL_FSEL_MASK BIT(7) +-#define HWTRAP_XTAL_FSEL_25MHZ BIT(7) +-#define HWTRAP_XTAL_FSEL_40MHZ 0 +-/* Unique fields of (M)HWSTRAP for MT7531 */ +-#define XTAL_FSEL_S 7 +-#define XTAL_FSEL_M BIT(7) +-#define PHY_EN BIT(6) +-#define CHG_STRAP BIT(8) ++/* Register for trap modification */ ++#define MT753X_MTRAP 0x7804 ++#define MT7530_P5_PHY0_SEL BIT(20) ++#define MT7530_CHG_TRAP BIT(16) ++#define MT7530_P5_MAC_SEL BIT(13) ++#define MT7530_P6_DIS BIT(8) ++#define MT7530_P5_RGMII_MODE BIT(7) ++#define MT7530_P5_DIS BIT(6) ++#define MT7530_PHY_INDIRECT_ACCESS BIT(5) ++#define MT7531_CHG_STRAP BIT(8) ++#define MT7531_PHY_EN BIT(6) + +-/* Register for hw trap modification */ +-#define MT7530_MHWTRAP 0x7804 +-#define MHWTRAP_PHY0_SEL BIT(20) +-#define MHWTRAP_MANUAL BIT(16) +-#define MHWTRAP_P5_MAC_SEL BIT(13) +-#define MHWTRAP_P6_DIS BIT(8) +-#define MHWTRAP_P5_RGMII_MODE BIT(7) +-#define MHWTRAP_P5_DIS BIT(6) +-#define MHWTRAP_PHY_ACCESS BIT(5) ++enum mt7531_xtal_fsel { ++ MT7531_XTAL_FSEL_25MHZ, ++ MT7531_XTAL_FSEL_40MHZ, ++}; + + /* Register for TOP signal control */ + #define MT7530_TOP_SIG_CTRL 0x7808 diff --git a/target/linux/generic/backport-6.6/790-44-v6.10-net-dsa-mt7530-move-MT753X_MTRAP-operations-for-MT75.patch b/target/linux/generic/backport-6.6/790-44-v6.10-net-dsa-mt7530-move-MT753X_MTRAP-operations-for-MT75.patch new file mode 100644 index 0000000000..f7802c02db --- /dev/null +++ b/target/linux/generic/backport-6.6/790-44-v6.10-net-dsa-mt7530-move-MT753X_MTRAP-operations-for-MT75.patch @@ -0,0 +1,117 @@ +From 2982f395c9a513b168f1e685588f70013cba2f5f Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= +Date: Mon, 22 Apr 2024 10:15:14 +0300 +Subject: [PATCH 07/15] net: dsa: mt7530: move MT753X_MTRAP operations for + MT7530 +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +On MT7530, the media-independent interfaces of port 5 and 6 are controlled +by the MT7530_P5_DIS and MT7530_P6_DIS bits of the hardware trap. Deal with +these bits only when the relevant port is being enabled or disabled. This +ensures that these ports will be disabled when they are not in use. + +Do not set MT7530_CHG_TRAP on mt7530_setup_port5() as that's already being +done on mt7530_setup(). + +Instead of globally setting MT7530_P5_MAC_SEL, clear it, then set it only +on the appropriate case. + +If PHY muxing is detected, clear MT7530_P5_DIS before calling +mt7530_setup_port5(). + +Signed-off-by: Arınç ÜNAL +--- + drivers/net/dsa/mt7530.c | 38 +++++++++++++++++++++++++++----------- + 1 file changed, 27 insertions(+), 11 deletions(-) + +--- a/drivers/net/dsa/mt7530.c ++++ b/drivers/net/dsa/mt7530.c +@@ -880,8 +880,7 @@ static void mt7530_setup_port5(struct ds + + val = mt7530_read(priv, MT753X_MTRAP); + +- val |= MT7530_CHG_TRAP | MT7530_P5_MAC_SEL | MT7530_P5_DIS; +- val &= ~MT7530_P5_RGMII_MODE & ~MT7530_P5_PHY0_SEL; ++ val &= ~MT7530_P5_PHY0_SEL & ~MT7530_P5_MAC_SEL & ~MT7530_P5_RGMII_MODE; + + switch (priv->p5_mode) { + /* MUX_PHY_P0: P0 -> P5 -> SoC MAC */ +@@ -891,15 +890,13 @@ static void mt7530_setup_port5(struct ds + + /* MUX_PHY_P4: P4 -> P5 -> SoC MAC */ + case MUX_PHY_P4: +- val &= ~MT7530_P5_MAC_SEL & ~MT7530_P5_DIS; +- + /* Setup the MAC by default for the cpu port */ + mt7530_write(priv, MT753X_PMCR_P(5), 0x56300); + break; + + /* GMAC5: P5 -> SoC MAC or external PHY */ + default: +- val &= ~MT7530_P5_DIS; ++ val |= MT7530_P5_MAC_SEL; + break; + } + +@@ -1193,6 +1190,14 @@ mt7530_port_enable(struct dsa_switch *ds + + mutex_unlock(&priv->reg_mutex); + ++ if (priv->id != ID_MT7530 && priv->id != ID_MT7621) ++ return 0; ++ ++ if (port == 5) ++ mt7530_clear(priv, MT753X_MTRAP, MT7530_P5_DIS); ++ else if (port == 6) ++ mt7530_clear(priv, MT753X_MTRAP, MT7530_P6_DIS); ++ + return 0; + } + +@@ -1211,6 +1216,14 @@ mt7530_port_disable(struct dsa_switch *d + PCR_MATRIX_CLR); + + mutex_unlock(&priv->reg_mutex); ++ ++ if (priv->id != ID_MT7530 && priv->id != ID_MT7621) ++ return; ++ ++ if (port == 5) ++ mt7530_set(priv, MT753X_MTRAP, MT7530_P5_DIS); ++ else if (port == 6) ++ mt7530_set(priv, MT753X_MTRAP, MT7530_P6_DIS); + } + + static int +@@ -2401,11 +2414,11 @@ mt7530_setup(struct dsa_switch *ds) + mt7530_rmw(priv, MT7530_TRGMII_RD(i), + RD_TAP_MASK, RD_TAP(16)); + +- /* Enable port 6 */ +- val = mt7530_read(priv, MT753X_MTRAP); +- val &= ~MT7530_P6_DIS & ~MT7530_PHY_INDIRECT_ACCESS; +- val |= MT7530_CHG_TRAP; +- mt7530_write(priv, MT753X_MTRAP, val); ++ /* Allow modifying the trap and directly access PHY registers via the ++ * MDIO bus the switch is on. ++ */ ++ mt7530_rmw(priv, MT753X_MTRAP, MT7530_CHG_TRAP | ++ MT7530_PHY_INDIRECT_ACCESS, MT7530_CHG_TRAP); + + if ((val & MT7530_XTAL_MASK) == MT7530_XTAL_40MHZ) + mt7530_pll_setup(priv); +@@ -2488,8 +2501,11 @@ mt7530_setup(struct dsa_switch *ds) + break; + } + +- if (priv->p5_mode == MUX_PHY_P0 || priv->p5_mode == MUX_PHY_P4) ++ if (priv->p5_mode == MUX_PHY_P0 || ++ priv->p5_mode == MUX_PHY_P4) { ++ mt7530_clear(priv, MT753X_MTRAP, MT7530_P5_DIS); + mt7530_setup_port5(ds, interface); ++ } + } + + #ifdef CONFIG_GPIOLIB diff --git a/target/linux/generic/backport-6.6/790-45-v6.10-net-dsa-mt7530-return-mt7530_setup_mdio-mt7531_setup.patch b/target/linux/generic/backport-6.6/790-45-v6.10-net-dsa-mt7530-return-mt7530_setup_mdio-mt7531_setup.patch new file mode 100644 index 0000000000..2eaa77c8cf --- /dev/null +++ b/target/linux/generic/backport-6.6/790-45-v6.10-net-dsa-mt7530-return-mt7530_setup_mdio-mt7531_setup.patch @@ -0,0 +1,39 @@ +From 1f5669efca65564c7533704917f79003c6b36c9c Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= +Date: Mon, 22 Apr 2024 10:15:15 +0300 +Subject: [PATCH 08/15] net: dsa: mt7530: return mt7530_setup_mdio & + mt7531_setup_common on error +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +The mt7530_setup_mdio() and mt7531_setup_common() functions should be +checked for errors. Return if the functions return a non-zero value. + +Signed-off-by: Arınç ÜNAL +--- + drivers/net/dsa/mt7530.c | 6 +++++- + 1 file changed, 5 insertions(+), 1 deletion(-) + +--- a/drivers/net/dsa/mt7530.c ++++ b/drivers/net/dsa/mt7530.c +@@ -2667,7 +2667,9 @@ mt7531_setup(struct dsa_switch *ds) + 0); + } + +- mt7531_setup_common(ds); ++ ret = mt7531_setup_common(ds); ++ if (ret) ++ return ret; + + /* Setup VLAN ID 0 for VLAN-unaware bridges */ + ret = mt7530_setup_vlan0(priv); +@@ -3020,6 +3022,8 @@ mt753x_setup(struct dsa_switch *ds) + ret = mt7530_setup_mdio(priv); + if (ret && priv->irq) + mt7530_free_irq_common(priv); ++ if (ret) ++ return ret; + + /* Initialise the PCS devices */ + for (i = 0; i < priv->ds->num_ports; i++) { diff --git a/target/linux/generic/backport-6.6/790-46-v6.10-net-dsa-mt7530-define-MAC-speed-capabilities-per-swi.patch b/target/linux/generic/backport-6.6/790-46-v6.10-net-dsa-mt7530-define-MAC-speed-capabilities-per-swi.patch new file mode 100644 index 0000000000..9a592c759d --- /dev/null +++ b/target/linux/generic/backport-6.6/790-46-v6.10-net-dsa-mt7530-define-MAC-speed-capabilities-per-swi.patch @@ -0,0 +1,75 @@ +From 6cc2d4ccd77509df74b7b8ef46bbc6ba0a571318 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= +Date: Mon, 22 Apr 2024 10:15:16 +0300 +Subject: [PATCH 09/15] net: dsa: mt7530: define MAC speed capabilities per + switch model +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +With the support of the MT7988 SoC switch, the MAC speed capabilities +defined on mt753x_phylink_get_caps() won't apply to all switch models +anymore. Move them to more appropriate locations instead of overwriting +config->mac_capabilities. + +Remove the comment on mt753x_phylink_get_caps() as it's become invalid with +the support of MT7531 and MT7988 SoC switch. + +Add break to case 6 of mt7988_mac_port_get_caps() to be explicit. + +Signed-off-by: Arınç ÜNAL +--- + drivers/net/dsa/mt7530.c | 15 ++++++++++----- + 1 file changed, 10 insertions(+), 5 deletions(-) + +--- a/drivers/net/dsa/mt7530.c ++++ b/drivers/net/dsa/mt7530.c +@@ -2685,6 +2685,8 @@ mt7531_setup(struct dsa_switch *ds) + static void mt7530_mac_port_get_caps(struct dsa_switch *ds, int port, + struct phylink_config *config) + { ++ config->mac_capabilities |= MAC_10 | MAC_100 | MAC_1000FD; ++ + switch (port) { + /* Ports which are connected to switch PHYs. There is no MII pinout. */ + case 0 ... 4: +@@ -2716,6 +2718,8 @@ static void mt7531_mac_port_get_caps(str + { + struct mt7530_priv *priv = ds->priv; + ++ config->mac_capabilities |= MAC_10 | MAC_100 | MAC_1000FD; ++ + switch (port) { + /* Ports which are connected to switch PHYs. There is no MII pinout. */ + case 0 ... 4: +@@ -2755,14 +2759,17 @@ static void mt7988_mac_port_get_caps(str + case 0 ... 3: + __set_bit(PHY_INTERFACE_MODE_INTERNAL, + config->supported_interfaces); ++ ++ config->mac_capabilities |= MAC_10 | MAC_100 | MAC_1000FD; + break; + + /* Port 6 is connected to SoC's XGMII MAC. There is no MII pinout. */ + case 6: + __set_bit(PHY_INTERFACE_MODE_INTERNAL, + config->supported_interfaces); +- config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | +- MAC_10000FD; ++ ++ config->mac_capabilities |= MAC_10000FD; ++ break; + } + } + +@@ -2932,9 +2939,7 @@ static void mt753x_phylink_get_caps(stru + { + struct mt7530_priv *priv = ds->priv; + +- /* This switch only supports full-duplex at 1Gbps */ +- config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | +- MAC_10 | MAC_100 | MAC_1000FD; ++ config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE; + + priv->info->mac_port_get_caps(ds, port, config); + } diff --git a/target/linux/generic/backport-6.6/790-47-v6.10-net-dsa-mt7530-get-rid-of-function-sanity-check.patch b/target/linux/generic/backport-6.6/790-47-v6.10-net-dsa-mt7530-get-rid-of-function-sanity-check.patch new file mode 100644 index 0000000000..bc84ecb778 --- /dev/null +++ b/target/linux/generic/backport-6.6/790-47-v6.10-net-dsa-mt7530-get-rid-of-function-sanity-check.patch @@ -0,0 +1,33 @@ +From dd0f15fc877c10567699190bce0f55e96f4ad6b5 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= +Date: Mon, 22 Apr 2024 10:15:17 +0300 +Subject: [PATCH 10/15] net: dsa: mt7530: get rid of function sanity check +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Get rid of checking whether functions are filled properly. priv->info which +is an mt753x_info structure is filled and checked for before this check. +It's unnecessary checking whether it's filled properly. + +Signed-off-by: Arınç ÜNAL +--- + drivers/net/dsa/mt7530.c | 7 ------- + 1 file changed, 7 deletions(-) + +--- a/drivers/net/dsa/mt7530.c ++++ b/drivers/net/dsa/mt7530.c +@@ -3232,13 +3232,6 @@ mt7530_probe_common(struct mt7530_priv * + if (!priv->info) + return -EINVAL; + +- /* Sanity check if these required device operations are filled +- * properly. +- */ +- if (!priv->info->sw_setup || !priv->info->phy_read_c22 || +- !priv->info->phy_write_c22 || !priv->info->mac_port_get_caps) +- return -EINVAL; +- + priv->id = priv->info->id; + priv->dev = dev; + priv->ds->priv = priv; diff --git a/target/linux/generic/backport-6.6/790-48-v6.10-net-dsa-mt7530-refactor-MT7530_PMEEECR_P.patch b/target/linux/generic/backport-6.6/790-48-v6.10-net-dsa-mt7530-refactor-MT7530_PMEEECR_P.patch new file mode 100644 index 0000000000..e75db9ba30 --- /dev/null +++ b/target/linux/generic/backport-6.6/790-48-v6.10-net-dsa-mt7530-refactor-MT7530_PMEEECR_P.patch @@ -0,0 +1,71 @@ +From 2dff9759602b069f97ccc939e15a47ca051b2983 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= +Date: Mon, 22 Apr 2024 10:15:18 +0300 +Subject: [PATCH 11/15] net: dsa: mt7530: refactor MT7530_PMEEECR_P() +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +The MT7530_PMEEECR_P() register is on MT7530, MT7531, and the switch on the +MT7988 SoC. Rename the definition for them to MT753X_PMEEECR_P(). Use the +FIELD_PREP and FIELD_GET macros. Rename GET_LPI_THRESH() and +SET_LPI_THRESH() to LPI_THRESH_GET() and LPI_THRESH_SET(). + +Signed-off-by: Arınç ÜNAL +--- + drivers/net/dsa/mt7530.c | 8 ++++---- + drivers/net/dsa/mt7530.h | 13 +++++++------ + 2 files changed, 11 insertions(+), 10 deletions(-) + +--- a/drivers/net/dsa/mt7530.c ++++ b/drivers/net/dsa/mt7530.c +@@ -3051,10 +3051,10 @@ static int mt753x_get_mac_eee(struct dsa + struct ethtool_eee *e) + { + struct mt7530_priv *priv = ds->priv; +- u32 eeecr = mt7530_read(priv, MT7530_PMEEECR_P(port)); ++ u32 eeecr = mt7530_read(priv, MT753X_PMEEECR_P(port)); + + e->tx_lpi_enabled = !(eeecr & LPI_MODE_EN); +- e->tx_lpi_timer = GET_LPI_THRESH(eeecr); ++ e->tx_lpi_timer = LPI_THRESH_GET(eeecr); + + return 0; + } +@@ -3068,11 +3068,11 @@ static int mt753x_set_mac_eee(struct dsa + if (e->tx_lpi_timer > 0xFFF) + return -EINVAL; + +- set = SET_LPI_THRESH(e->tx_lpi_timer); ++ set = LPI_THRESH_SET(e->tx_lpi_timer); + if (!e->tx_lpi_enabled) + /* Force LPI Mode without a delay */ + set |= LPI_MODE_EN; +- mt7530_rmw(priv, MT7530_PMEEECR_P(port), mask, set); ++ mt7530_rmw(priv, MT753X_PMEEECR_P(port), mask, set); + + return 0; + } +--- a/drivers/net/dsa/mt7530.h ++++ b/drivers/net/dsa/mt7530.h +@@ -364,13 +364,14 @@ enum mt7530_vlan_port_acc_frm { + PMCR_FORCE_SPEED_100 | \ + PMCR_FORCE_FDX | PMCR_FORCE_LNK) + +-#define MT7530_PMEEECR_P(x) (0x3004 + (x) * 0x100) +-#define WAKEUP_TIME_1000(x) (((x) & 0xFF) << 24) +-#define WAKEUP_TIME_100(x) (((x) & 0xFF) << 16) ++#define MT753X_PMEEECR_P(x) (0x3004 + (x) * 0x100) ++#define WAKEUP_TIME_1000_MASK GENMASK(31, 24) ++#define WAKEUP_TIME_1000(x) FIELD_PREP(WAKEUP_TIME_1000_MASK, x) ++#define WAKEUP_TIME_100_MASK GENMASK(23, 16) ++#define WAKEUP_TIME_100(x) FIELD_PREP(WAKEUP_TIME_100_MASK, x) + #define LPI_THRESH_MASK GENMASK(15, 4) +-#define LPI_THRESH_SHT 4 +-#define SET_LPI_THRESH(x) (((x) << LPI_THRESH_SHT) & LPI_THRESH_MASK) +-#define GET_LPI_THRESH(x) (((x) & LPI_THRESH_MASK) >> LPI_THRESH_SHT) ++#define LPI_THRESH_GET(x) FIELD_GET(LPI_THRESH_MASK, x) ++#define LPI_THRESH_SET(x) FIELD_PREP(LPI_THRESH_MASK, x) + #define LPI_MODE_EN BIT(0) + + #define MT7530_PMSR_P(x) (0x3008 + (x) * 0x100) diff --git a/target/linux/generic/backport-6.6/790-49-v6.10-net-dsa-mt7530-get-rid-of-mac_port_validate-member-o.patch b/target/linux/generic/backport-6.6/790-49-v6.10-net-dsa-mt7530-get-rid-of-mac_port_validate-member-o.patch new file mode 100644 index 0000000000..d083708548 --- /dev/null +++ b/target/linux/generic/backport-6.6/790-49-v6.10-net-dsa-mt7530-get-rid-of-mac_port_validate-member-o.patch @@ -0,0 +1,48 @@ +From 21d67c2fabfe40baf33202d3287b67b6c16f8382 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= +Date: Mon, 22 Apr 2024 10:15:19 +0300 +Subject: [PATCH 12/15] net: dsa: mt7530: get rid of mac_port_validate member + of mt753x_info +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +The mac_port_validate member of the mt753x_info structure is not being +used, remove it. Improve the member description section in the process. + +Signed-off-by: Arınç ÜNAL +--- + drivers/net/dsa/mt7530.h | 10 +++------- + 1 file changed, 3 insertions(+), 7 deletions(-) + +--- a/drivers/net/dsa/mt7530.h ++++ b/drivers/net/dsa/mt7530.h +@@ -743,15 +743,14 @@ struct mt753x_pcs { + + /* struct mt753x_info - This is the main data structure for holding the specific + * part for each supported device ++ * @id: Holding the identifier to a switch model ++ * @pcs_ops: Holding the pointer to the MAC PCS operations structure + * @sw_setup: Holding the handler to a device initialization + * @phy_read_c22: Holding the way reading PHY port using C22 + * @phy_write_c22: Holding the way writing PHY port using C22 + * @phy_read_c45: Holding the way reading PHY port using C45 + * @phy_write_c45: Holding the way writing PHY port using C45 +- * @phy_mode_supported: Check if the PHY type is being supported on a certain +- * port +- * @mac_port_validate: Holding the way to set addition validate type for a +- * certan MAC port ++ * @mac_port_get_caps: Holding the handler that provides MAC capabilities + * @mac_port_config: Holding the way setting up the PHY attribute to a + * certain MAC port + */ +@@ -770,9 +769,6 @@ struct mt753x_info { + int regnum, u16 val); + void (*mac_port_get_caps)(struct dsa_switch *ds, int port, + struct phylink_config *config); +- void (*mac_port_validate)(struct dsa_switch *ds, int port, +- phy_interface_t interface, +- unsigned long *supported); + void (*mac_port_config)(struct dsa_switch *ds, int port, + unsigned int mode, + phy_interface_t interface); diff --git a/target/linux/generic/backport-6.6/790-50-v6.10-net-dsa-mt7530-use-priv-ds-num_ports-instead-of-MT75.patch b/target/linux/generic/backport-6.6/790-50-v6.10-net-dsa-mt7530-use-priv-ds-num_ports-instead-of-MT75.patch new file mode 100644 index 0000000000..f63d4d7705 --- /dev/null +++ b/target/linux/generic/backport-6.6/790-50-v6.10-net-dsa-mt7530-use-priv-ds-num_ports-instead-of-MT75.patch @@ -0,0 +1,57 @@ +From 6efc8ae3eb0363328f479191a0cf0dc12a16e090 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= +Date: Mon, 22 Apr 2024 10:15:20 +0300 +Subject: [PATCH 13/15] net: dsa: mt7530: use priv->ds->num_ports instead of + MT7530_NUM_PORTS +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Use priv->ds->num_ports on all for loops which configure the switch +registers. In the future, the value of MT7530_NUM_PORTS will depend on +priv->id. Therefore, this change prepares the subdriver for a simpler +implementation. + +Signed-off-by: Arınç ÜNAL +--- + drivers/net/dsa/mt7530.c | 8 ++++---- + 1 file changed, 4 insertions(+), 4 deletions(-) + +--- a/drivers/net/dsa/mt7530.c ++++ b/drivers/net/dsa/mt7530.c +@@ -1411,7 +1411,7 @@ mt7530_port_set_vlan_unaware(struct dsa_ + mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, + G0_PORT_VID_DEF); + +- for (i = 0; i < MT7530_NUM_PORTS; i++) { ++ for (i = 0; i < priv->ds->num_ports; i++) { + if (dsa_is_user_port(ds, i) && + dsa_port_is_vlan_filtering(dsa_to_port(ds, i))) { + all_user_ports_removed = false; +@@ -2428,7 +2428,7 @@ mt7530_setup(struct dsa_switch *ds) + /* Enable and reset MIB counters */ + mt7530_mib_reset(ds); + +- for (i = 0; i < MT7530_NUM_PORTS; i++) { ++ for (i = 0; i < priv->ds->num_ports; i++) { + /* Clear link settings and enable force mode to force link down + * on all ports until they're enabled later. + */ +@@ -2539,7 +2539,7 @@ mt7531_setup_common(struct dsa_switch *d + mt7530_clear(priv, MT753X_MFC, BC_FFP_MASK | UNM_FFP_MASK | + UNU_FFP_MASK); + +- for (i = 0; i < MT7530_NUM_PORTS; i++) { ++ for (i = 0; i < priv->ds->num_ports; i++) { + /* Clear link settings and enable force mode to force link down + * on all ports until they're enabled later. + */ +@@ -2626,7 +2626,7 @@ mt7531_setup(struct dsa_switch *ds) + priv->p5_sgmii = !!(val & PAD_DUAL_SGMII_EN); + + /* Force link down on all ports before internal reset */ +- for (i = 0; i < MT7530_NUM_PORTS; i++) ++ for (i = 0; i < priv->ds->num_ports; i++) + mt7530_write(priv, MT753X_PMCR_P(i), MT7531_FORCE_MODE_LNK); + + /* Reset the switch through internal reset */ diff --git a/target/linux/generic/backport-6.6/790-51-v6.10-net-dsa-mt7530-do-not-pass-port-variable-to-mt7531_r.patch b/target/linux/generic/backport-6.6/790-51-v6.10-net-dsa-mt7530-do-not-pass-port-variable-to-mt7531_r.patch new file mode 100644 index 0000000000..9ba12b1269 --- /dev/null +++ b/target/linux/generic/backport-6.6/790-51-v6.10-net-dsa-mt7530-do-not-pass-port-variable-to-mt7531_r.patch @@ -0,0 +1,37 @@ +From c078ebbf5f6f6d8390035a9f92eeab766b78884d Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= +Date: Mon, 22 Apr 2024 10:15:21 +0300 +Subject: [PATCH 14/15] net: dsa: mt7530: do not pass port variable to + mt7531_rgmii_setup() +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +The mt7531_rgmii_setup() function does not use the port variable, do not +pass the variable to it. + +Signed-off-by: Arınç ÜNAL +--- + drivers/net/dsa/mt7530.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/drivers/net/dsa/mt7530.c ++++ b/drivers/net/dsa/mt7530.c +@@ -2785,7 +2785,7 @@ mt7530_mac_config(struct dsa_switch *ds, + mt7530_setup_port6(priv->ds, interface); + } + +-static void mt7531_rgmii_setup(struct mt7530_priv *priv, u32 port, ++static void mt7531_rgmii_setup(struct mt7530_priv *priv, + phy_interface_t interface, + struct phy_device *phydev) + { +@@ -2836,7 +2836,7 @@ mt7531_mac_config(struct dsa_switch *ds, + if (phy_interface_mode_is_rgmii(interface)) { + dp = dsa_to_port(ds, port); + phydev = dp->slave->phydev; +- mt7531_rgmii_setup(priv, port, interface, phydev); ++ mt7531_rgmii_setup(priv, interface, phydev); + } + } + diff --git a/target/linux/generic/backport-6.6/790-52-v6.10-net-dsa-mt7530-explain-exposing-MDIO-bus-of-MT7531AE.patch b/target/linux/generic/backport-6.6/790-52-v6.10-net-dsa-mt7530-explain-exposing-MDIO-bus-of-MT7531AE.patch new file mode 100644 index 0000000000..58c3e0bc3c --- /dev/null +++ b/target/linux/generic/backport-6.6/790-52-v6.10-net-dsa-mt7530-explain-exposing-MDIO-bus-of-MT7531AE.patch @@ -0,0 +1,33 @@ +From e7a9cc3cc00b40e0bc2bae40bd2ece0e48fa51d5 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= +Date: Mon, 22 Apr 2024 10:15:22 +0300 +Subject: [PATCH 15/15] net: dsa: mt7530: explain exposing MDIO bus of MT7531AE + better +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Unlike MT7531BE, the GPIO 6-12 pins are not used for RGMII on MT7531AE. +Therefore, the GPIO 11-12 pins are set to function as MDC and MDIO to +expose the MDIO bus of the switch. Replace the comment with a better +explanation. + +Signed-off-by: Arınç ÜNAL +--- + drivers/net/dsa/mt7530.c | 5 ++++- + 1 file changed, 4 insertions(+), 1 deletion(-) + +--- a/drivers/net/dsa/mt7530.c ++++ b/drivers/net/dsa/mt7530.c +@@ -2635,7 +2635,10 @@ mt7531_setup(struct dsa_switch *ds) + if (!priv->p5_sgmii) { + mt7531_pll_setup(priv); + } else { +- /* Let ds->slave_mii_bus be able to access external phy. */ ++ /* Unlike MT7531BE, the GPIO 6-12 pins are not used for RGMII on ++ * MT7531AE. Set the GPIO 11-12 pins to function as MDC and MDIO ++ * to expose the MDIO bus of the switch. ++ */ + mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO11_RG_RXD2_MASK, + MT7531_EXT_P_MDC_11); + mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO12_RG_RXD3_MASK, diff --git a/target/linux/generic/pending-6.1/795-01-net-dsa-mt7530-disable-EEE-abilities-on-failure-on-M.patch b/target/linux/generic/pending-6.1/795-01-net-dsa-mt7530-disable-EEE-abilities-on-failure-on-M.patch deleted file mode 100644 index 44cf60cf14..0000000000 --- a/target/linux/generic/pending-6.1/795-01-net-dsa-mt7530-disable-EEE-abilities-on-failure-on-M.patch +++ /dev/null @@ -1,88 +0,0 @@ -From 856e8954a0a88d1a4d2b43e9002b9249131a156f Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= -Date: Mon, 22 Apr 2024 10:15:08 +0300 -Subject: [PATCH 01/15] net: dsa: mt7530: disable EEE abilities on failure on - MT7531 and MT7988 -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -The MT7531_FORCE_EEE1G and MT7531_FORCE_EEE100 bits let the -PMCR_FORCE_EEE1G and PMCR_FORCE_EEE100 bits determine the 1G/100 EEE -abilities of the MAC. If MT7531_FORCE_EEE1G and MT7531_FORCE_EEE100 are -unset, the abilities are left to be determined by PHY auto polling. - -The commit 40b5d2f15c09 ("net: dsa: mt7530: Add support for EEE features") -made it so that the PMCR_FORCE_EEE1G and PMCR_FORCE_EEE100 bits are set on -mt753x_phylink_mac_link_up(). But it did not set the MT7531_FORCE_EEE1G and -MT7531_FORCE_EEE100 bits. Because of this, the EEE abilities will be -determined by PHY auto polling, regardless of the result of phy_init_eee(). - -Define these bits and add them to the MT7531_FORCE_MODE mask which is set -in mt7531_setup_common(). With this, there won't be any EEE abilities set -when phy_init_eee() returns a negative value. - -Thanks to Russell for explaining when phy_init_eee() could return a -negative value below. - -Looking at phy_init_eee(), it could return a negative value when: - -1. phydev->drv is NULL -2. if genphy_c45_eee_is_active() returns negative -3. if genphy_c45_eee_is_active() returns zero, it returns -EPROTONOSUPPORT -4. if phy_set_bits_mmd() fails (e.g. communication error with the PHY) - -If we then look at genphy_c45_eee_is_active(), then: - -genphy_c45_read_eee_adv() and genphy_c45_read_eee_lpa() propagate their -non-zero return values, otherwise this function returns zero or positive -integer. - -If we then look at genphy_c45_read_eee_adv(), then a failure of -phy_read_mmd() would cause a negative value to be returned. - -Looking at genphy_c45_read_eee_lpa(), the same is true. - -So, it can be summarised as: - -- phydev->drv is NULL -- there is a communication error accessing the PHY -- EEE is not active - -otherwise, it returns zero on success. - -If one wishes to determine whether an error occurred vs EEE not being -supported through negotiation for the negotiated speed, if it returns --EPROTONOSUPPORT in the latter case. Other error codes mean either the -driver has been unloaded or communication error. - -In conclusion, determining the EEE abilities by PHY auto polling shouldn't -result in having any EEE abilities enabled, when one of the last two -situations in the summary happens. And it seems that if phydev->drv is -NULL, there would be bigger problems with the device than a broken link. So -this is not a bugfix. - -Signed-off-by: Arınç ÜNAL ---- - drivers/net/dsa/mt7530.h | 6 +++++- - 1 file changed, 5 insertions(+), 1 deletion(-) - ---- a/drivers/net/dsa/mt7530.h -+++ b/drivers/net/dsa/mt7530.h -@@ -328,11 +328,15 @@ enum mt7530_vlan_port_acc_frm { - #define MT7531_FORCE_DPX BIT(29) - #define MT7531_FORCE_RX_FC BIT(28) - #define MT7531_FORCE_TX_FC BIT(27) -+#define MT7531_FORCE_EEE100 BIT(26) -+#define MT7531_FORCE_EEE1G BIT(25) - #define MT7531_FORCE_MODE (MT7531_FORCE_LNK | \ - MT7531_FORCE_SPD | \ - MT7531_FORCE_DPX | \ - MT7531_FORCE_RX_FC | \ -- MT7531_FORCE_TX_FC) -+ MT7531_FORCE_TX_FC | \ -+ MT7531_FORCE_EEE100 | \ -+ MT7531_FORCE_EEE1G) - #define PMCR_LINK_SETTINGS_MASK (PMCR_TX_EN | PMCR_FORCE_SPEED_1000 | \ - PMCR_RX_EN | PMCR_FORCE_SPEED_100 | \ - PMCR_TX_FC_EN | PMCR_RX_FC_EN | \ diff --git a/target/linux/generic/pending-6.1/795-01-net-dsa-mt7530-do-not-set-MT7530_P5_DIS-when-PHY-.patch b/target/linux/generic/pending-6.1/795-01-net-dsa-mt7530-do-not-set-MT7530_P5_DIS-when-PHY-.patch new file mode 100644 index 0000000000..da3fd7cbe1 --- /dev/null +++ b/target/linux/generic/pending-6.1/795-01-net-dsa-mt7530-do-not-set-MT7530_P5_DIS-when-PHY-.patch @@ -0,0 +1,79 @@ +From patchwork Sat Apr 27 11:24:42 2024 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 8bit +X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTCB2aWEgQjQgUmVsYXk=?= + +X-Patchwork-Id: 13645655 +From: =?utf-8?b?QXLEsW7DpyDDnE5BTCB2aWEgQjQgUmVsYXk=?= + +Date: Sat, 27 Apr 2024 14:24:42 +0300 +Subject: [PATCH net-next] net: dsa: mt7530: do not set MT7530_P5_DIS when + PHY muxing is being used +Precedence: bulk +X-Mailing-List: netdev@vger.kernel.org +List-Id: +List-Subscribe: +List-Unsubscribe: +MIME-Version: 1.0 +Message-Id: + <20240427-for-netnext-mt7530-do-not-disable-port5-when-phy-muxing-v1-1-793cdf9d7707@arinc9.com> +To: Daniel Golle , DENG Qingfang , + Sean Wang , Andrew Lunn , + Florian Fainelli , + Vladimir Oltean , + "David S. Miller" , Eric Dumazet , + Jakub Kicinski , Paolo Abeni , + Matthias Brugger , + AngeloGioacchino Del Regno +Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, + linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, + =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= +X-Mailer: b4 0.13.0 +X-Patchwork-Delegate: kuba@kernel.org + +From: Arınç ÜNAL + +When the PHY muxing feature is in use, port 5 won't be defined in the +device tree. Because of this, the type member of the dsa_port structure for +this port will be assigned DSA_PORT_TYPE_UNUSED. The dsa_port_setup() +function calls ds->ops->port_disable() when the port type is +DSA_PORT_TYPE_UNUSED. + +The MT7530_P5_DIS bit is unset when PHY muxing is being used. +mt7530_port_disable() which is assigned to ds->ops->port_disable() is +called afterwards. Currently, mt7530_port_disable() sets MT7530_P5_DIS +which breaks network connectivity when PHY muxing is being used. + +Therefore, do not set MT7530_P5_DIS when PHY muxing is being used. + +Fixes: 377174c5760c ("net: dsa: mt7530: move MT753X_MTRAP operations for MT7530") +Reported-by: Daniel Golle +Signed-off-by: Arınç ÜNAL +--- +Hello. + +I've sent this to net-next as the patch it fixes is on the current +development cycle. +--- + drivers/net/dsa/mt7530.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + + +--- +base-commit: 5c4c0edca68a5841a8d53ccd49596fe199c8334c +change-id: 20240427-for-netnext-mt7530-do-not-disable-port5-when-phy-muxing-7ff5fd0995d7 + +Best regards, + +--- a/drivers/net/dsa/mt7530.c ++++ b/drivers/net/dsa/mt7530.c +@@ -1213,7 +1213,7 @@ mt7530_port_disable(struct dsa_switch *d + if (priv->id != ID_MT7530 && priv->id != ID_MT7621) + return; + +- if (port == 5) ++ if (port == 5 && priv->p5_mode == GMAC5) + mt7530_set(priv, MT753X_MTRAP, MT7530_P5_DIS); + else if (port == 6) + mt7530_set(priv, MT753X_MTRAP, MT7530_P6_DIS); diff --git a/target/linux/generic/pending-6.1/795-02-net-dsa-mt7530-refactor-MT7530_PMCR_P.patch b/target/linux/generic/pending-6.1/795-02-net-dsa-mt7530-refactor-MT7530_PMCR_P.patch deleted file mode 100644 index 3cbd62e929..0000000000 --- a/target/linux/generic/pending-6.1/795-02-net-dsa-mt7530-refactor-MT7530_PMCR_P.patch +++ /dev/null @@ -1,200 +0,0 @@ -From 712ad00d2f43814c81a7abfcbc339690a05fb6a0 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= -Date: Mon, 22 Apr 2024 10:15:09 +0300 -Subject: [PATCH 02/15] net: dsa: mt7530: refactor MT7530_PMCR_P() -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -The MT7530_PMCR_P() registers are on MT7530, MT7531, and the switch on the -MT7988 SoC. Rename the definition for them to MT753X_PMCR_P(). Bit 15 is -for MT7530 only. Add MT7530 prefix to the definition for bit 15. - -Use GENMASK and FIELD_PREP for PMCR_IFG_XMIT(). - -Rename PMCR_TX_EN and PMCR_RX_EN to PMCR_MAC_TX_EN and PMCR_MAC_TX_EN to -follow the naming on the "MT7621 Giga Switch Programming Guide v0.3", -"MT7531 Reference Manual for Development Board v1.0", and "MT7988A Wi-Fi 7 -Generation Router Platform: Datasheet (Open Version) v0.1" documents. - -These documents show that PMCR_RX_FC_EN is at bit 5. Correct this along -with renaming it to PMCR_FORCE_RX_FC_EN, and the same for PMCR_TX_FC_EN. - -Remove PMCR_SPEED_MASK which doesn't have a use. - -Rename the force mode definitions for MT7531 to FORCE_MODE. Add MASK at the -end for the mask that includes all force mode definitions. - -Signed-off-by: Arınç ÜNAL ---- - drivers/net/dsa/mt7530.c | 24 ++++++++--------- - drivers/net/dsa/mt7530.h | 58 +++++++++++++++++++++------------------- - 2 files changed, 42 insertions(+), 40 deletions(-) - ---- a/drivers/net/dsa/mt7530.c -+++ b/drivers/net/dsa/mt7530.c -@@ -889,7 +889,7 @@ static void mt7530_setup_port5(struct ds - val &= ~MHWTRAP_P5_MAC_SEL & ~MHWTRAP_P5_DIS; - - /* Setup the MAC by default for the cpu port */ -- mt7530_write(priv, MT7530_PMCR_P(5), 0x56300); -+ mt7530_write(priv, MT753X_PMCR_P(5), 0x56300); - break; - case P5_INTF_SEL_GMAC5: - /* MT7530_P5_MODE_GMAC: P5 -> External phy or 2nd GMAC */ -@@ -2435,8 +2435,8 @@ mt7530_setup(struct dsa_switch *ds) - /* Clear link settings and enable force mode to force link down - * on all ports until they're enabled later. - */ -- mt7530_rmw(priv, MT7530_PMCR_P(i), PMCR_LINK_SETTINGS_MASK | -- PMCR_FORCE_MODE, PMCR_FORCE_MODE); -+ mt7530_rmw(priv, MT753X_PMCR_P(i), PMCR_LINK_SETTINGS_MASK | -+ MT7530_FORCE_MODE, MT7530_FORCE_MODE); - - /* Disable forwarding by default on all ports */ - mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK, -@@ -2546,8 +2546,8 @@ mt7531_setup_common(struct dsa_switch *d - /* Clear link settings and enable force mode to force link down - * on all ports until they're enabled later. - */ -- mt7530_rmw(priv, MT7530_PMCR_P(i), PMCR_LINK_SETTINGS_MASK | -- MT7531_FORCE_MODE, MT7531_FORCE_MODE); -+ mt7530_rmw(priv, MT753X_PMCR_P(i), PMCR_LINK_SETTINGS_MASK | -+ MT7531_FORCE_MODE_MASK, MT7531_FORCE_MODE_MASK); - - /* Disable forwarding by default on all ports */ - mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK, -@@ -2630,7 +2630,7 @@ mt7531_setup(struct dsa_switch *ds) - - /* Force link down on all ports before internal reset */ - for (i = 0; i < MT7530_NUM_PORTS; i++) -- mt7530_write(priv, MT7530_PMCR_P(i), MT7531_FORCE_LNK); -+ mt7530_write(priv, MT753X_PMCR_P(i), MT7531_FORCE_MODE_LNK); - - /* Reset the switch through internal reset */ - mt7530_write(priv, MT7530_SYS_CTRL, SYS_CTRL_SW_RST | SYS_CTRL_REG_RST); -@@ -2872,7 +2872,7 @@ mt753x_phylink_mac_config(struct phylink - - /* Are we connected to external phy */ - if (port == 5 && dsa_is_user_port(ds, 5)) -- mt7530_set(priv, MT7530_PMCR_P(port), PMCR_EXT_PHY); -+ mt7530_set(priv, MT753X_PMCR_P(port), PMCR_EXT_PHY); - } - - static void mt753x_phylink_mac_link_down(struct phylink_config *config, -@@ -2882,7 +2882,7 @@ static void mt753x_phylink_mac_link_down - struct dsa_port *dp = dsa_phylink_to_port(config); - struct mt7530_priv *priv = dp->ds->priv; - -- mt7530_clear(priv, MT7530_PMCR_P(dp->index), PMCR_LINK_SETTINGS_MASK); -+ mt7530_clear(priv, MT753X_PMCR_P(dp->index), PMCR_LINK_SETTINGS_MASK); - } - - static void mt753x_phylink_mac_link_up(struct phylink_config *config, -@@ -2896,7 +2896,7 @@ static void mt753x_phylink_mac_link_up(s - struct mt7530_priv *priv = dp->ds->priv; - u32 mcr; - -- mcr = PMCR_RX_EN | PMCR_TX_EN | PMCR_FORCE_LNK; -+ mcr = PMCR_MAC_RX_EN | PMCR_MAC_TX_EN | PMCR_FORCE_LNK; - - switch (speed) { - case SPEED_1000: -@@ -2911,9 +2911,9 @@ static void mt753x_phylink_mac_link_up(s - if (duplex == DUPLEX_FULL) { - mcr |= PMCR_FORCE_FDX; - if (tx_pause) -- mcr |= PMCR_TX_FC_EN; -+ mcr |= PMCR_FORCE_TX_FC_EN; - if (rx_pause) -- mcr |= PMCR_RX_FC_EN; -+ mcr |= PMCR_FORCE_RX_FC_EN; - } - - if (mode == MLO_AN_PHY && phydev && phy_init_eee(phydev, false) >= 0) { -@@ -2928,7 +2928,7 @@ static void mt753x_phylink_mac_link_up(s - } - } - -- mt7530_set(priv, MT7530_PMCR_P(dp->index), mcr); -+ mt7530_set(priv, MT753X_PMCR_P(dp->index), mcr); - } - - static void mt753x_phylink_get_caps(struct dsa_switch *ds, int port, ---- a/drivers/net/dsa/mt7530.h -+++ b/drivers/net/dsa/mt7530.h -@@ -304,44 +304,46 @@ enum mt7530_vlan_port_acc_frm { - #define G0_PORT_VID_DEF G0_PORT_VID(0) - - /* Register for port MAC control register */ --#define MT7530_PMCR_P(x) (0x3000 + ((x) * 0x100)) --#define PMCR_IFG_XMIT(x) (((x) & 0x3) << 18) -+#define MT753X_PMCR_P(x) (0x3000 + ((x) * 0x100)) -+#define PMCR_IFG_XMIT_MASK GENMASK(19, 18) -+#define PMCR_IFG_XMIT(x) FIELD_PREP(PMCR_IFG_XMIT_MASK, x) - #define PMCR_EXT_PHY BIT(17) - #define PMCR_MAC_MODE BIT(16) --#define PMCR_FORCE_MODE BIT(15) --#define PMCR_TX_EN BIT(14) --#define PMCR_RX_EN BIT(13) -+#define MT7530_FORCE_MODE BIT(15) -+#define PMCR_MAC_TX_EN BIT(14) -+#define PMCR_MAC_RX_EN BIT(13) - #define PMCR_BACKOFF_EN BIT(9) - #define PMCR_BACKPR_EN BIT(8) - #define PMCR_FORCE_EEE1G BIT(7) - #define PMCR_FORCE_EEE100 BIT(6) --#define PMCR_TX_FC_EN BIT(5) --#define PMCR_RX_FC_EN BIT(4) -+#define PMCR_FORCE_RX_FC_EN BIT(5) -+#define PMCR_FORCE_TX_FC_EN BIT(4) - #define PMCR_FORCE_SPEED_1000 BIT(3) - #define PMCR_FORCE_SPEED_100 BIT(2) - #define PMCR_FORCE_FDX BIT(1) - #define PMCR_FORCE_LNK BIT(0) --#define PMCR_SPEED_MASK (PMCR_FORCE_SPEED_100 | \ -- PMCR_FORCE_SPEED_1000) --#define MT7531_FORCE_LNK BIT(31) --#define MT7531_FORCE_SPD BIT(30) --#define MT7531_FORCE_DPX BIT(29) --#define MT7531_FORCE_RX_FC BIT(28) --#define MT7531_FORCE_TX_FC BIT(27) --#define MT7531_FORCE_EEE100 BIT(26) --#define MT7531_FORCE_EEE1G BIT(25) --#define MT7531_FORCE_MODE (MT7531_FORCE_LNK | \ -- MT7531_FORCE_SPD | \ -- MT7531_FORCE_DPX | \ -- MT7531_FORCE_RX_FC | \ -- MT7531_FORCE_TX_FC | \ -- MT7531_FORCE_EEE100 | \ -- MT7531_FORCE_EEE1G) --#define PMCR_LINK_SETTINGS_MASK (PMCR_TX_EN | PMCR_FORCE_SPEED_1000 | \ -- PMCR_RX_EN | PMCR_FORCE_SPEED_100 | \ -- PMCR_TX_FC_EN | PMCR_RX_FC_EN | \ -- PMCR_FORCE_FDX | PMCR_FORCE_LNK | \ -- PMCR_FORCE_EEE1G | PMCR_FORCE_EEE100) -+#define MT7531_FORCE_MODE_LNK BIT(31) -+#define MT7531_FORCE_MODE_SPD BIT(30) -+#define MT7531_FORCE_MODE_DPX BIT(29) -+#define MT7531_FORCE_MODE_RX_FC BIT(28) -+#define MT7531_FORCE_MODE_TX_FC BIT(27) -+#define MT7531_FORCE_MODE_EEE100 BIT(26) -+#define MT7531_FORCE_MODE_EEE1G BIT(25) -+#define MT7531_FORCE_MODE_MASK (MT7531_FORCE_MODE_LNK | \ -+ MT7531_FORCE_MODE_SPD | \ -+ MT7531_FORCE_MODE_DPX | \ -+ MT7531_FORCE_MODE_RX_FC | \ -+ MT7531_FORCE_MODE_TX_FC | \ -+ MT7531_FORCE_MODE_EEE100 | \ -+ MT7531_FORCE_MODE_EEE1G) -+#define PMCR_LINK_SETTINGS_MASK (PMCR_MAC_TX_EN | PMCR_MAC_RX_EN | \ -+ PMCR_FORCE_EEE1G | \ -+ PMCR_FORCE_EEE100 | \ -+ PMCR_FORCE_RX_FC_EN | \ -+ PMCR_FORCE_TX_FC_EN | \ -+ PMCR_FORCE_SPEED_1000 | \ -+ PMCR_FORCE_SPEED_100 | \ -+ PMCR_FORCE_FDX | PMCR_FORCE_LNK) - - #define MT7530_PMEEECR_P(x) (0x3004 + (x) * 0x100) - #define WAKEUP_TIME_1000(x) (((x) & 0xFF) << 24) diff --git a/target/linux/generic/pending-6.1/795-03-net-dsa-mt7530-rename-p5_intf_sel-and-use-only-for-M.patch b/target/linux/generic/pending-6.1/795-03-net-dsa-mt7530-rename-p5_intf_sel-and-use-only-for-M.patch deleted file mode 100644 index 9697e7eb4f..0000000000 --- a/target/linux/generic/pending-6.1/795-03-net-dsa-mt7530-rename-p5_intf_sel-and-use-only-for-M.patch +++ /dev/null @@ -1,185 +0,0 @@ -From 875ec5b67ab88e969b171e6e9ea803e3ed759614 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= -Date: Mon, 22 Apr 2024 10:15:10 +0300 -Subject: [PATCH 03/15] net: dsa: mt7530: rename p5_intf_sel and use only for - MT7530 switch -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -The p5_intf_sel pointer is used to store the information of whether PHY -muxing is used or not. PHY muxing is a feature specific to port 5 of the -MT7530 switch. Do not use it for other switch models. - -Rename the pointer to p5_mode to store the mode the port is being used in. -Rename the p5_interface_select enum to mt7530_p5_mode, the string -representation to mt7530_p5_mode_str, and the enum elements. - -If PHY muxing is not detected, the default mode, GMAC5, will be used. - -Signed-off-by: Arınç ÜNAL ---- - drivers/net/dsa/mt7530.c | 62 +++++++++++++++++----------------------- - drivers/net/dsa/mt7530.h | 15 +++++----- - 2 files changed, 33 insertions(+), 44 deletions(-) - ---- a/drivers/net/dsa/mt7530.c -+++ b/drivers/net/dsa/mt7530.c -@@ -850,19 +850,15 @@ mt7530_set_ageing_time(struct dsa_switch - return 0; - } - --static const char *p5_intf_modes(unsigned int p5_interface) -+static const char *mt7530_p5_mode_str(unsigned int mode) - { -- switch (p5_interface) { -- case P5_DISABLED: -- return "DISABLED"; -- case P5_INTF_SEL_PHY_P0: -- return "PHY P0"; -- case P5_INTF_SEL_PHY_P4: -- return "PHY P4"; -- case P5_INTF_SEL_GMAC5: -- return "GMAC5"; -+ switch (mode) { -+ case MUX_PHY_P0: -+ return "MUX PHY P0"; -+ case MUX_PHY_P4: -+ return "MUX PHY P4"; - default: -- return "unknown"; -+ return "GMAC5"; - } - } - -@@ -879,23 +875,23 @@ static void mt7530_setup_port5(struct ds - val |= MHWTRAP_MANUAL | MHWTRAP_P5_MAC_SEL | MHWTRAP_P5_DIS; - val &= ~MHWTRAP_P5_RGMII_MODE & ~MHWTRAP_PHY0_SEL; - -- switch (priv->p5_intf_sel) { -- case P5_INTF_SEL_PHY_P0: -- /* MT7530_P5_MODE_GPHY_P0: 2nd GMAC -> P5 -> P0 */ -+ switch (priv->p5_mode) { -+ /* MUX_PHY_P0: P0 -> P5 -> SoC MAC */ -+ case MUX_PHY_P0: - val |= MHWTRAP_PHY0_SEL; - fallthrough; -- case P5_INTF_SEL_PHY_P4: -- /* MT7530_P5_MODE_GPHY_P4: 2nd GMAC -> P5 -> P4 */ -+ -+ /* MUX_PHY_P4: P4 -> P5 -> SoC MAC */ -+ case MUX_PHY_P4: - val &= ~MHWTRAP_P5_MAC_SEL & ~MHWTRAP_P5_DIS; - - /* Setup the MAC by default for the cpu port */ - mt7530_write(priv, MT753X_PMCR_P(5), 0x56300); - break; -- case P5_INTF_SEL_GMAC5: -- /* MT7530_P5_MODE_GMAC: P5 -> External phy or 2nd GMAC */ -- val &= ~MHWTRAP_P5_DIS; -- break; -+ -+ /* GMAC5: P5 -> SoC MAC or external PHY */ - default: -+ val &= ~MHWTRAP_P5_DIS; - break; - } - -@@ -923,8 +919,8 @@ static void mt7530_setup_port5(struct ds - - mt7530_write(priv, MT7530_MHWTRAP, val); - -- dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, intf_sel=%s, phy-mode=%s\n", -- val, p5_intf_modes(priv->p5_intf_sel), phy_modes(interface)); -+ dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, mode=%s, phy-mode=%s\n", val, -+ mt7530_p5_mode_str(priv->p5_mode), phy_modes(interface)); - - mutex_unlock(&priv->reg_mutex); - } -@@ -2467,13 +2463,11 @@ mt7530_setup(struct dsa_switch *ds) - if (ret) - return ret; - -- /* Setup port 5 */ -- if (!dsa_is_unused_port(ds, 5)) { -- priv->p5_intf_sel = P5_INTF_SEL_GMAC5; -- } else { -+ /* Check for PHY muxing on port 5 */ -+ if (dsa_is_unused_port(ds, 5)) { - /* Scan the ethernet nodes. Look for GMAC1, lookup the used PHY. -- * Set priv->p5_intf_sel to the appropriate value if PHY muxing -- * is detected. -+ * Set priv->p5_mode to the appropriate value if PHY muxing is -+ * detected. - */ - for_each_child_of_node(dn, mac_np) { - if (!of_device_is_compatible(mac_np, -@@ -2497,17 +2491,16 @@ mt7530_setup(struct dsa_switch *ds) - } - id = of_mdio_parse_addr(ds->dev, phy_node); - if (id == 0) -- priv->p5_intf_sel = P5_INTF_SEL_PHY_P0; -+ priv->p5_mode = MUX_PHY_P0; - if (id == 4) -- priv->p5_intf_sel = P5_INTF_SEL_PHY_P4; -+ priv->p5_mode = MUX_PHY_P4; - } - of_node_put(mac_np); - of_node_put(phy_node); - break; - } - -- if (priv->p5_intf_sel == P5_INTF_SEL_PHY_P0 || -- priv->p5_intf_sel == P5_INTF_SEL_PHY_P4) -+ if (priv->p5_mode == MUX_PHY_P0 || priv->p5_mode == MUX_PHY_P4) - mt7530_setup_port5(ds, interface); - } - -@@ -2645,9 +2638,6 @@ mt7531_setup(struct dsa_switch *ds) - MT7531_EXT_P_MDIO_12); - } - -- if (!dsa_is_unused_port(ds, 5)) -- priv->p5_intf_sel = P5_INTF_SEL_GMAC5; -- - mt7530_rmw(priv, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK, - MT7531_GPIO0_INTERRUPT); - ---- a/drivers/net/dsa/mt7530.h -+++ b/drivers/net/dsa/mt7530.h -@@ -708,12 +708,11 @@ struct mt7530_port { - struct phylink_pcs *sgmii_pcs; - }; - --/* Port 5 interface select definitions */ --enum p5_interface_select { -- P5_DISABLED, -- P5_INTF_SEL_PHY_P0, -- P5_INTF_SEL_PHY_P4, -- P5_INTF_SEL_GMAC5, -+/* Port 5 mode definitions of the MT7530 switch */ -+enum mt7530_p5_mode { -+ GMAC5, -+ MUX_PHY_P0, -+ MUX_PHY_P4, - }; - - struct mt7530_priv; -@@ -769,7 +768,7 @@ struct mt753x_info { - * @ports: Holding the state among ports - * @reg_mutex: The lock for protecting among process accessing - * registers -- * @p5_intf_sel: Holding the current port 5 interface select -+ * @p5_mode: Holding the current mode of port 5 of the MT7530 switch - * @p5_sgmii: Flag for distinguishing if port 5 of the MT7531 switch - * has got SGMII - * @irq: IRQ number of the switch -@@ -791,7 +790,7 @@ struct mt7530_priv { - const struct mt753x_info *info; - unsigned int id; - bool mcm; -- enum p5_interface_select p5_intf_sel; -+ enum mt7530_p5_mode p5_mode; - bool p5_sgmii; - u8 mirror_rx; - u8 mirror_tx; diff --git a/target/linux/generic/pending-6.1/795-04-net-dsa-mt7530-rename-mt753x_bpdu_port_fw-enum-to-mt.patch b/target/linux/generic/pending-6.1/795-04-net-dsa-mt7530-rename-mt753x_bpdu_port_fw-enum-to-mt.patch deleted file mode 100644 index 77a2df8586..0000000000 --- a/target/linux/generic/pending-6.1/795-04-net-dsa-mt7530-rename-mt753x_bpdu_port_fw-enum-to-mt.patch +++ /dev/null @@ -1,169 +0,0 @@ -From 83fe3df057e641cd0e88425e579d7a5a370ca430 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= -Date: Mon, 22 Apr 2024 10:15:11 +0300 -Subject: [PATCH 04/15] net: dsa: mt7530: rename mt753x_bpdu_port_fw enum to - mt753x_to_cpu_fw -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -The mt753x_bpdu_port_fw enum is globally used for manipulating the process -of deciding the forwardable ports, specifically concerning the CPU port(s). -Therefore, rename it and the values in it to mt753x_to_cpu_fw. - -Change FOLLOW_MFC to SYSTEM_DEFAULT to be on par with the switch documents. - -Signed-off-by: Arınç ÜNAL ---- - drivers/net/dsa/mt7530.c | 44 ++++++++++------------- - drivers/net/dsa/mt7530.h | 76 ++++++++++++++++++++-------------------- - 2 files changed, 56 insertions(+), 64 deletions(-) - ---- a/drivers/net/dsa/mt7530.c -+++ b/drivers/net/dsa/mt7530.c -@@ -1100,42 +1100,34 @@ mt753x_trap_frames(struct mt7530_priv *p - * VLAN-untagged. - */ - mt7530_rmw(priv, MT753X_BPC, -- MT753X_PAE_BPDU_FR | MT753X_PAE_EG_TAG_MASK | -- MT753X_PAE_PORT_FW_MASK | MT753X_BPDU_EG_TAG_MASK | -- MT753X_BPDU_PORT_FW_MASK, -- MT753X_PAE_BPDU_FR | -- MT753X_PAE_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | -- MT753X_PAE_PORT_FW(MT753X_BPDU_CPU_ONLY) | -- MT753X_BPDU_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | -- MT753X_BPDU_CPU_ONLY); -+ PAE_BPDU_FR | PAE_EG_TAG_MASK | PAE_PORT_FW_MASK | -+ BPDU_EG_TAG_MASK | BPDU_PORT_FW_MASK, -+ PAE_BPDU_FR | PAE_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | -+ PAE_PORT_FW(TO_CPU_FW_CPU_ONLY) | -+ BPDU_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | -+ TO_CPU_FW_CPU_ONLY); - - /* Trap frames with :01 and :02 MAC DAs to the CPU port(s) and egress - * them VLAN-untagged. - */ - mt7530_rmw(priv, MT753X_RGAC1, -- MT753X_R02_BPDU_FR | MT753X_R02_EG_TAG_MASK | -- MT753X_R02_PORT_FW_MASK | MT753X_R01_BPDU_FR | -- MT753X_R01_EG_TAG_MASK | MT753X_R01_PORT_FW_MASK, -- MT753X_R02_BPDU_FR | -- MT753X_R02_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | -- MT753X_R02_PORT_FW(MT753X_BPDU_CPU_ONLY) | -- MT753X_R01_BPDU_FR | -- MT753X_R01_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | -- MT753X_BPDU_CPU_ONLY); -+ R02_BPDU_FR | R02_EG_TAG_MASK | R02_PORT_FW_MASK | -+ R01_BPDU_FR | R01_EG_TAG_MASK | R01_PORT_FW_MASK, -+ R02_BPDU_FR | R02_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | -+ R02_PORT_FW(TO_CPU_FW_CPU_ONLY) | R01_BPDU_FR | -+ R01_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | -+ TO_CPU_FW_CPU_ONLY); - - /* Trap frames with :03 and :0E MAC DAs to the CPU port(s) and egress - * them VLAN-untagged. - */ - mt7530_rmw(priv, MT753X_RGAC2, -- MT753X_R0E_BPDU_FR | MT753X_R0E_EG_TAG_MASK | -- MT753X_R0E_PORT_FW_MASK | MT753X_R03_BPDU_FR | -- MT753X_R03_EG_TAG_MASK | MT753X_R03_PORT_FW_MASK, -- MT753X_R0E_BPDU_FR | -- MT753X_R0E_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | -- MT753X_R0E_PORT_FW(MT753X_BPDU_CPU_ONLY) | -- MT753X_R03_BPDU_FR | -- MT753X_R03_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | -- MT753X_BPDU_CPU_ONLY); -+ R0E_BPDU_FR | R0E_EG_TAG_MASK | R0E_PORT_FW_MASK | -+ R03_BPDU_FR | R03_EG_TAG_MASK | R03_PORT_FW_MASK, -+ R0E_BPDU_FR | R0E_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | -+ R0E_PORT_FW(TO_CPU_FW_CPU_ONLY) | R03_BPDU_FR | -+ R03_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | -+ TO_CPU_FW_CPU_ONLY); - } - - static void ---- a/drivers/net/dsa/mt7530.h -+++ b/drivers/net/dsa/mt7530.h -@@ -67,47 +67,47 @@ enum mt753x_id { - #define MT753X_MIRROR_MASK(id) ((((id) == ID_MT7531) || ((id) == ID_MT7988)) ? \ - MT7531_MIRROR_MASK : MIRROR_MASK) - --/* Registers for BPDU and PAE frame control*/ -+/* Register for BPDU and PAE frame control */ - #define MT753X_BPC 0x24 --#define MT753X_PAE_BPDU_FR BIT(25) --#define MT753X_PAE_EG_TAG_MASK GENMASK(24, 22) --#define MT753X_PAE_EG_TAG(x) FIELD_PREP(MT753X_PAE_EG_TAG_MASK, x) --#define MT753X_PAE_PORT_FW_MASK GENMASK(18, 16) --#define MT753X_PAE_PORT_FW(x) FIELD_PREP(MT753X_PAE_PORT_FW_MASK, x) --#define MT753X_BPDU_EG_TAG_MASK GENMASK(8, 6) --#define MT753X_BPDU_EG_TAG(x) FIELD_PREP(MT753X_BPDU_EG_TAG_MASK, x) --#define MT753X_BPDU_PORT_FW_MASK GENMASK(2, 0) -+#define PAE_BPDU_FR BIT(25) -+#define PAE_EG_TAG_MASK GENMASK(24, 22) -+#define PAE_EG_TAG(x) FIELD_PREP(PAE_EG_TAG_MASK, x) -+#define PAE_PORT_FW_MASK GENMASK(18, 16) -+#define PAE_PORT_FW(x) FIELD_PREP(PAE_PORT_FW_MASK, x) -+#define BPDU_EG_TAG_MASK GENMASK(8, 6) -+#define BPDU_EG_TAG(x) FIELD_PREP(BPDU_EG_TAG_MASK, x) -+#define BPDU_PORT_FW_MASK GENMASK(2, 0) - --/* Register for :01 and :02 MAC DA frame control */ -+/* Register for 01-80-C2-00-00-[01,02] MAC DA frame control */ - #define MT753X_RGAC1 0x28 --#define MT753X_R02_BPDU_FR BIT(25) --#define MT753X_R02_EG_TAG_MASK GENMASK(24, 22) --#define MT753X_R02_EG_TAG(x) FIELD_PREP(MT753X_R02_EG_TAG_MASK, x) --#define MT753X_R02_PORT_FW_MASK GENMASK(18, 16) --#define MT753X_R02_PORT_FW(x) FIELD_PREP(MT753X_R02_PORT_FW_MASK, x) --#define MT753X_R01_BPDU_FR BIT(9) --#define MT753X_R01_EG_TAG_MASK GENMASK(8, 6) --#define MT753X_R01_EG_TAG(x) FIELD_PREP(MT753X_R01_EG_TAG_MASK, x) --#define MT753X_R01_PORT_FW_MASK GENMASK(2, 0) -+#define R02_BPDU_FR BIT(25) -+#define R02_EG_TAG_MASK GENMASK(24, 22) -+#define R02_EG_TAG(x) FIELD_PREP(R02_EG_TAG_MASK, x) -+#define R02_PORT_FW_MASK GENMASK(18, 16) -+#define R02_PORT_FW(x) FIELD_PREP(R02_PORT_FW_MASK, x) -+#define R01_BPDU_FR BIT(9) -+#define R01_EG_TAG_MASK GENMASK(8, 6) -+#define R01_EG_TAG(x) FIELD_PREP(R01_EG_TAG_MASK, x) -+#define R01_PORT_FW_MASK GENMASK(2, 0) - --/* Register for :03 and :0E MAC DA frame control */ -+/* Register for 01-80-C2-00-00-[03,0E] MAC DA frame control */ - #define MT753X_RGAC2 0x2c --#define MT753X_R0E_BPDU_FR BIT(25) --#define MT753X_R0E_EG_TAG_MASK GENMASK(24, 22) --#define MT753X_R0E_EG_TAG(x) FIELD_PREP(MT753X_R0E_EG_TAG_MASK, x) --#define MT753X_R0E_PORT_FW_MASK GENMASK(18, 16) --#define MT753X_R0E_PORT_FW(x) FIELD_PREP(MT753X_R0E_PORT_FW_MASK, x) --#define MT753X_R03_BPDU_FR BIT(9) --#define MT753X_R03_EG_TAG_MASK GENMASK(8, 6) --#define MT753X_R03_EG_TAG(x) FIELD_PREP(MT753X_R03_EG_TAG_MASK, x) --#define MT753X_R03_PORT_FW_MASK GENMASK(2, 0) -+#define R0E_BPDU_FR BIT(25) -+#define R0E_EG_TAG_MASK GENMASK(24, 22) -+#define R0E_EG_TAG(x) FIELD_PREP(R0E_EG_TAG_MASK, x) -+#define R0E_PORT_FW_MASK GENMASK(18, 16) -+#define R0E_PORT_FW(x) FIELD_PREP(R0E_PORT_FW_MASK, x) -+#define R03_BPDU_FR BIT(9) -+#define R03_EG_TAG_MASK GENMASK(8, 6) -+#define R03_EG_TAG(x) FIELD_PREP(R03_EG_TAG_MASK, x) -+#define R03_PORT_FW_MASK GENMASK(2, 0) - --enum mt753x_bpdu_port_fw { -- MT753X_BPDU_FOLLOW_MFC, -- MT753X_BPDU_CPU_EXCLUDE = 4, -- MT753X_BPDU_CPU_INCLUDE = 5, -- MT753X_BPDU_CPU_ONLY = 6, -- MT753X_BPDU_DROP = 7, -+enum mt753x_to_cpu_fw { -+ TO_CPU_FW_SYSTEM_DEFAULT, -+ TO_CPU_FW_CPU_EXCLUDE = 4, -+ TO_CPU_FW_CPU_INCLUDE = 5, -+ TO_CPU_FW_CPU_ONLY = 6, -+ TO_CPU_FW_DROP = 7, - }; - - /* Registers for address table access */ diff --git a/target/linux/generic/pending-6.1/795-05-net-dsa-mt7530-refactor-MT7530_MFC-and-MT7531_CFC-ad.patch b/target/linux/generic/pending-6.1/795-05-net-dsa-mt7530-refactor-MT7530_MFC-and-MT7531_CFC-ad.patch deleted file mode 100644 index 95cdfac02e..0000000000 --- a/target/linux/generic/pending-6.1/795-05-net-dsa-mt7530-refactor-MT7530_MFC-and-MT7531_CFC-ad.patch +++ /dev/null @@ -1,201 +0,0 @@ -From 1dbc1bdc2869e6d2929235c70d64e393aa5a5fa2 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= -Date: Mon, 22 Apr 2024 10:15:12 +0300 -Subject: [PATCH 05/15] net: dsa: mt7530: refactor MT7530_MFC and MT7531_CFC, - add MT7531_QRY_FFP -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -The MT7530_MFC register is on MT7530, MT7531, and the switch on the MT7988 -SoC. Rename it to MT753X_MFC. Bit 7 to 0 differs between MT7530 and -MT7531/MT7988. Add MT7530 prefix to these definitions, and define the -IGMP/MLD Query Frame Flooding Ports mask for MT7531. - -Rename the cases of MIRROR_MASK to MIRROR_PORT_MASK. - -Move mt753x_mirror_port_get() and mt753x_port_mirror_set() to mt7530.h as -macros. - -Signed-off-by: Arınç ÜNAL ---- - drivers/net/dsa/mt7530.c | 38 ++++++++-------------- - drivers/net/dsa/mt7530.h | 69 +++++++++++++++++++++++++--------------- - 2 files changed, 57 insertions(+), 50 deletions(-) - ---- a/drivers/net/dsa/mt7530.c -+++ b/drivers/net/dsa/mt7530.c -@@ -1140,7 +1140,7 @@ mt753x_cpu_port_enable(struct dsa_switch - PORT_SPEC_TAG); - - /* Enable flooding on the CPU port */ -- mt7530_set(priv, MT7530_MFC, BC_FFP(BIT(port)) | UNM_FFP(BIT(port)) | -+ mt7530_set(priv, MT753X_MFC, BC_FFP(BIT(port)) | UNM_FFP(BIT(port)) | - UNU_FFP(BIT(port))); - - /* Add the CPU port to the CPU port bitmap for MT7531 and the switch on -@@ -1304,15 +1304,15 @@ mt7530_port_bridge_flags(struct dsa_swit - flags.val & BR_LEARNING ? 0 : SA_DIS); - - if (flags.mask & BR_FLOOD) -- mt7530_rmw(priv, MT7530_MFC, UNU_FFP(BIT(port)), -+ mt7530_rmw(priv, MT753X_MFC, UNU_FFP(BIT(port)), - flags.val & BR_FLOOD ? UNU_FFP(BIT(port)) : 0); - - if (flags.mask & BR_MCAST_FLOOD) -- mt7530_rmw(priv, MT7530_MFC, UNM_FFP(BIT(port)), -+ mt7530_rmw(priv, MT753X_MFC, UNM_FFP(BIT(port)), - flags.val & BR_MCAST_FLOOD ? UNM_FFP(BIT(port)) : 0); - - if (flags.mask & BR_BCAST_FLOOD) -- mt7530_rmw(priv, MT7530_MFC, BC_FFP(BIT(port)), -+ mt7530_rmw(priv, MT753X_MFC, BC_FFP(BIT(port)), - flags.val & BR_BCAST_FLOOD ? BC_FFP(BIT(port)) : 0); - - return 0; -@@ -1848,20 +1848,6 @@ mt7530_port_vlan_del(struct dsa_switch * - return 0; - } - --static int mt753x_mirror_port_get(unsigned int id, u32 val) --{ -- return (id == ID_MT7531 || id == ID_MT7988) ? -- MT7531_MIRROR_PORT_GET(val) : -- MIRROR_PORT(val); --} -- --static int mt753x_mirror_port_set(unsigned int id, u32 val) --{ -- return (id == ID_MT7531 || id == ID_MT7988) ? -- MT7531_MIRROR_PORT_SET(val) : -- MIRROR_PORT(val); --} -- - static int mt753x_port_mirror_add(struct dsa_switch *ds, int port, - struct dsa_mall_mirror_tc_entry *mirror, - bool ingress, struct netlink_ext_ack *extack) -@@ -1877,14 +1863,14 @@ static int mt753x_port_mirror_add(struct - val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id)); - - /* MT7530 only supports one monitor port */ -- monitor_port = mt753x_mirror_port_get(priv->id, val); -+ monitor_port = MT753X_MIRROR_PORT_GET(priv->id, val); - if (val & MT753X_MIRROR_EN(priv->id) && - monitor_port != mirror->to_local_port) - return -EEXIST; - - val |= MT753X_MIRROR_EN(priv->id); -- val &= ~MT753X_MIRROR_MASK(priv->id); -- val |= mt753x_mirror_port_set(priv->id, mirror->to_local_port); -+ val &= ~MT753X_MIRROR_PORT_MASK(priv->id); -+ val |= MT753X_MIRROR_PORT_SET(priv->id, mirror->to_local_port); - mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val); - - val = mt7530_read(priv, MT7530_PCR_P(port)); -@@ -2524,7 +2510,7 @@ mt7531_setup_common(struct dsa_switch *d - mt7530_mib_reset(ds); - - /* Disable flooding on all ports */ -- mt7530_clear(priv, MT7530_MFC, BC_FFP_MASK | UNM_FFP_MASK | -+ mt7530_clear(priv, MT753X_MFC, BC_FFP_MASK | UNM_FFP_MASK | - UNU_FFP_MASK); - - for (i = 0; i < MT7530_NUM_PORTS; i++) { -@@ -3086,10 +3072,12 @@ mt753x_conduit_state_change(struct dsa_s - else - priv->active_cpu_ports &= ~mask; - -- if (priv->active_cpu_ports) -- val = CPU_EN | CPU_PORT(__ffs(priv->active_cpu_ports)); -+ if (priv->active_cpu_ports) { -+ val = MT7530_CPU_EN | -+ MT7530_CPU_PORT(__ffs(priv->active_cpu_ports)); -+ } - -- mt7530_rmw(priv, MT7530_MFC, CPU_EN | CPU_PORT_MASK, val); -+ mt7530_rmw(priv, MT753X_MFC, MT7530_CPU_EN | MT7530_CPU_PORT_MASK, val); - } - - static int mt7988_setup(struct dsa_switch *ds) ---- a/drivers/net/dsa/mt7530.h -+++ b/drivers/net/dsa/mt7530.h -@@ -36,36 +36,55 @@ enum mt753x_id { - #define MT753X_AGC 0xc - #define LOCAL_EN BIT(7) - --/* Registers to mac forward control for unknown frames */ --#define MT7530_MFC 0x10 --#define BC_FFP(x) (((x) & 0xff) << 24) --#define BC_FFP_MASK BC_FFP(~0) --#define UNM_FFP(x) (((x) & 0xff) << 16) --#define UNM_FFP_MASK UNM_FFP(~0) --#define UNU_FFP(x) (((x) & 0xff) << 8) --#define UNU_FFP_MASK UNU_FFP(~0) --#define CPU_EN BIT(7) --#define CPU_PORT_MASK GENMASK(6, 4) --#define CPU_PORT(x) FIELD_PREP(CPU_PORT_MASK, x) --#define MIRROR_EN BIT(3) --#define MIRROR_PORT(x) ((x) & 0x7) --#define MIRROR_MASK 0x7 -+/* Register for MAC forward control */ -+#define MT753X_MFC 0x10 -+#define BC_FFP_MASK GENMASK(31, 24) -+#define BC_FFP(x) FIELD_PREP(BC_FFP_MASK, x) -+#define UNM_FFP_MASK GENMASK(23, 16) -+#define UNM_FFP(x) FIELD_PREP(UNM_FFP_MASK, x) -+#define UNU_FFP_MASK GENMASK(15, 8) -+#define UNU_FFP(x) FIELD_PREP(UNU_FFP_MASK, x) -+#define MT7530_CPU_EN BIT(7) -+#define MT7530_CPU_PORT_MASK GENMASK(6, 4) -+#define MT7530_CPU_PORT(x) FIELD_PREP(MT7530_CPU_PORT_MASK, x) -+#define MT7530_MIRROR_EN BIT(3) -+#define MT7530_MIRROR_PORT_MASK GENMASK(2, 0) -+#define MT7530_MIRROR_PORT_GET(x) FIELD_GET(MT7530_MIRROR_PORT_MASK, x) -+#define MT7530_MIRROR_PORT_SET(x) FIELD_PREP(MT7530_MIRROR_PORT_MASK, x) -+#define MT7531_QRY_FFP_MASK GENMASK(7, 0) -+#define MT7531_QRY_FFP(x) FIELD_PREP(MT7531_QRY_FFP_MASK, x) - --/* Registers for CPU forward control */ -+/* Register for CPU forward control */ - #define MT7531_CFC 0x4 - #define MT7531_MIRROR_EN BIT(19) --#define MT7531_MIRROR_MASK (MIRROR_MASK << 16) --#define MT7531_MIRROR_PORT_GET(x) (((x) >> 16) & MIRROR_MASK) --#define MT7531_MIRROR_PORT_SET(x) (((x) & MIRROR_MASK) << 16) -+#define MT7531_MIRROR_PORT_MASK GENMASK(18, 16) -+#define MT7531_MIRROR_PORT_GET(x) FIELD_GET(MT7531_MIRROR_PORT_MASK, x) -+#define MT7531_MIRROR_PORT_SET(x) FIELD_PREP(MT7531_MIRROR_PORT_MASK, x) - #define MT7531_CPU_PMAP_MASK GENMASK(7, 0) - #define MT7531_CPU_PMAP(x) FIELD_PREP(MT7531_CPU_PMAP_MASK, x) - --#define MT753X_MIRROR_REG(id) ((((id) == ID_MT7531) || ((id) == ID_MT7988)) ? \ -- MT7531_CFC : MT7530_MFC) --#define MT753X_MIRROR_EN(id) ((((id) == ID_MT7531) || ((id) == ID_MT7988)) ? \ -- MT7531_MIRROR_EN : MIRROR_EN) --#define MT753X_MIRROR_MASK(id) ((((id) == ID_MT7531) || ((id) == ID_MT7988)) ? \ -- MT7531_MIRROR_MASK : MIRROR_MASK) -+#define MT753X_MIRROR_REG(id) ((id == ID_MT7531 || \ -+ id == ID_MT7988) ? \ -+ MT7531_CFC : MT753X_MFC) -+ -+#define MT753X_MIRROR_EN(id) ((id == ID_MT7531 || \ -+ id == ID_MT7988) ? \ -+ MT7531_MIRROR_EN : MT7530_MIRROR_EN) -+ -+#define MT753X_MIRROR_PORT_MASK(id) ((id == ID_MT7531 || \ -+ id == ID_MT7988) ? \ -+ MT7531_MIRROR_PORT_MASK : \ -+ MT7530_MIRROR_PORT_MASK) -+ -+#define MT753X_MIRROR_PORT_GET(id, val) ((id == ID_MT7531 || \ -+ id == ID_MT7988) ? \ -+ MT7531_MIRROR_PORT_GET(val) : \ -+ MT7530_MIRROR_PORT_GET(val)) -+ -+#define MT753X_MIRROR_PORT_SET(id, val) ((id == ID_MT7531 || \ -+ id == ID_MT7988) ? \ -+ MT7531_MIRROR_PORT_SET(val) : \ -+ MT7530_MIRROR_PORT_SET(val)) - - /* Register for BPDU and PAE frame control */ - #define MT753X_BPC 0x24 diff --git a/target/linux/generic/pending-6.1/795-06-net-dsa-mt7530-refactor-MT7530_HWTRAP-and-MT7530_MHW.patch b/target/linux/generic/pending-6.1/795-06-net-dsa-mt7530-refactor-MT7530_HWTRAP-and-MT7530_MHW.patch deleted file mode 100644 index d2497d5c90..0000000000 --- a/target/linux/generic/pending-6.1/795-06-net-dsa-mt7530-refactor-MT7530_HWTRAP-and-MT7530_MHW.patch +++ /dev/null @@ -1,257 +0,0 @@ -From 3ccf67597d35c06a7319e407b1c42f78a7966779 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= -Date: Mon, 22 Apr 2024 10:15:13 +0300 -Subject: [PATCH 06/15] net: dsa: mt7530: refactor MT7530_HWTRAP and - MT7530_MHWTRAP -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -The MT7530_HWTRAP and MT7530_MHWTRAP registers are on MT7530 and MT7531. -It's called hardware trap on MT7530, software trap on MT7531. That's -because some bits of the trap on MT7530 cannot be modified by software -whilst all bits of the trap on MT7531 can. Rename the definitions for them -to MT753X_TRAP and MT753X_MTRAP. Add MT7530 and MT7531 prefixes to the -definitions specific to the switch model. - -Remove the extra parentheses from MT7530_XTAL_40MHZ and MT7530_XTAL_20MHZ. - -Rename MHWTRAP_PHY0_SEL, MHWTRAP_MANUAL, and MHWTRAP_PHY_ACCESS to be on -par with the "MT7621 Giga Switch Programming Guide v0.3" document. - -Make an enumaration for the XTAL frequency. Set the data type of the xtal -variable on mt7531_pll_setup() to it. - -Signed-off-by: Arınç ÜNAL ---- - drivers/net/dsa/mt7530.c | 59 ++++++++++++++++++++-------------------- - drivers/net/dsa/mt7530.h | 50 ++++++++++++++++------------------ - 2 files changed, 54 insertions(+), 55 deletions(-) - ---- a/drivers/net/dsa/mt7530.c -+++ b/drivers/net/dsa/mt7530.c -@@ -403,23 +403,23 @@ mt7530_setup_port6(struct dsa_switch *ds - - mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK, P6_INTF_MODE(1)); - -- xtal = mt7530_read(priv, MT7530_MHWTRAP) & HWTRAP_XTAL_MASK; -+ xtal = mt7530_read(priv, MT753X_MTRAP) & MT7530_XTAL_MASK; - -- if (xtal == HWTRAP_XTAL_25MHZ) -+ if (xtal == MT7530_XTAL_25MHZ) - ssc_delta = 0x57; - else - ssc_delta = 0x87; - - if (priv->id == ID_MT7621) { - /* PLL frequency: 125MHz: 1.0GBit */ -- if (xtal == HWTRAP_XTAL_40MHZ) -+ if (xtal == MT7530_XTAL_40MHZ) - ncpo1 = 0x0640; -- if (xtal == HWTRAP_XTAL_25MHZ) -+ if (xtal == MT7530_XTAL_25MHZ) - ncpo1 = 0x0a00; - } else { /* PLL frequency: 250MHz: 2.0Gbit */ -- if (xtal == HWTRAP_XTAL_40MHZ) -+ if (xtal == MT7530_XTAL_40MHZ) - ncpo1 = 0x0c80; -- if (xtal == HWTRAP_XTAL_25MHZ) -+ if (xtal == MT7530_XTAL_25MHZ) - ncpo1 = 0x1400; - } - -@@ -442,19 +442,20 @@ mt7530_setup_port6(struct dsa_switch *ds - static void - mt7531_pll_setup(struct mt7530_priv *priv) - { -+ enum mt7531_xtal_fsel xtal; - u32 top_sig; - u32 hwstrap; -- u32 xtal; - u32 val; - - val = mt7530_read(priv, MT7531_CREV); - top_sig = mt7530_read(priv, MT7531_TOP_SIG_SR); -- hwstrap = mt7530_read(priv, MT7531_HWTRAP); -+ hwstrap = mt7530_read(priv, MT753X_TRAP); - if ((val & CHIP_REV_M) > 0) -- xtal = (top_sig & PAD_MCM_SMI_EN) ? HWTRAP_XTAL_FSEL_40MHZ : -- HWTRAP_XTAL_FSEL_25MHZ; -+ xtal = (top_sig & PAD_MCM_SMI_EN) ? MT7531_XTAL_FSEL_40MHZ : -+ MT7531_XTAL_FSEL_25MHZ; - else -- xtal = hwstrap & HWTRAP_XTAL_FSEL_MASK; -+ xtal = (hwstrap & MT7531_XTAL25) ? MT7531_XTAL_FSEL_25MHZ : -+ MT7531_XTAL_FSEL_40MHZ; - - /* Step 1 : Disable MT7531 COREPLL */ - val = mt7530_read(priv, MT7531_PLLGP_EN); -@@ -483,13 +484,13 @@ mt7531_pll_setup(struct mt7530_priv *pri - usleep_range(25, 35); - - switch (xtal) { -- case HWTRAP_XTAL_FSEL_25MHZ: -+ case MT7531_XTAL_FSEL_25MHZ: - val = mt7530_read(priv, MT7531_PLLGP_CR0); - val &= ~RG_COREPLL_SDM_PCW_M; - val |= 0x140000 << RG_COREPLL_SDM_PCW_S; - mt7530_write(priv, MT7531_PLLGP_CR0, val); - break; -- case HWTRAP_XTAL_FSEL_40MHZ: -+ case MT7531_XTAL_FSEL_40MHZ: - val = mt7530_read(priv, MT7531_PLLGP_CR0); - val &= ~RG_COREPLL_SDM_PCW_M; - val |= 0x190000 << RG_COREPLL_SDM_PCW_S; -@@ -870,20 +871,20 @@ static void mt7530_setup_port5(struct ds - - mutex_lock(&priv->reg_mutex); - -- val = mt7530_read(priv, MT7530_MHWTRAP); -+ val = mt7530_read(priv, MT753X_MTRAP); - -- val |= MHWTRAP_MANUAL | MHWTRAP_P5_MAC_SEL | MHWTRAP_P5_DIS; -- val &= ~MHWTRAP_P5_RGMII_MODE & ~MHWTRAP_PHY0_SEL; -+ val |= MT7530_CHG_TRAP | MT7530_P5_MAC_SEL | MT7530_P5_DIS; -+ val &= ~MT7530_P5_RGMII_MODE & ~MT7530_P5_PHY0_SEL; - - switch (priv->p5_mode) { - /* MUX_PHY_P0: P0 -> P5 -> SoC MAC */ - case MUX_PHY_P0: -- val |= MHWTRAP_PHY0_SEL; -+ val |= MT7530_P5_PHY0_SEL; - fallthrough; - - /* MUX_PHY_P4: P4 -> P5 -> SoC MAC */ - case MUX_PHY_P4: -- val &= ~MHWTRAP_P5_MAC_SEL & ~MHWTRAP_P5_DIS; -+ val &= ~MT7530_P5_MAC_SEL & ~MT7530_P5_DIS; - - /* Setup the MAC by default for the cpu port */ - mt7530_write(priv, MT753X_PMCR_P(5), 0x56300); -@@ -891,13 +892,13 @@ static void mt7530_setup_port5(struct ds - - /* GMAC5: P5 -> SoC MAC or external PHY */ - default: -- val &= ~MHWTRAP_P5_DIS; -+ val &= ~MT7530_P5_DIS; - break; - } - - /* Setup RGMII settings */ - if (phy_interface_mode_is_rgmii(interface)) { -- val |= MHWTRAP_P5_RGMII_MODE; -+ val |= MT7530_P5_RGMII_MODE; - - /* P5 RGMII RX Clock Control: delay setting for 1000M */ - mt7530_write(priv, MT7530_P5RGMIIRXCR, CSR_RGMII_EDGE_ALIGN); -@@ -917,7 +918,7 @@ static void mt7530_setup_port5(struct ds - P5_IO_CLK_DRV(1) | P5_IO_DATA_DRV(1)); - } - -- mt7530_write(priv, MT7530_MHWTRAP, val); -+ mt7530_write(priv, MT753X_MTRAP, val); - - dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, mode=%s, phy-mode=%s\n", val, - mt7530_p5_mode_str(priv->p5_mode), phy_modes(interface)); -@@ -2356,7 +2357,7 @@ mt7530_setup(struct dsa_switch *ds) - } - - /* Waiting for MT7530 got to stable */ -- INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP); -+ INIT_MT7530_DUMMY_POLL(&p, priv, MT753X_TRAP); - ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0, - 20, 1000000); - if (ret < 0) { -@@ -2371,7 +2372,7 @@ mt7530_setup(struct dsa_switch *ds) - return -ENODEV; - } - -- if ((val & HWTRAP_XTAL_MASK) == HWTRAP_XTAL_20MHZ) { -+ if ((val & MT7530_XTAL_MASK) == MT7530_XTAL_20MHZ) { - dev_err(priv->dev, - "MT7530 with a 20MHz XTAL is not supported!\n"); - return -EINVAL; -@@ -2392,12 +2393,12 @@ mt7530_setup(struct dsa_switch *ds) - RD_TAP_MASK, RD_TAP(16)); - - /* Enable port 6 */ -- val = mt7530_read(priv, MT7530_MHWTRAP); -- val &= ~MHWTRAP_P6_DIS & ~MHWTRAP_PHY_ACCESS; -- val |= MHWTRAP_MANUAL; -- mt7530_write(priv, MT7530_MHWTRAP, val); -+ val = mt7530_read(priv, MT753X_MTRAP); -+ val &= ~MT7530_P6_DIS & ~MT7530_PHY_INDIRECT_ACCESS; -+ val |= MT7530_CHG_TRAP; -+ mt7530_write(priv, MT753X_MTRAP, val); - -- if ((val & HWTRAP_XTAL_MASK) == HWTRAP_XTAL_40MHZ) -+ if ((val & MT7530_XTAL_MASK) == MT7530_XTAL_40MHZ) - mt7530_pll_setup(priv); - - mt753x_trap_frames(priv); -@@ -2577,7 +2578,7 @@ mt7531_setup(struct dsa_switch *ds) - } - - /* Waiting for MT7530 got to stable */ -- INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP); -+ INIT_MT7530_DUMMY_POLL(&p, priv, MT753X_TRAP); - ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0, - 20, 1000000); - if (ret < 0) { ---- a/drivers/net/dsa/mt7530.h -+++ b/drivers/net/dsa/mt7530.h -@@ -495,32 +495,30 @@ enum mt7531_clk_skew { - MT7531_CLK_SKEW_REVERSE = 3, - }; - --/* Register for hw trap status */ --#define MT7530_HWTRAP 0x7800 --#define HWTRAP_XTAL_MASK (BIT(10) | BIT(9)) --#define HWTRAP_XTAL_25MHZ (BIT(10) | BIT(9)) --#define HWTRAP_XTAL_40MHZ (BIT(10)) --#define HWTRAP_XTAL_20MHZ (BIT(9)) -+/* Register for trap status */ -+#define MT753X_TRAP 0x7800 -+#define MT7530_XTAL_MASK (BIT(10) | BIT(9)) -+#define MT7530_XTAL_25MHZ (BIT(10) | BIT(9)) -+#define MT7530_XTAL_40MHZ BIT(10) -+#define MT7530_XTAL_20MHZ BIT(9) -+#define MT7531_XTAL25 BIT(7) - --#define MT7531_HWTRAP 0x7800 --#define HWTRAP_XTAL_FSEL_MASK BIT(7) --#define HWTRAP_XTAL_FSEL_25MHZ BIT(7) --#define HWTRAP_XTAL_FSEL_40MHZ 0 --/* Unique fields of (M)HWSTRAP for MT7531 */ --#define XTAL_FSEL_S 7 --#define XTAL_FSEL_M BIT(7) --#define PHY_EN BIT(6) --#define CHG_STRAP BIT(8) -+/* Register for trap modification */ -+#define MT753X_MTRAP 0x7804 -+#define MT7530_P5_PHY0_SEL BIT(20) -+#define MT7530_CHG_TRAP BIT(16) -+#define MT7530_P5_MAC_SEL BIT(13) -+#define MT7530_P6_DIS BIT(8) -+#define MT7530_P5_RGMII_MODE BIT(7) -+#define MT7530_P5_DIS BIT(6) -+#define MT7530_PHY_INDIRECT_ACCESS BIT(5) -+#define MT7531_CHG_STRAP BIT(8) -+#define MT7531_PHY_EN BIT(6) - --/* Register for hw trap modification */ --#define MT7530_MHWTRAP 0x7804 --#define MHWTRAP_PHY0_SEL BIT(20) --#define MHWTRAP_MANUAL BIT(16) --#define MHWTRAP_P5_MAC_SEL BIT(13) --#define MHWTRAP_P6_DIS BIT(8) --#define MHWTRAP_P5_RGMII_MODE BIT(7) --#define MHWTRAP_P5_DIS BIT(6) --#define MHWTRAP_PHY_ACCESS BIT(5) -+enum mt7531_xtal_fsel { -+ MT7531_XTAL_FSEL_25MHZ, -+ MT7531_XTAL_FSEL_40MHZ, -+}; - - /* Register for TOP signal control */ - #define MT7530_TOP_SIG_CTRL 0x7808 diff --git a/target/linux/generic/pending-6.1/795-08-net-dsa-mt7530-return-mt7530_setup_mdio-mt7531_setup.patch b/target/linux/generic/pending-6.1/795-08-net-dsa-mt7530-return-mt7530_setup_mdio-mt7531_setup.patch deleted file mode 100644 index 5624a64599..0000000000 --- a/target/linux/generic/pending-6.1/795-08-net-dsa-mt7530-return-mt7530_setup_mdio-mt7531_setup.patch +++ /dev/null @@ -1,39 +0,0 @@ -From 1f5669efca65564c7533704917f79003c6b36c9c Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= -Date: Mon, 22 Apr 2024 10:15:15 +0300 -Subject: [PATCH 08/15] net: dsa: mt7530: return mt7530_setup_mdio & - mt7531_setup_common on error -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -The mt7530_setup_mdio() and mt7531_setup_common() functions should be -checked for errors. Return if the functions return a non-zero value. - -Signed-off-by: Arınç ÜNAL ---- - drivers/net/dsa/mt7530.c | 6 +++++- - 1 file changed, 5 insertions(+), 1 deletion(-) - ---- a/drivers/net/dsa/mt7530.c -+++ b/drivers/net/dsa/mt7530.c -@@ -2642,7 +2642,9 @@ mt7531_setup(struct dsa_switch *ds) - 0); - } - -- mt7531_setup_common(ds); -+ ret = mt7531_setup_common(ds); -+ if (ret) -+ return ret; - - /* Setup VLAN ID 0 for VLAN-unaware bridges */ - ret = mt7530_setup_vlan0(priv); -@@ -3001,6 +3003,8 @@ mt753x_setup(struct dsa_switch *ds) - ret = mt7530_setup_mdio(priv); - if (ret && priv->irq) - mt7530_free_irq_common(priv); -+ if (ret) -+ return ret; - - /* Initialise the PCS devices */ - for (i = 0; i < priv->ds->num_ports; i++) { diff --git a/target/linux/generic/pending-6.1/795-09-net-dsa-mt7530-define-MAC-speed-capabilities-per-swi.patch b/target/linux/generic/pending-6.1/795-09-net-dsa-mt7530-define-MAC-speed-capabilities-per-swi.patch deleted file mode 100644 index ed7923f9ee..0000000000 --- a/target/linux/generic/pending-6.1/795-09-net-dsa-mt7530-define-MAC-speed-capabilities-per-swi.patch +++ /dev/null @@ -1,75 +0,0 @@ -From 6cc2d4ccd77509df74b7b8ef46bbc6ba0a571318 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= -Date: Mon, 22 Apr 2024 10:15:16 +0300 -Subject: [PATCH 09/15] net: dsa: mt7530: define MAC speed capabilities per - switch model -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -With the support of the MT7988 SoC switch, the MAC speed capabilities -defined on mt753x_phylink_get_caps() won't apply to all switch models -anymore. Move them to more appropriate locations instead of overwriting -config->mac_capabilities. - -Remove the comment on mt753x_phylink_get_caps() as it's become invalid with -the support of MT7531 and MT7988 SoC switch. - -Add break to case 6 of mt7988_mac_port_get_caps() to be explicit. - -Signed-off-by: Arınç ÜNAL ---- - drivers/net/dsa/mt7530.c | 15 ++++++++++----- - 1 file changed, 10 insertions(+), 5 deletions(-) - ---- a/drivers/net/dsa/mt7530.c -+++ b/drivers/net/dsa/mt7530.c -@@ -2660,6 +2660,8 @@ mt7531_setup(struct dsa_switch *ds) - static void mt7530_mac_port_get_caps(struct dsa_switch *ds, int port, - struct phylink_config *config) - { -+ config->mac_capabilities |= MAC_10 | MAC_100 | MAC_1000FD; -+ - switch (port) { - /* Ports which are connected to switch PHYs. There is no MII pinout. */ - case 0 ... 4: -@@ -2691,6 +2693,8 @@ static void mt7531_mac_port_get_caps(str - { - struct mt7530_priv *priv = ds->priv; - -+ config->mac_capabilities |= MAC_10 | MAC_100 | MAC_1000FD; -+ - switch (port) { - /* Ports which are connected to switch PHYs. There is no MII pinout. */ - case 0 ... 4: -@@ -2730,14 +2734,17 @@ static void mt7988_mac_port_get_caps(str - case 0 ... 3: - __set_bit(PHY_INTERFACE_MODE_INTERNAL, - config->supported_interfaces); -+ -+ config->mac_capabilities |= MAC_10 | MAC_100 | MAC_1000FD; - break; - - /* Port 6 is connected to SoC's XGMII MAC. There is no MII pinout. */ - case 6: - __set_bit(PHY_INTERFACE_MODE_INTERNAL, - config->supported_interfaces); -- config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | -- MAC_10000FD; -+ -+ config->mac_capabilities |= MAC_10000FD; -+ break; - } - } - -@@ -2907,9 +2914,7 @@ static void mt753x_phylink_get_caps(stru - { - struct mt7530_priv *priv = ds->priv; - -- /* This switch only supports full-duplex at 1Gbps */ -- config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | -- MAC_10 | MAC_100 | MAC_1000FD; -+ config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE; - - /* This driver does not make use of the speed, duplex, pause or the - * advertisement in its mac_config, so it is safe to mark this driver diff --git a/target/linux/generic/pending-6.1/795-10-net-dsa-mt7530-get-rid-of-function-sanity-check.patch b/target/linux/generic/pending-6.1/795-10-net-dsa-mt7530-get-rid-of-function-sanity-check.patch deleted file mode 100644 index f674ab7c6b..0000000000 --- a/target/linux/generic/pending-6.1/795-10-net-dsa-mt7530-get-rid-of-function-sanity-check.patch +++ /dev/null @@ -1,33 +0,0 @@ -From dd0f15fc877c10567699190bce0f55e96f4ad6b5 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= -Date: Mon, 22 Apr 2024 10:15:17 +0300 -Subject: [PATCH 10/15] net: dsa: mt7530: get rid of function sanity check -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Get rid of checking whether functions are filled properly. priv->info which -is an mt753x_info structure is filled and checked for before this check. -It's unnecessary checking whether it's filled properly. - -Signed-off-by: Arınç ÜNAL ---- - drivers/net/dsa/mt7530.c | 7 ------- - 1 file changed, 7 deletions(-) - ---- a/drivers/net/dsa/mt7530.c -+++ b/drivers/net/dsa/mt7530.c -@@ -3204,13 +3204,6 @@ mt7530_probe_common(struct mt7530_priv * - if (!priv->info) - return -EINVAL; - -- /* Sanity check if these required device operations are filled -- * properly. -- */ -- if (!priv->info->sw_setup || !priv->info->phy_read || -- !priv->info->phy_write || !priv->info->mac_port_get_caps) -- return -EINVAL; -- - priv->id = priv->info->id; - priv->dev = dev; - priv->ds->priv = priv; diff --git a/target/linux/generic/pending-6.1/795-11-net-dsa-mt7530-refactor-MT7530_PMEEECR_P.patch b/target/linux/generic/pending-6.1/795-11-net-dsa-mt7530-refactor-MT7530_PMEEECR_P.patch deleted file mode 100644 index b1d08a74e3..0000000000 --- a/target/linux/generic/pending-6.1/795-11-net-dsa-mt7530-refactor-MT7530_PMEEECR_P.patch +++ /dev/null @@ -1,71 +0,0 @@ -From 2dff9759602b069f97ccc939e15a47ca051b2983 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= -Date: Mon, 22 Apr 2024 10:15:18 +0300 -Subject: [PATCH 11/15] net: dsa: mt7530: refactor MT7530_PMEEECR_P() -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -The MT7530_PMEEECR_P() register is on MT7530, MT7531, and the switch on the -MT7988 SoC. Rename the definition for them to MT753X_PMEEECR_P(). Use the -FIELD_PREP and FIELD_GET macros. Rename GET_LPI_THRESH() and -SET_LPI_THRESH() to LPI_THRESH_GET() and LPI_THRESH_SET(). - -Signed-off-by: Arınç ÜNAL ---- - drivers/net/dsa/mt7530.c | 8 ++++---- - drivers/net/dsa/mt7530.h | 13 +++++++------ - 2 files changed, 11 insertions(+), 10 deletions(-) - ---- a/drivers/net/dsa/mt7530.c -+++ b/drivers/net/dsa/mt7530.c -@@ -3032,10 +3032,10 @@ static int mt753x_get_mac_eee(struct dsa - struct ethtool_eee *e) - { - struct mt7530_priv *priv = ds->priv; -- u32 eeecr = mt7530_read(priv, MT7530_PMEEECR_P(port)); -+ u32 eeecr = mt7530_read(priv, MT753X_PMEEECR_P(port)); - - e->tx_lpi_enabled = !(eeecr & LPI_MODE_EN); -- e->tx_lpi_timer = GET_LPI_THRESH(eeecr); -+ e->tx_lpi_timer = LPI_THRESH_GET(eeecr); - - return 0; - } -@@ -3049,11 +3049,11 @@ static int mt753x_set_mac_eee(struct dsa - if (e->tx_lpi_timer > 0xFFF) - return -EINVAL; - -- set = SET_LPI_THRESH(e->tx_lpi_timer); -+ set = LPI_THRESH_SET(e->tx_lpi_timer); - if (!e->tx_lpi_enabled) - /* Force LPI Mode without a delay */ - set |= LPI_MODE_EN; -- mt7530_rmw(priv, MT7530_PMEEECR_P(port), mask, set); -+ mt7530_rmw(priv, MT753X_PMEEECR_P(port), mask, set); - - return 0; - } ---- a/drivers/net/dsa/mt7530.h -+++ b/drivers/net/dsa/mt7530.h -@@ -364,13 +364,14 @@ enum mt7530_vlan_port_acc_frm { - PMCR_FORCE_SPEED_100 | \ - PMCR_FORCE_FDX | PMCR_FORCE_LNK) - --#define MT7530_PMEEECR_P(x) (0x3004 + (x) * 0x100) --#define WAKEUP_TIME_1000(x) (((x) & 0xFF) << 24) --#define WAKEUP_TIME_100(x) (((x) & 0xFF) << 16) -+#define MT753X_PMEEECR_P(x) (0x3004 + (x) * 0x100) -+#define WAKEUP_TIME_1000_MASK GENMASK(31, 24) -+#define WAKEUP_TIME_1000(x) FIELD_PREP(WAKEUP_TIME_1000_MASK, x) -+#define WAKEUP_TIME_100_MASK GENMASK(23, 16) -+#define WAKEUP_TIME_100(x) FIELD_PREP(WAKEUP_TIME_100_MASK, x) - #define LPI_THRESH_MASK GENMASK(15, 4) --#define LPI_THRESH_SHT 4 --#define SET_LPI_THRESH(x) (((x) << LPI_THRESH_SHT) & LPI_THRESH_MASK) --#define GET_LPI_THRESH(x) (((x) & LPI_THRESH_MASK) >> LPI_THRESH_SHT) -+#define LPI_THRESH_GET(x) FIELD_GET(LPI_THRESH_MASK, x) -+#define LPI_THRESH_SET(x) FIELD_PREP(LPI_THRESH_MASK, x) - #define LPI_MODE_EN BIT(0) - - #define MT7530_PMSR_P(x) (0x3008 + (x) * 0x100) diff --git a/target/linux/generic/pending-6.1/795-12-net-dsa-mt7530-get-rid-of-mac_port_validate-member-o.patch b/target/linux/generic/pending-6.1/795-12-net-dsa-mt7530-get-rid-of-mac_port_validate-member-o.patch deleted file mode 100644 index 7ce2d4c04e..0000000000 --- a/target/linux/generic/pending-6.1/795-12-net-dsa-mt7530-get-rid-of-mac_port_validate-member-o.patch +++ /dev/null @@ -1,46 +0,0 @@ -From 21d67c2fabfe40baf33202d3287b67b6c16f8382 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= -Date: Mon, 22 Apr 2024 10:15:19 +0300 -Subject: [PATCH 12/15] net: dsa: mt7530: get rid of mac_port_validate member - of mt753x_info -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -The mac_port_validate member of the mt753x_info structure is not being -used, remove it. Improve the member description section in the process. - -Signed-off-by: Arınç ÜNAL ---- - drivers/net/dsa/mt7530.h | 10 +++------- - 1 file changed, 3 insertions(+), 7 deletions(-) - ---- a/drivers/net/dsa/mt7530.h -+++ b/drivers/net/dsa/mt7530.h -@@ -743,13 +743,12 @@ struct mt753x_pcs { - - /* struct mt753x_info - This is the main data structure for holding the specific - * part for each supported device -+ * @id: Holding the identifier to a switch model -+ * @pcs_ops: Holding the pointer to the MAC PCS operations structure - * @sw_setup: Holding the handler to a device initialization - * @phy_read: Holding the way reading PHY port - * @phy_write: Holding the way writing PHY port -- * @phy_mode_supported: Check if the PHY type is being supported on a certain -- * port -- * @mac_port_validate: Holding the way to set addition validate type for a -- * certan MAC port -+ * @mac_port_get_caps: Holding the handler that provides MAC capabilities - * @mac_port_config: Holding the way setting up the PHY attribute to a - * certain MAC port - */ -@@ -763,9 +762,6 @@ struct mt753x_info { - int (*phy_write)(struct mt7530_priv *priv, int port, int regnum, u16 val); - void (*mac_port_get_caps)(struct dsa_switch *ds, int port, - struct phylink_config *config); -- void (*mac_port_validate)(struct dsa_switch *ds, int port, -- phy_interface_t interface, -- unsigned long *supported); - void (*mac_port_config)(struct dsa_switch *ds, int port, - unsigned int mode, - phy_interface_t interface); diff --git a/target/linux/generic/pending-6.1/795-13-net-dsa-mt7530-use-priv-ds-num_ports-instead-of-MT75.patch b/target/linux/generic/pending-6.1/795-13-net-dsa-mt7530-use-priv-ds-num_ports-instead-of-MT75.patch deleted file mode 100644 index ce75556791..0000000000 --- a/target/linux/generic/pending-6.1/795-13-net-dsa-mt7530-use-priv-ds-num_ports-instead-of-MT75.patch +++ /dev/null @@ -1,57 +0,0 @@ -From 6efc8ae3eb0363328f479191a0cf0dc12a16e090 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= -Date: Mon, 22 Apr 2024 10:15:20 +0300 -Subject: [PATCH 13/15] net: dsa: mt7530: use priv->ds->num_ports instead of - MT7530_NUM_PORTS -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Use priv->ds->num_ports on all for loops which configure the switch -registers. In the future, the value of MT7530_NUM_PORTS will depend on -priv->id. Therefore, this change prepares the subdriver for a simpler -implementation. - -Signed-off-by: Arınç ÜNAL ---- - drivers/net/dsa/mt7530.c | 8 ++++---- - 1 file changed, 4 insertions(+), 4 deletions(-) - ---- a/drivers/net/dsa/mt7530.c -+++ b/drivers/net/dsa/mt7530.c -@@ -1391,7 +1391,7 @@ mt7530_port_set_vlan_unaware(struct dsa_ - mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, - G0_PORT_VID_DEF); - -- for (i = 0; i < MT7530_NUM_PORTS; i++) { -+ for (i = 0; i < priv->ds->num_ports; i++) { - if (dsa_is_user_port(ds, i) && - dsa_port_is_vlan_filtering(dsa_to_port(ds, i))) { - all_user_ports_removed = false; -@@ -2406,7 +2406,7 @@ mt7530_setup(struct dsa_switch *ds) - /* Enable and reset MIB counters */ - mt7530_mib_reset(ds); - -- for (i = 0; i < MT7530_NUM_PORTS; i++) { -+ for (i = 0; i < priv->ds->num_ports; i++) { - /* Clear link settings and enable force mode to force link down - * on all ports until they're enabled later. - */ -@@ -2514,7 +2514,7 @@ mt7531_setup_common(struct dsa_switch *d - mt7530_clear(priv, MT753X_MFC, BC_FFP_MASK | UNM_FFP_MASK | - UNU_FFP_MASK); - -- for (i = 0; i < MT7530_NUM_PORTS; i++) { -+ for (i = 0; i < priv->ds->num_ports; i++) { - /* Clear link settings and enable force mode to force link down - * on all ports until they're enabled later. - */ -@@ -2601,7 +2601,7 @@ mt7531_setup(struct dsa_switch *ds) - priv->p5_sgmii = !!(val & PAD_DUAL_SGMII_EN); - - /* Force link down on all ports before internal reset */ -- for (i = 0; i < MT7530_NUM_PORTS; i++) -+ for (i = 0; i < priv->ds->num_ports; i++) - mt7530_write(priv, MT753X_PMCR_P(i), MT7531_FORCE_MODE_LNK); - - /* Reset the switch through internal reset */ diff --git a/target/linux/generic/pending-6.1/795-14-net-dsa-mt7530-do-not-pass-port-variable-to-mt7531_r.patch b/target/linux/generic/pending-6.1/795-14-net-dsa-mt7530-do-not-pass-port-variable-to-mt7531_r.patch deleted file mode 100644 index e12d084c2f..0000000000 --- a/target/linux/generic/pending-6.1/795-14-net-dsa-mt7530-do-not-pass-port-variable-to-mt7531_r.patch +++ /dev/null @@ -1,37 +0,0 @@ -From 4794c12e3aefe05dd0063c2b6b0101854b143bac Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= -Date: Mon, 22 Apr 2024 10:15:21 +0300 -Subject: [PATCH 14/15] net: dsa: mt7530: do not pass port variable to - mt7531_rgmii_setup() -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -The mt7531_rgmii_setup() function does not use the port variable, do not -pass the variable to it. - -Signed-off-by: Arınç ÜNAL ---- - drivers/net/dsa/mt7530.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/net/dsa/mt7530.c -+++ b/drivers/net/dsa/mt7530.c -@@ -2760,7 +2760,7 @@ mt7530_mac_config(struct dsa_switch *ds, - mt7530_setup_port6(priv->ds, interface); - } - --static void mt7531_rgmii_setup(struct mt7530_priv *priv, u32 port, -+static void mt7531_rgmii_setup(struct mt7530_priv *priv, - phy_interface_t interface, - struct phy_device *phydev) - { -@@ -2811,7 +2811,7 @@ mt7531_mac_config(struct dsa_switch *ds, - if (phy_interface_mode_is_rgmii(interface)) { - dp = dsa_to_port(ds, port); - phydev = dp->slave->phydev; -- mt7531_rgmii_setup(priv, port, interface, phydev); -+ mt7531_rgmii_setup(priv, interface, phydev); - } - } - diff --git a/target/linux/generic/pending-6.1/795-15-net-dsa-mt7530-explain-exposing-MDIO-bus-of-MT7531AE.patch b/target/linux/generic/pending-6.1/795-15-net-dsa-mt7530-explain-exposing-MDIO-bus-of-MT7531AE.patch deleted file mode 100644 index 0eaf4fc2e8..0000000000 --- a/target/linux/generic/pending-6.1/795-15-net-dsa-mt7530-explain-exposing-MDIO-bus-of-MT7531AE.patch +++ /dev/null @@ -1,33 +0,0 @@ -From c45832fe783f468aaaace09ae95a30cbf0acf724 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= -Date: Mon, 22 Apr 2024 10:15:22 +0300 -Subject: [PATCH 15/15] net: dsa: mt7530: explain exposing MDIO bus of MT7531AE - better -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Unlike MT7531BE, the GPIO 6-12 pins are not used for RGMII on MT7531AE. -Therefore, the GPIO 11-12 pins are set to function as MDC and MDIO to -expose the MDIO bus of the switch. Replace the comment with a better -explanation. - -Signed-off-by: Arınç ÜNAL ---- - drivers/net/dsa/mt7530.c | 5 ++++- - 1 file changed, 4 insertions(+), 1 deletion(-) - ---- a/drivers/net/dsa/mt7530.c -+++ b/drivers/net/dsa/mt7530.c -@@ -2610,7 +2610,10 @@ mt7531_setup(struct dsa_switch *ds) - if (!priv->p5_sgmii) { - mt7531_pll_setup(priv); - } else { -- /* Let ds->slave_mii_bus be able to access external phy. */ -+ /* Unlike MT7531BE, the GPIO 6-12 pins are not used for RGMII on -+ * MT7531AE. Set the GPIO 11-12 pins to function as MDC and MDIO -+ * to expose the MDIO bus of the switch. -+ */ - mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO11_RG_RXD2_MASK, - MT7531_EXT_P_MDC_11); - mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO12_RG_RXD3_MASK, diff --git a/target/linux/generic/pending-6.6/745-01-net-dsa-mt7530-disable-EEE-abilities-on-failure-on-M.patch b/target/linux/generic/pending-6.6/745-01-net-dsa-mt7530-disable-EEE-abilities-on-failure-on-M.patch deleted file mode 100644 index 44cf60cf14..0000000000 --- a/target/linux/generic/pending-6.6/745-01-net-dsa-mt7530-disable-EEE-abilities-on-failure-on-M.patch +++ /dev/null @@ -1,88 +0,0 @@ -From 856e8954a0a88d1a4d2b43e9002b9249131a156f Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= -Date: Mon, 22 Apr 2024 10:15:08 +0300 -Subject: [PATCH 01/15] net: dsa: mt7530: disable EEE abilities on failure on - MT7531 and MT7988 -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -The MT7531_FORCE_EEE1G and MT7531_FORCE_EEE100 bits let the -PMCR_FORCE_EEE1G and PMCR_FORCE_EEE100 bits determine the 1G/100 EEE -abilities of the MAC. If MT7531_FORCE_EEE1G and MT7531_FORCE_EEE100 are -unset, the abilities are left to be determined by PHY auto polling. - -The commit 40b5d2f15c09 ("net: dsa: mt7530: Add support for EEE features") -made it so that the PMCR_FORCE_EEE1G and PMCR_FORCE_EEE100 bits are set on -mt753x_phylink_mac_link_up(). But it did not set the MT7531_FORCE_EEE1G and -MT7531_FORCE_EEE100 bits. Because of this, the EEE abilities will be -determined by PHY auto polling, regardless of the result of phy_init_eee(). - -Define these bits and add them to the MT7531_FORCE_MODE mask which is set -in mt7531_setup_common(). With this, there won't be any EEE abilities set -when phy_init_eee() returns a negative value. - -Thanks to Russell for explaining when phy_init_eee() could return a -negative value below. - -Looking at phy_init_eee(), it could return a negative value when: - -1. phydev->drv is NULL -2. if genphy_c45_eee_is_active() returns negative -3. if genphy_c45_eee_is_active() returns zero, it returns -EPROTONOSUPPORT -4. if phy_set_bits_mmd() fails (e.g. communication error with the PHY) - -If we then look at genphy_c45_eee_is_active(), then: - -genphy_c45_read_eee_adv() and genphy_c45_read_eee_lpa() propagate their -non-zero return values, otherwise this function returns zero or positive -integer. - -If we then look at genphy_c45_read_eee_adv(), then a failure of -phy_read_mmd() would cause a negative value to be returned. - -Looking at genphy_c45_read_eee_lpa(), the same is true. - -So, it can be summarised as: - -- phydev->drv is NULL -- there is a communication error accessing the PHY -- EEE is not active - -otherwise, it returns zero on success. - -If one wishes to determine whether an error occurred vs EEE not being -supported through negotiation for the negotiated speed, if it returns --EPROTONOSUPPORT in the latter case. Other error codes mean either the -driver has been unloaded or communication error. - -In conclusion, determining the EEE abilities by PHY auto polling shouldn't -result in having any EEE abilities enabled, when one of the last two -situations in the summary happens. And it seems that if phydev->drv is -NULL, there would be bigger problems with the device than a broken link. So -this is not a bugfix. - -Signed-off-by: Arınç ÜNAL ---- - drivers/net/dsa/mt7530.h | 6 +++++- - 1 file changed, 5 insertions(+), 1 deletion(-) - ---- a/drivers/net/dsa/mt7530.h -+++ b/drivers/net/dsa/mt7530.h -@@ -328,11 +328,15 @@ enum mt7530_vlan_port_acc_frm { - #define MT7531_FORCE_DPX BIT(29) - #define MT7531_FORCE_RX_FC BIT(28) - #define MT7531_FORCE_TX_FC BIT(27) -+#define MT7531_FORCE_EEE100 BIT(26) -+#define MT7531_FORCE_EEE1G BIT(25) - #define MT7531_FORCE_MODE (MT7531_FORCE_LNK | \ - MT7531_FORCE_SPD | \ - MT7531_FORCE_DPX | \ - MT7531_FORCE_RX_FC | \ -- MT7531_FORCE_TX_FC) -+ MT7531_FORCE_TX_FC | \ -+ MT7531_FORCE_EEE100 | \ -+ MT7531_FORCE_EEE1G) - #define PMCR_LINK_SETTINGS_MASK (PMCR_TX_EN | PMCR_FORCE_SPEED_1000 | \ - PMCR_RX_EN | PMCR_FORCE_SPEED_100 | \ - PMCR_TX_FC_EN | PMCR_RX_FC_EN | \ diff --git a/target/linux/generic/pending-6.6/745-02-net-dsa-mt7530-refactor-MT7530_PMCR_P.patch b/target/linux/generic/pending-6.6/745-02-net-dsa-mt7530-refactor-MT7530_PMCR_P.patch deleted file mode 100644 index 89fad45dd5..0000000000 --- a/target/linux/generic/pending-6.6/745-02-net-dsa-mt7530-refactor-MT7530_PMCR_P.patch +++ /dev/null @@ -1,200 +0,0 @@ -From 712ad00d2f43814c81a7abfcbc339690a05fb6a0 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= -Date: Mon, 22 Apr 2024 10:15:09 +0300 -Subject: [PATCH 02/15] net: dsa: mt7530: refactor MT7530_PMCR_P() -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -The MT7530_PMCR_P() registers are on MT7530, MT7531, and the switch on the -MT7988 SoC. Rename the definition for them to MT753X_PMCR_P(). Bit 15 is -for MT7530 only. Add MT7530 prefix to the definition for bit 15. - -Use GENMASK and FIELD_PREP for PMCR_IFG_XMIT(). - -Rename PMCR_TX_EN and PMCR_RX_EN to PMCR_MAC_TX_EN and PMCR_MAC_TX_EN to -follow the naming on the "MT7621 Giga Switch Programming Guide v0.3", -"MT7531 Reference Manual for Development Board v1.0", and "MT7988A Wi-Fi 7 -Generation Router Platform: Datasheet (Open Version) v0.1" documents. - -These documents show that PMCR_RX_FC_EN is at bit 5. Correct this along -with renaming it to PMCR_FORCE_RX_FC_EN, and the same for PMCR_TX_FC_EN. - -Remove PMCR_SPEED_MASK which doesn't have a use. - -Rename the force mode definitions for MT7531 to FORCE_MODE. Add MASK at the -end for the mask that includes all force mode definitions. - -Signed-off-by: Arınç ÜNAL ---- - drivers/net/dsa/mt7530.c | 24 ++++++++--------- - drivers/net/dsa/mt7530.h | 58 +++++++++++++++++++++------------------- - 2 files changed, 42 insertions(+), 40 deletions(-) - ---- a/drivers/net/dsa/mt7530.c -+++ b/drivers/net/dsa/mt7530.c -@@ -896,7 +896,7 @@ static void mt7530_setup_port5(struct ds - val &= ~MHWTRAP_P5_MAC_SEL & ~MHWTRAP_P5_DIS; - - /* Setup the MAC by default for the cpu port */ -- mt7530_write(priv, MT7530_PMCR_P(5), 0x56300); -+ mt7530_write(priv, MT753X_PMCR_P(5), 0x56300); - break; - case P5_INTF_SEL_GMAC5: - /* MT7530_P5_MODE_GMAC: P5 -> External phy or 2nd GMAC */ -@@ -2444,8 +2444,8 @@ mt7530_setup(struct dsa_switch *ds) - /* Clear link settings and enable force mode to force link down - * on all ports until they're enabled later. - */ -- mt7530_rmw(priv, MT7530_PMCR_P(i), PMCR_LINK_SETTINGS_MASK | -- PMCR_FORCE_MODE, PMCR_FORCE_MODE); -+ mt7530_rmw(priv, MT753X_PMCR_P(i), PMCR_LINK_SETTINGS_MASK | -+ MT7530_FORCE_MODE, MT7530_FORCE_MODE); - - /* Disable forwarding by default on all ports */ - mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK, -@@ -2555,8 +2555,8 @@ mt7531_setup_common(struct dsa_switch *d - /* Clear link settings and enable force mode to force link down - * on all ports until they're enabled later. - */ -- mt7530_rmw(priv, MT7530_PMCR_P(i), PMCR_LINK_SETTINGS_MASK | -- MT7531_FORCE_MODE, MT7531_FORCE_MODE); -+ mt7530_rmw(priv, MT753X_PMCR_P(i), PMCR_LINK_SETTINGS_MASK | -+ MT7531_FORCE_MODE_MASK, MT7531_FORCE_MODE_MASK); - - /* Disable forwarding by default on all ports */ - mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK, -@@ -2639,7 +2639,7 @@ mt7531_setup(struct dsa_switch *ds) - - /* Force link down on all ports before internal reset */ - for (i = 0; i < MT7530_NUM_PORTS; i++) -- mt7530_write(priv, MT7530_PMCR_P(i), MT7531_FORCE_LNK); -+ mt7530_write(priv, MT753X_PMCR_P(i), MT7531_FORCE_MODE_LNK); - - /* Reset the switch through internal reset */ - mt7530_write(priv, MT7530_SYS_CTRL, SYS_CTRL_SW_RST | SYS_CTRL_REG_RST); -@@ -2881,7 +2881,7 @@ mt753x_phylink_mac_config(struct phylink - - /* Are we connected to external phy */ - if (port == 5 && dsa_is_user_port(ds, 5)) -- mt7530_set(priv, MT7530_PMCR_P(port), PMCR_EXT_PHY); -+ mt7530_set(priv, MT753X_PMCR_P(port), PMCR_EXT_PHY); - } - - static void mt753x_phylink_mac_link_down(struct phylink_config *config, -@@ -2891,7 +2891,7 @@ static void mt753x_phylink_mac_link_down - struct dsa_port *dp = dsa_phylink_to_port(config); - struct mt7530_priv *priv = dp->ds->priv; - -- mt7530_clear(priv, MT7530_PMCR_P(dp->index), PMCR_LINK_SETTINGS_MASK); -+ mt7530_clear(priv, MT753X_PMCR_P(dp->index), PMCR_LINK_SETTINGS_MASK); - } - - static void mt753x_phylink_mac_link_up(struct phylink_config *config, -@@ -2905,7 +2905,7 @@ static void mt753x_phylink_mac_link_up(s - struct mt7530_priv *priv = dp->ds->priv; - u32 mcr; - -- mcr = PMCR_RX_EN | PMCR_TX_EN | PMCR_FORCE_LNK; -+ mcr = PMCR_MAC_RX_EN | PMCR_MAC_TX_EN | PMCR_FORCE_LNK; - - switch (speed) { - case SPEED_1000: -@@ -2920,9 +2920,9 @@ static void mt753x_phylink_mac_link_up(s - if (duplex == DUPLEX_FULL) { - mcr |= PMCR_FORCE_FDX; - if (tx_pause) -- mcr |= PMCR_TX_FC_EN; -+ mcr |= PMCR_FORCE_TX_FC_EN; - if (rx_pause) -- mcr |= PMCR_RX_FC_EN; -+ mcr |= PMCR_FORCE_RX_FC_EN; - } - - if (mode == MLO_AN_PHY && phydev && phy_init_eee(phydev, false) >= 0) { -@@ -2937,7 +2937,7 @@ static void mt753x_phylink_mac_link_up(s - } - } - -- mt7530_set(priv, MT7530_PMCR_P(dp->index), mcr); -+ mt7530_set(priv, MT753X_PMCR_P(dp->index), mcr); - } - - static void mt753x_phylink_get_caps(struct dsa_switch *ds, int port, ---- a/drivers/net/dsa/mt7530.h -+++ b/drivers/net/dsa/mt7530.h -@@ -304,44 +304,46 @@ enum mt7530_vlan_port_acc_frm { - #define G0_PORT_VID_DEF G0_PORT_VID(0) - - /* Register for port MAC control register */ --#define MT7530_PMCR_P(x) (0x3000 + ((x) * 0x100)) --#define PMCR_IFG_XMIT(x) (((x) & 0x3) << 18) -+#define MT753X_PMCR_P(x) (0x3000 + ((x) * 0x100)) -+#define PMCR_IFG_XMIT_MASK GENMASK(19, 18) -+#define PMCR_IFG_XMIT(x) FIELD_PREP(PMCR_IFG_XMIT_MASK, x) - #define PMCR_EXT_PHY BIT(17) - #define PMCR_MAC_MODE BIT(16) --#define PMCR_FORCE_MODE BIT(15) --#define PMCR_TX_EN BIT(14) --#define PMCR_RX_EN BIT(13) -+#define MT7530_FORCE_MODE BIT(15) -+#define PMCR_MAC_TX_EN BIT(14) -+#define PMCR_MAC_RX_EN BIT(13) - #define PMCR_BACKOFF_EN BIT(9) - #define PMCR_BACKPR_EN BIT(8) - #define PMCR_FORCE_EEE1G BIT(7) - #define PMCR_FORCE_EEE100 BIT(6) --#define PMCR_TX_FC_EN BIT(5) --#define PMCR_RX_FC_EN BIT(4) -+#define PMCR_FORCE_RX_FC_EN BIT(5) -+#define PMCR_FORCE_TX_FC_EN BIT(4) - #define PMCR_FORCE_SPEED_1000 BIT(3) - #define PMCR_FORCE_SPEED_100 BIT(2) - #define PMCR_FORCE_FDX BIT(1) - #define PMCR_FORCE_LNK BIT(0) --#define PMCR_SPEED_MASK (PMCR_FORCE_SPEED_100 | \ -- PMCR_FORCE_SPEED_1000) --#define MT7531_FORCE_LNK BIT(31) --#define MT7531_FORCE_SPD BIT(30) --#define MT7531_FORCE_DPX BIT(29) --#define MT7531_FORCE_RX_FC BIT(28) --#define MT7531_FORCE_TX_FC BIT(27) --#define MT7531_FORCE_EEE100 BIT(26) --#define MT7531_FORCE_EEE1G BIT(25) --#define MT7531_FORCE_MODE (MT7531_FORCE_LNK | \ -- MT7531_FORCE_SPD | \ -- MT7531_FORCE_DPX | \ -- MT7531_FORCE_RX_FC | \ -- MT7531_FORCE_TX_FC | \ -- MT7531_FORCE_EEE100 | \ -- MT7531_FORCE_EEE1G) --#define PMCR_LINK_SETTINGS_MASK (PMCR_TX_EN | PMCR_FORCE_SPEED_1000 | \ -- PMCR_RX_EN | PMCR_FORCE_SPEED_100 | \ -- PMCR_TX_FC_EN | PMCR_RX_FC_EN | \ -- PMCR_FORCE_FDX | PMCR_FORCE_LNK | \ -- PMCR_FORCE_EEE1G | PMCR_FORCE_EEE100) -+#define MT7531_FORCE_MODE_LNK BIT(31) -+#define MT7531_FORCE_MODE_SPD BIT(30) -+#define MT7531_FORCE_MODE_DPX BIT(29) -+#define MT7531_FORCE_MODE_RX_FC BIT(28) -+#define MT7531_FORCE_MODE_TX_FC BIT(27) -+#define MT7531_FORCE_MODE_EEE100 BIT(26) -+#define MT7531_FORCE_MODE_EEE1G BIT(25) -+#define MT7531_FORCE_MODE_MASK (MT7531_FORCE_MODE_LNK | \ -+ MT7531_FORCE_MODE_SPD | \ -+ MT7531_FORCE_MODE_DPX | \ -+ MT7531_FORCE_MODE_RX_FC | \ -+ MT7531_FORCE_MODE_TX_FC | \ -+ MT7531_FORCE_MODE_EEE100 | \ -+ MT7531_FORCE_MODE_EEE1G) -+#define PMCR_LINK_SETTINGS_MASK (PMCR_MAC_TX_EN | PMCR_MAC_RX_EN | \ -+ PMCR_FORCE_EEE1G | \ -+ PMCR_FORCE_EEE100 | \ -+ PMCR_FORCE_RX_FC_EN | \ -+ PMCR_FORCE_TX_FC_EN | \ -+ PMCR_FORCE_SPEED_1000 | \ -+ PMCR_FORCE_SPEED_100 | \ -+ PMCR_FORCE_FDX | PMCR_FORCE_LNK) - - #define MT7530_PMEEECR_P(x) (0x3004 + (x) * 0x100) - #define WAKEUP_TIME_1000(x) (((x) & 0xFF) << 24) diff --git a/target/linux/generic/pending-6.6/745-03-net-dsa-mt7530-rename-p5_intf_sel-and-use-only-for-M.patch b/target/linux/generic/pending-6.6/745-03-net-dsa-mt7530-rename-p5_intf_sel-and-use-only-for-M.patch deleted file mode 100644 index 601171a594..0000000000 --- a/target/linux/generic/pending-6.6/745-03-net-dsa-mt7530-rename-p5_intf_sel-and-use-only-for-M.patch +++ /dev/null @@ -1,185 +0,0 @@ -From 875ec5b67ab88e969b171e6e9ea803e3ed759614 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= -Date: Mon, 22 Apr 2024 10:15:10 +0300 -Subject: [PATCH 03/15] net: dsa: mt7530: rename p5_intf_sel and use only for - MT7530 switch -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -The p5_intf_sel pointer is used to store the information of whether PHY -muxing is used or not. PHY muxing is a feature specific to port 5 of the -MT7530 switch. Do not use it for other switch models. - -Rename the pointer to p5_mode to store the mode the port is being used in. -Rename the p5_interface_select enum to mt7530_p5_mode, the string -representation to mt7530_p5_mode_str, and the enum elements. - -If PHY muxing is not detected, the default mode, GMAC5, will be used. - -Signed-off-by: Arınç ÜNAL ---- - drivers/net/dsa/mt7530.c | 62 +++++++++++++++++----------------------- - drivers/net/dsa/mt7530.h | 15 +++++----- - 2 files changed, 33 insertions(+), 44 deletions(-) - ---- a/drivers/net/dsa/mt7530.c -+++ b/drivers/net/dsa/mt7530.c -@@ -857,19 +857,15 @@ mt7530_set_ageing_time(struct dsa_switch - return 0; - } - --static const char *p5_intf_modes(unsigned int p5_interface) -+static const char *mt7530_p5_mode_str(unsigned int mode) - { -- switch (p5_interface) { -- case P5_DISABLED: -- return "DISABLED"; -- case P5_INTF_SEL_PHY_P0: -- return "PHY P0"; -- case P5_INTF_SEL_PHY_P4: -- return "PHY P4"; -- case P5_INTF_SEL_GMAC5: -- return "GMAC5"; -+ switch (mode) { -+ case MUX_PHY_P0: -+ return "MUX PHY P0"; -+ case MUX_PHY_P4: -+ return "MUX PHY P4"; - default: -- return "unknown"; -+ return "GMAC5"; - } - } - -@@ -886,23 +882,23 @@ static void mt7530_setup_port5(struct ds - val |= MHWTRAP_MANUAL | MHWTRAP_P5_MAC_SEL | MHWTRAP_P5_DIS; - val &= ~MHWTRAP_P5_RGMII_MODE & ~MHWTRAP_PHY0_SEL; - -- switch (priv->p5_intf_sel) { -- case P5_INTF_SEL_PHY_P0: -- /* MT7530_P5_MODE_GPHY_P0: 2nd GMAC -> P5 -> P0 */ -+ switch (priv->p5_mode) { -+ /* MUX_PHY_P0: P0 -> P5 -> SoC MAC */ -+ case MUX_PHY_P0: - val |= MHWTRAP_PHY0_SEL; - fallthrough; -- case P5_INTF_SEL_PHY_P4: -- /* MT7530_P5_MODE_GPHY_P4: 2nd GMAC -> P5 -> P4 */ -+ -+ /* MUX_PHY_P4: P4 -> P5 -> SoC MAC */ -+ case MUX_PHY_P4: - val &= ~MHWTRAP_P5_MAC_SEL & ~MHWTRAP_P5_DIS; - - /* Setup the MAC by default for the cpu port */ - mt7530_write(priv, MT753X_PMCR_P(5), 0x56300); - break; -- case P5_INTF_SEL_GMAC5: -- /* MT7530_P5_MODE_GMAC: P5 -> External phy or 2nd GMAC */ -- val &= ~MHWTRAP_P5_DIS; -- break; -+ -+ /* GMAC5: P5 -> SoC MAC or external PHY */ - default: -+ val &= ~MHWTRAP_P5_DIS; - break; - } - -@@ -930,8 +926,8 @@ static void mt7530_setup_port5(struct ds - - mt7530_write(priv, MT7530_MHWTRAP, val); - -- dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, intf_sel=%s, phy-mode=%s\n", -- val, p5_intf_modes(priv->p5_intf_sel), phy_modes(interface)); -+ dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, mode=%s, phy-mode=%s\n", val, -+ mt7530_p5_mode_str(priv->p5_mode), phy_modes(interface)); - - mutex_unlock(&priv->reg_mutex); - } -@@ -2476,13 +2472,11 @@ mt7530_setup(struct dsa_switch *ds) - if (ret) - return ret; - -- /* Setup port 5 */ -- if (!dsa_is_unused_port(ds, 5)) { -- priv->p5_intf_sel = P5_INTF_SEL_GMAC5; -- } else { -+ /* Check for PHY muxing on port 5 */ -+ if (dsa_is_unused_port(ds, 5)) { - /* Scan the ethernet nodes. Look for GMAC1, lookup the used PHY. -- * Set priv->p5_intf_sel to the appropriate value if PHY muxing -- * is detected. -+ * Set priv->p5_mode to the appropriate value if PHY muxing is -+ * detected. - */ - for_each_child_of_node(dn, mac_np) { - if (!of_device_is_compatible(mac_np, -@@ -2506,17 +2500,16 @@ mt7530_setup(struct dsa_switch *ds) - } - id = of_mdio_parse_addr(ds->dev, phy_node); - if (id == 0) -- priv->p5_intf_sel = P5_INTF_SEL_PHY_P0; -+ priv->p5_mode = MUX_PHY_P0; - if (id == 4) -- priv->p5_intf_sel = P5_INTF_SEL_PHY_P4; -+ priv->p5_mode = MUX_PHY_P4; - } - of_node_put(mac_np); - of_node_put(phy_node); - break; - } - -- if (priv->p5_intf_sel == P5_INTF_SEL_PHY_P0 || -- priv->p5_intf_sel == P5_INTF_SEL_PHY_P4) -+ if (priv->p5_mode == MUX_PHY_P0 || priv->p5_mode == MUX_PHY_P4) - mt7530_setup_port5(ds, interface); - } - -@@ -2654,9 +2647,6 @@ mt7531_setup(struct dsa_switch *ds) - MT7531_EXT_P_MDIO_12); - } - -- if (!dsa_is_unused_port(ds, 5)) -- priv->p5_intf_sel = P5_INTF_SEL_GMAC5; -- - mt7530_rmw(priv, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK, - MT7531_GPIO0_INTERRUPT); - ---- a/drivers/net/dsa/mt7530.h -+++ b/drivers/net/dsa/mt7530.h -@@ -708,12 +708,11 @@ struct mt7530_port { - struct phylink_pcs *sgmii_pcs; - }; - --/* Port 5 interface select definitions */ --enum p5_interface_select { -- P5_DISABLED, -- P5_INTF_SEL_PHY_P0, -- P5_INTF_SEL_PHY_P4, -- P5_INTF_SEL_GMAC5, -+/* Port 5 mode definitions of the MT7530 switch */ -+enum mt7530_p5_mode { -+ GMAC5, -+ MUX_PHY_P0, -+ MUX_PHY_P4, - }; - - struct mt7530_priv; -@@ -776,7 +775,7 @@ struct mt753x_info { - * @ports: Holding the state among ports - * @reg_mutex: The lock for protecting among process accessing - * registers -- * @p5_intf_sel: Holding the current port 5 interface select -+ * @p5_mode: Holding the current mode of port 5 of the MT7530 switch - * @p5_sgmii: Flag for distinguishing if port 5 of the MT7531 switch - * has got SGMII - * @irq: IRQ number of the switch -@@ -798,7 +797,7 @@ struct mt7530_priv { - const struct mt753x_info *info; - unsigned int id; - bool mcm; -- enum p5_interface_select p5_intf_sel; -+ enum mt7530_p5_mode p5_mode; - bool p5_sgmii; - u8 mirror_rx; - u8 mirror_tx; diff --git a/target/linux/generic/pending-6.6/745-04-net-dsa-mt7530-rename-mt753x_bpdu_port_fw-enum-to-mt.patch b/target/linux/generic/pending-6.6/745-04-net-dsa-mt7530-rename-mt753x_bpdu_port_fw-enum-to-mt.patch deleted file mode 100644 index 948baf58d0..0000000000 --- a/target/linux/generic/pending-6.6/745-04-net-dsa-mt7530-rename-mt753x_bpdu_port_fw-enum-to-mt.patch +++ /dev/null @@ -1,169 +0,0 @@ -From 83fe3df057e641cd0e88425e579d7a5a370ca430 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= -Date: Mon, 22 Apr 2024 10:15:11 +0300 -Subject: [PATCH 04/15] net: dsa: mt7530: rename mt753x_bpdu_port_fw enum to - mt753x_to_cpu_fw -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -The mt753x_bpdu_port_fw enum is globally used for manipulating the process -of deciding the forwardable ports, specifically concerning the CPU port(s). -Therefore, rename it and the values in it to mt753x_to_cpu_fw. - -Change FOLLOW_MFC to SYSTEM_DEFAULT to be on par with the switch documents. - -Signed-off-by: Arınç ÜNAL ---- - drivers/net/dsa/mt7530.c | 44 ++++++++++------------- - drivers/net/dsa/mt7530.h | 76 ++++++++++++++++++++-------------------- - 2 files changed, 56 insertions(+), 64 deletions(-) - ---- a/drivers/net/dsa/mt7530.c -+++ b/drivers/net/dsa/mt7530.c -@@ -1107,42 +1107,34 @@ mt753x_trap_frames(struct mt7530_priv *p - * VLAN-untagged. - */ - mt7530_rmw(priv, MT753X_BPC, -- MT753X_PAE_BPDU_FR | MT753X_PAE_EG_TAG_MASK | -- MT753X_PAE_PORT_FW_MASK | MT753X_BPDU_EG_TAG_MASK | -- MT753X_BPDU_PORT_FW_MASK, -- MT753X_PAE_BPDU_FR | -- MT753X_PAE_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | -- MT753X_PAE_PORT_FW(MT753X_BPDU_CPU_ONLY) | -- MT753X_BPDU_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | -- MT753X_BPDU_CPU_ONLY); -+ PAE_BPDU_FR | PAE_EG_TAG_MASK | PAE_PORT_FW_MASK | -+ BPDU_EG_TAG_MASK | BPDU_PORT_FW_MASK, -+ PAE_BPDU_FR | PAE_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | -+ PAE_PORT_FW(TO_CPU_FW_CPU_ONLY) | -+ BPDU_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | -+ TO_CPU_FW_CPU_ONLY); - - /* Trap frames with :01 and :02 MAC DAs to the CPU port(s) and egress - * them VLAN-untagged. - */ - mt7530_rmw(priv, MT753X_RGAC1, -- MT753X_R02_BPDU_FR | MT753X_R02_EG_TAG_MASK | -- MT753X_R02_PORT_FW_MASK | MT753X_R01_BPDU_FR | -- MT753X_R01_EG_TAG_MASK | MT753X_R01_PORT_FW_MASK, -- MT753X_R02_BPDU_FR | -- MT753X_R02_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | -- MT753X_R02_PORT_FW(MT753X_BPDU_CPU_ONLY) | -- MT753X_R01_BPDU_FR | -- MT753X_R01_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | -- MT753X_BPDU_CPU_ONLY); -+ R02_BPDU_FR | R02_EG_TAG_MASK | R02_PORT_FW_MASK | -+ R01_BPDU_FR | R01_EG_TAG_MASK | R01_PORT_FW_MASK, -+ R02_BPDU_FR | R02_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | -+ R02_PORT_FW(TO_CPU_FW_CPU_ONLY) | R01_BPDU_FR | -+ R01_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | -+ TO_CPU_FW_CPU_ONLY); - - /* Trap frames with :03 and :0E MAC DAs to the CPU port(s) and egress - * them VLAN-untagged. - */ - mt7530_rmw(priv, MT753X_RGAC2, -- MT753X_R0E_BPDU_FR | MT753X_R0E_EG_TAG_MASK | -- MT753X_R0E_PORT_FW_MASK | MT753X_R03_BPDU_FR | -- MT753X_R03_EG_TAG_MASK | MT753X_R03_PORT_FW_MASK, -- MT753X_R0E_BPDU_FR | -- MT753X_R0E_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | -- MT753X_R0E_PORT_FW(MT753X_BPDU_CPU_ONLY) | -- MT753X_R03_BPDU_FR | -- MT753X_R03_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | -- MT753X_BPDU_CPU_ONLY); -+ R0E_BPDU_FR | R0E_EG_TAG_MASK | R0E_PORT_FW_MASK | -+ R03_BPDU_FR | R03_EG_TAG_MASK | R03_PORT_FW_MASK, -+ R0E_BPDU_FR | R0E_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | -+ R0E_PORT_FW(TO_CPU_FW_CPU_ONLY) | R03_BPDU_FR | -+ R03_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | -+ TO_CPU_FW_CPU_ONLY); - } - - static void ---- a/drivers/net/dsa/mt7530.h -+++ b/drivers/net/dsa/mt7530.h -@@ -67,47 +67,47 @@ enum mt753x_id { - #define MT753X_MIRROR_MASK(id) ((((id) == ID_MT7531) || ((id) == ID_MT7988)) ? \ - MT7531_MIRROR_MASK : MIRROR_MASK) - --/* Registers for BPDU and PAE frame control*/ -+/* Register for BPDU and PAE frame control */ - #define MT753X_BPC 0x24 --#define MT753X_PAE_BPDU_FR BIT(25) --#define MT753X_PAE_EG_TAG_MASK GENMASK(24, 22) --#define MT753X_PAE_EG_TAG(x) FIELD_PREP(MT753X_PAE_EG_TAG_MASK, x) --#define MT753X_PAE_PORT_FW_MASK GENMASK(18, 16) --#define MT753X_PAE_PORT_FW(x) FIELD_PREP(MT753X_PAE_PORT_FW_MASK, x) --#define MT753X_BPDU_EG_TAG_MASK GENMASK(8, 6) --#define MT753X_BPDU_EG_TAG(x) FIELD_PREP(MT753X_BPDU_EG_TAG_MASK, x) --#define MT753X_BPDU_PORT_FW_MASK GENMASK(2, 0) -+#define PAE_BPDU_FR BIT(25) -+#define PAE_EG_TAG_MASK GENMASK(24, 22) -+#define PAE_EG_TAG(x) FIELD_PREP(PAE_EG_TAG_MASK, x) -+#define PAE_PORT_FW_MASK GENMASK(18, 16) -+#define PAE_PORT_FW(x) FIELD_PREP(PAE_PORT_FW_MASK, x) -+#define BPDU_EG_TAG_MASK GENMASK(8, 6) -+#define BPDU_EG_TAG(x) FIELD_PREP(BPDU_EG_TAG_MASK, x) -+#define BPDU_PORT_FW_MASK GENMASK(2, 0) - --/* Register for :01 and :02 MAC DA frame control */ -+/* Register for 01-80-C2-00-00-[01,02] MAC DA frame control */ - #define MT753X_RGAC1 0x28 --#define MT753X_R02_BPDU_FR BIT(25) --#define MT753X_R02_EG_TAG_MASK GENMASK(24, 22) --#define MT753X_R02_EG_TAG(x) FIELD_PREP(MT753X_R02_EG_TAG_MASK, x) --#define MT753X_R02_PORT_FW_MASK GENMASK(18, 16) --#define MT753X_R02_PORT_FW(x) FIELD_PREP(MT753X_R02_PORT_FW_MASK, x) --#define MT753X_R01_BPDU_FR BIT(9) --#define MT753X_R01_EG_TAG_MASK GENMASK(8, 6) --#define MT753X_R01_EG_TAG(x) FIELD_PREP(MT753X_R01_EG_TAG_MASK, x) --#define MT753X_R01_PORT_FW_MASK GENMASK(2, 0) -+#define R02_BPDU_FR BIT(25) -+#define R02_EG_TAG_MASK GENMASK(24, 22) -+#define R02_EG_TAG(x) FIELD_PREP(R02_EG_TAG_MASK, x) -+#define R02_PORT_FW_MASK GENMASK(18, 16) -+#define R02_PORT_FW(x) FIELD_PREP(R02_PORT_FW_MASK, x) -+#define R01_BPDU_FR BIT(9) -+#define R01_EG_TAG_MASK GENMASK(8, 6) -+#define R01_EG_TAG(x) FIELD_PREP(R01_EG_TAG_MASK, x) -+#define R01_PORT_FW_MASK GENMASK(2, 0) - --/* Register for :03 and :0E MAC DA frame control */ -+/* Register for 01-80-C2-00-00-[03,0E] MAC DA frame control */ - #define MT753X_RGAC2 0x2c --#define MT753X_R0E_BPDU_FR BIT(25) --#define MT753X_R0E_EG_TAG_MASK GENMASK(24, 22) --#define MT753X_R0E_EG_TAG(x) FIELD_PREP(MT753X_R0E_EG_TAG_MASK, x) --#define MT753X_R0E_PORT_FW_MASK GENMASK(18, 16) --#define MT753X_R0E_PORT_FW(x) FIELD_PREP(MT753X_R0E_PORT_FW_MASK, x) --#define MT753X_R03_BPDU_FR BIT(9) --#define MT753X_R03_EG_TAG_MASK GENMASK(8, 6) --#define MT753X_R03_EG_TAG(x) FIELD_PREP(MT753X_R03_EG_TAG_MASK, x) --#define MT753X_R03_PORT_FW_MASK GENMASK(2, 0) -+#define R0E_BPDU_FR BIT(25) -+#define R0E_EG_TAG_MASK GENMASK(24, 22) -+#define R0E_EG_TAG(x) FIELD_PREP(R0E_EG_TAG_MASK, x) -+#define R0E_PORT_FW_MASK GENMASK(18, 16) -+#define R0E_PORT_FW(x) FIELD_PREP(R0E_PORT_FW_MASK, x) -+#define R03_BPDU_FR BIT(9) -+#define R03_EG_TAG_MASK GENMASK(8, 6) -+#define R03_EG_TAG(x) FIELD_PREP(R03_EG_TAG_MASK, x) -+#define R03_PORT_FW_MASK GENMASK(2, 0) - --enum mt753x_bpdu_port_fw { -- MT753X_BPDU_FOLLOW_MFC, -- MT753X_BPDU_CPU_EXCLUDE = 4, -- MT753X_BPDU_CPU_INCLUDE = 5, -- MT753X_BPDU_CPU_ONLY = 6, -- MT753X_BPDU_DROP = 7, -+enum mt753x_to_cpu_fw { -+ TO_CPU_FW_SYSTEM_DEFAULT, -+ TO_CPU_FW_CPU_EXCLUDE = 4, -+ TO_CPU_FW_CPU_INCLUDE = 5, -+ TO_CPU_FW_CPU_ONLY = 6, -+ TO_CPU_FW_DROP = 7, - }; - - /* Registers for address table access */ diff --git a/target/linux/generic/pending-6.6/745-05-net-dsa-mt7530-refactor-MT7530_MFC-and-MT7531_CFC-ad.patch b/target/linux/generic/pending-6.6/745-05-net-dsa-mt7530-refactor-MT7530_MFC-and-MT7531_CFC-ad.patch deleted file mode 100644 index a5d293b509..0000000000 --- a/target/linux/generic/pending-6.6/745-05-net-dsa-mt7530-refactor-MT7530_MFC-and-MT7531_CFC-ad.patch +++ /dev/null @@ -1,201 +0,0 @@ -From 1dbc1bdc2869e6d2929235c70d64e393aa5a5fa2 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= -Date: Mon, 22 Apr 2024 10:15:12 +0300 -Subject: [PATCH 05/15] net: dsa: mt7530: refactor MT7530_MFC and MT7531_CFC, - add MT7531_QRY_FFP -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -The MT7530_MFC register is on MT7530, MT7531, and the switch on the MT7988 -SoC. Rename it to MT753X_MFC. Bit 7 to 0 differs between MT7530 and -MT7531/MT7988. Add MT7530 prefix to these definitions, and define the -IGMP/MLD Query Frame Flooding Ports mask for MT7531. - -Rename the cases of MIRROR_MASK to MIRROR_PORT_MASK. - -Move mt753x_mirror_port_get() and mt753x_port_mirror_set() to mt7530.h as -macros. - -Signed-off-by: Arınç ÜNAL ---- - drivers/net/dsa/mt7530.c | 38 ++++++++-------------- - drivers/net/dsa/mt7530.h | 69 +++++++++++++++++++++++++--------------- - 2 files changed, 57 insertions(+), 50 deletions(-) - ---- a/drivers/net/dsa/mt7530.c -+++ b/drivers/net/dsa/mt7530.c -@@ -1147,7 +1147,7 @@ mt753x_cpu_port_enable(struct dsa_switch - PORT_SPEC_TAG); - - /* Enable flooding on the CPU port */ -- mt7530_set(priv, MT7530_MFC, BC_FFP(BIT(port)) | UNM_FFP(BIT(port)) | -+ mt7530_set(priv, MT753X_MFC, BC_FFP(BIT(port)) | UNM_FFP(BIT(port)) | - UNU_FFP(BIT(port))); - - /* Add the CPU port to the CPU port bitmap for MT7531 and the switch on -@@ -1311,15 +1311,15 @@ mt7530_port_bridge_flags(struct dsa_swit - flags.val & BR_LEARNING ? 0 : SA_DIS); - - if (flags.mask & BR_FLOOD) -- mt7530_rmw(priv, MT7530_MFC, UNU_FFP(BIT(port)), -+ mt7530_rmw(priv, MT753X_MFC, UNU_FFP(BIT(port)), - flags.val & BR_FLOOD ? UNU_FFP(BIT(port)) : 0); - - if (flags.mask & BR_MCAST_FLOOD) -- mt7530_rmw(priv, MT7530_MFC, UNM_FFP(BIT(port)), -+ mt7530_rmw(priv, MT753X_MFC, UNM_FFP(BIT(port)), - flags.val & BR_MCAST_FLOOD ? UNM_FFP(BIT(port)) : 0); - - if (flags.mask & BR_BCAST_FLOOD) -- mt7530_rmw(priv, MT7530_MFC, BC_FFP(BIT(port)), -+ mt7530_rmw(priv, MT753X_MFC, BC_FFP(BIT(port)), - flags.val & BR_BCAST_FLOOD ? BC_FFP(BIT(port)) : 0); - - return 0; -@@ -1855,20 +1855,6 @@ mt7530_port_vlan_del(struct dsa_switch * - return 0; - } - --static int mt753x_mirror_port_get(unsigned int id, u32 val) --{ -- return (id == ID_MT7531 || id == ID_MT7988) ? -- MT7531_MIRROR_PORT_GET(val) : -- MIRROR_PORT(val); --} -- --static int mt753x_mirror_port_set(unsigned int id, u32 val) --{ -- return (id == ID_MT7531 || id == ID_MT7988) ? -- MT7531_MIRROR_PORT_SET(val) : -- MIRROR_PORT(val); --} -- - static int mt753x_port_mirror_add(struct dsa_switch *ds, int port, - struct dsa_mall_mirror_tc_entry *mirror, - bool ingress, struct netlink_ext_ack *extack) -@@ -1884,14 +1870,14 @@ static int mt753x_port_mirror_add(struct - val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id)); - - /* MT7530 only supports one monitor port */ -- monitor_port = mt753x_mirror_port_get(priv->id, val); -+ monitor_port = MT753X_MIRROR_PORT_GET(priv->id, val); - if (val & MT753X_MIRROR_EN(priv->id) && - monitor_port != mirror->to_local_port) - return -EEXIST; - - val |= MT753X_MIRROR_EN(priv->id); -- val &= ~MT753X_MIRROR_MASK(priv->id); -- val |= mt753x_mirror_port_set(priv->id, mirror->to_local_port); -+ val &= ~MT753X_MIRROR_PORT_MASK(priv->id); -+ val |= MT753X_MIRROR_PORT_SET(priv->id, mirror->to_local_port); - mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val); - - val = mt7530_read(priv, MT7530_PCR_P(port)); -@@ -2533,7 +2519,7 @@ mt7531_setup_common(struct dsa_switch *d - mt7530_mib_reset(ds); - - /* Disable flooding on all ports */ -- mt7530_clear(priv, MT7530_MFC, BC_FFP_MASK | UNM_FFP_MASK | -+ mt7530_clear(priv, MT753X_MFC, BC_FFP_MASK | UNM_FFP_MASK | - UNU_FFP_MASK); - - for (i = 0; i < MT7530_NUM_PORTS; i++) { -@@ -3089,10 +3075,12 @@ mt753x_conduit_state_change(struct dsa_s - else - priv->active_cpu_ports &= ~mask; - -- if (priv->active_cpu_ports) -- val = CPU_EN | CPU_PORT(__ffs(priv->active_cpu_ports)); -+ if (priv->active_cpu_ports) { -+ val = MT7530_CPU_EN | -+ MT7530_CPU_PORT(__ffs(priv->active_cpu_ports)); -+ } - -- mt7530_rmw(priv, MT7530_MFC, CPU_EN | CPU_PORT_MASK, val); -+ mt7530_rmw(priv, MT753X_MFC, MT7530_CPU_EN | MT7530_CPU_PORT_MASK, val); - } - - static int mt7988_setup(struct dsa_switch *ds) ---- a/drivers/net/dsa/mt7530.h -+++ b/drivers/net/dsa/mt7530.h -@@ -36,36 +36,55 @@ enum mt753x_id { - #define MT753X_AGC 0xc - #define LOCAL_EN BIT(7) - --/* Registers to mac forward control for unknown frames */ --#define MT7530_MFC 0x10 --#define BC_FFP(x) (((x) & 0xff) << 24) --#define BC_FFP_MASK BC_FFP(~0) --#define UNM_FFP(x) (((x) & 0xff) << 16) --#define UNM_FFP_MASK UNM_FFP(~0) --#define UNU_FFP(x) (((x) & 0xff) << 8) --#define UNU_FFP_MASK UNU_FFP(~0) --#define CPU_EN BIT(7) --#define CPU_PORT_MASK GENMASK(6, 4) --#define CPU_PORT(x) FIELD_PREP(CPU_PORT_MASK, x) --#define MIRROR_EN BIT(3) --#define MIRROR_PORT(x) ((x) & 0x7) --#define MIRROR_MASK 0x7 -+/* Register for MAC forward control */ -+#define MT753X_MFC 0x10 -+#define BC_FFP_MASK GENMASK(31, 24) -+#define BC_FFP(x) FIELD_PREP(BC_FFP_MASK, x) -+#define UNM_FFP_MASK GENMASK(23, 16) -+#define UNM_FFP(x) FIELD_PREP(UNM_FFP_MASK, x) -+#define UNU_FFP_MASK GENMASK(15, 8) -+#define UNU_FFP(x) FIELD_PREP(UNU_FFP_MASK, x) -+#define MT7530_CPU_EN BIT(7) -+#define MT7530_CPU_PORT_MASK GENMASK(6, 4) -+#define MT7530_CPU_PORT(x) FIELD_PREP(MT7530_CPU_PORT_MASK, x) -+#define MT7530_MIRROR_EN BIT(3) -+#define MT7530_MIRROR_PORT_MASK GENMASK(2, 0) -+#define MT7530_MIRROR_PORT_GET(x) FIELD_GET(MT7530_MIRROR_PORT_MASK, x) -+#define MT7530_MIRROR_PORT_SET(x) FIELD_PREP(MT7530_MIRROR_PORT_MASK, x) -+#define MT7531_QRY_FFP_MASK GENMASK(7, 0) -+#define MT7531_QRY_FFP(x) FIELD_PREP(MT7531_QRY_FFP_MASK, x) - --/* Registers for CPU forward control */ -+/* Register for CPU forward control */ - #define MT7531_CFC 0x4 - #define MT7531_MIRROR_EN BIT(19) --#define MT7531_MIRROR_MASK (MIRROR_MASK << 16) --#define MT7531_MIRROR_PORT_GET(x) (((x) >> 16) & MIRROR_MASK) --#define MT7531_MIRROR_PORT_SET(x) (((x) & MIRROR_MASK) << 16) -+#define MT7531_MIRROR_PORT_MASK GENMASK(18, 16) -+#define MT7531_MIRROR_PORT_GET(x) FIELD_GET(MT7531_MIRROR_PORT_MASK, x) -+#define MT7531_MIRROR_PORT_SET(x) FIELD_PREP(MT7531_MIRROR_PORT_MASK, x) - #define MT7531_CPU_PMAP_MASK GENMASK(7, 0) - #define MT7531_CPU_PMAP(x) FIELD_PREP(MT7531_CPU_PMAP_MASK, x) - --#define MT753X_MIRROR_REG(id) ((((id) == ID_MT7531) || ((id) == ID_MT7988)) ? \ -- MT7531_CFC : MT7530_MFC) --#define MT753X_MIRROR_EN(id) ((((id) == ID_MT7531) || ((id) == ID_MT7988)) ? \ -- MT7531_MIRROR_EN : MIRROR_EN) --#define MT753X_MIRROR_MASK(id) ((((id) == ID_MT7531) || ((id) == ID_MT7988)) ? \ -- MT7531_MIRROR_MASK : MIRROR_MASK) -+#define MT753X_MIRROR_REG(id) ((id == ID_MT7531 || \ -+ id == ID_MT7988) ? \ -+ MT7531_CFC : MT753X_MFC) -+ -+#define MT753X_MIRROR_EN(id) ((id == ID_MT7531 || \ -+ id == ID_MT7988) ? \ -+ MT7531_MIRROR_EN : MT7530_MIRROR_EN) -+ -+#define MT753X_MIRROR_PORT_MASK(id) ((id == ID_MT7531 || \ -+ id == ID_MT7988) ? \ -+ MT7531_MIRROR_PORT_MASK : \ -+ MT7530_MIRROR_PORT_MASK) -+ -+#define MT753X_MIRROR_PORT_GET(id, val) ((id == ID_MT7531 || \ -+ id == ID_MT7988) ? \ -+ MT7531_MIRROR_PORT_GET(val) : \ -+ MT7530_MIRROR_PORT_GET(val)) -+ -+#define MT753X_MIRROR_PORT_SET(id, val) ((id == ID_MT7531 || \ -+ id == ID_MT7988) ? \ -+ MT7531_MIRROR_PORT_SET(val) : \ -+ MT7530_MIRROR_PORT_SET(val)) - - /* Register for BPDU and PAE frame control */ - #define MT753X_BPC 0x24 diff --git a/target/linux/generic/pending-6.6/745-06-net-dsa-mt7530-refactor-MT7530_HWTRAP-and-MT7530_MHW.patch b/target/linux/generic/pending-6.6/745-06-net-dsa-mt7530-refactor-MT7530_HWTRAP-and-MT7530_MHW.patch deleted file mode 100644 index 1f66575f02..0000000000 --- a/target/linux/generic/pending-6.6/745-06-net-dsa-mt7530-refactor-MT7530_HWTRAP-and-MT7530_MHW.patch +++ /dev/null @@ -1,257 +0,0 @@ -From 3ccf67597d35c06a7319e407b1c42f78a7966779 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= -Date: Mon, 22 Apr 2024 10:15:13 +0300 -Subject: [PATCH 06/15] net: dsa: mt7530: refactor MT7530_HWTRAP and - MT7530_MHWTRAP -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -The MT7530_HWTRAP and MT7530_MHWTRAP registers are on MT7530 and MT7531. -It's called hardware trap on MT7530, software trap on MT7531. That's -because some bits of the trap on MT7530 cannot be modified by software -whilst all bits of the trap on MT7531 can. Rename the definitions for them -to MT753X_TRAP and MT753X_MTRAP. Add MT7530 and MT7531 prefixes to the -definitions specific to the switch model. - -Remove the extra parentheses from MT7530_XTAL_40MHZ and MT7530_XTAL_20MHZ. - -Rename MHWTRAP_PHY0_SEL, MHWTRAP_MANUAL, and MHWTRAP_PHY_ACCESS to be on -par with the "MT7621 Giga Switch Programming Guide v0.3" document. - -Make an enumaration for the XTAL frequency. Set the data type of the xtal -variable on mt7531_pll_setup() to it. - -Signed-off-by: Arınç ÜNAL ---- - drivers/net/dsa/mt7530.c | 59 ++++++++++++++++++++-------------------- - drivers/net/dsa/mt7530.h | 50 ++++++++++++++++------------------ - 2 files changed, 54 insertions(+), 55 deletions(-) - ---- a/drivers/net/dsa/mt7530.c -+++ b/drivers/net/dsa/mt7530.c -@@ -417,23 +417,23 @@ mt7530_setup_port6(struct dsa_switch *ds - - mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK, P6_INTF_MODE(1)); - -- xtal = mt7530_read(priv, MT7530_MHWTRAP) & HWTRAP_XTAL_MASK; -+ xtal = mt7530_read(priv, MT753X_MTRAP) & MT7530_XTAL_MASK; - -- if (xtal == HWTRAP_XTAL_25MHZ) -+ if (xtal == MT7530_XTAL_25MHZ) - ssc_delta = 0x57; - else - ssc_delta = 0x87; - - if (priv->id == ID_MT7621) { - /* PLL frequency: 125MHz: 1.0GBit */ -- if (xtal == HWTRAP_XTAL_40MHZ) -+ if (xtal == MT7530_XTAL_40MHZ) - ncpo1 = 0x0640; -- if (xtal == HWTRAP_XTAL_25MHZ) -+ if (xtal == MT7530_XTAL_25MHZ) - ncpo1 = 0x0a00; - } else { /* PLL frequency: 250MHz: 2.0Gbit */ -- if (xtal == HWTRAP_XTAL_40MHZ) -+ if (xtal == MT7530_XTAL_40MHZ) - ncpo1 = 0x0c80; -- if (xtal == HWTRAP_XTAL_25MHZ) -+ if (xtal == MT7530_XTAL_25MHZ) - ncpo1 = 0x1400; - } - -@@ -456,19 +456,20 @@ mt7530_setup_port6(struct dsa_switch *ds - static void - mt7531_pll_setup(struct mt7530_priv *priv) - { -+ enum mt7531_xtal_fsel xtal; - u32 top_sig; - u32 hwstrap; -- u32 xtal; - u32 val; - - val = mt7530_read(priv, MT7531_CREV); - top_sig = mt7530_read(priv, MT7531_TOP_SIG_SR); -- hwstrap = mt7530_read(priv, MT7531_HWTRAP); -+ hwstrap = mt7530_read(priv, MT753X_TRAP); - if ((val & CHIP_REV_M) > 0) -- xtal = (top_sig & PAD_MCM_SMI_EN) ? HWTRAP_XTAL_FSEL_40MHZ : -- HWTRAP_XTAL_FSEL_25MHZ; -+ xtal = (top_sig & PAD_MCM_SMI_EN) ? MT7531_XTAL_FSEL_40MHZ : -+ MT7531_XTAL_FSEL_25MHZ; - else -- xtal = hwstrap & HWTRAP_XTAL_FSEL_MASK; -+ xtal = (hwstrap & MT7531_XTAL25) ? MT7531_XTAL_FSEL_25MHZ : -+ MT7531_XTAL_FSEL_40MHZ; - - /* Step 1 : Disable MT7531 COREPLL */ - val = mt7530_read(priv, MT7531_PLLGP_EN); -@@ -497,13 +498,13 @@ mt7531_pll_setup(struct mt7530_priv *pri - usleep_range(25, 35); - - switch (xtal) { -- case HWTRAP_XTAL_FSEL_25MHZ: -+ case MT7531_XTAL_FSEL_25MHZ: - val = mt7530_read(priv, MT7531_PLLGP_CR0); - val &= ~RG_COREPLL_SDM_PCW_M; - val |= 0x140000 << RG_COREPLL_SDM_PCW_S; - mt7530_write(priv, MT7531_PLLGP_CR0, val); - break; -- case HWTRAP_XTAL_FSEL_40MHZ: -+ case MT7531_XTAL_FSEL_40MHZ: - val = mt7530_read(priv, MT7531_PLLGP_CR0); - val &= ~RG_COREPLL_SDM_PCW_M; - val |= 0x190000 << RG_COREPLL_SDM_PCW_S; -@@ -877,20 +878,20 @@ static void mt7530_setup_port5(struct ds - - mutex_lock(&priv->reg_mutex); - -- val = mt7530_read(priv, MT7530_MHWTRAP); -+ val = mt7530_read(priv, MT753X_MTRAP); - -- val |= MHWTRAP_MANUAL | MHWTRAP_P5_MAC_SEL | MHWTRAP_P5_DIS; -- val &= ~MHWTRAP_P5_RGMII_MODE & ~MHWTRAP_PHY0_SEL; -+ val |= MT7530_CHG_TRAP | MT7530_P5_MAC_SEL | MT7530_P5_DIS; -+ val &= ~MT7530_P5_RGMII_MODE & ~MT7530_P5_PHY0_SEL; - - switch (priv->p5_mode) { - /* MUX_PHY_P0: P0 -> P5 -> SoC MAC */ - case MUX_PHY_P0: -- val |= MHWTRAP_PHY0_SEL; -+ val |= MT7530_P5_PHY0_SEL; - fallthrough; - - /* MUX_PHY_P4: P4 -> P5 -> SoC MAC */ - case MUX_PHY_P4: -- val &= ~MHWTRAP_P5_MAC_SEL & ~MHWTRAP_P5_DIS; -+ val &= ~MT7530_P5_MAC_SEL & ~MT7530_P5_DIS; - - /* Setup the MAC by default for the cpu port */ - mt7530_write(priv, MT753X_PMCR_P(5), 0x56300); -@@ -898,13 +899,13 @@ static void mt7530_setup_port5(struct ds - - /* GMAC5: P5 -> SoC MAC or external PHY */ - default: -- val &= ~MHWTRAP_P5_DIS; -+ val &= ~MT7530_P5_DIS; - break; - } - - /* Setup RGMII settings */ - if (phy_interface_mode_is_rgmii(interface)) { -- val |= MHWTRAP_P5_RGMII_MODE; -+ val |= MT7530_P5_RGMII_MODE; - - /* P5 RGMII RX Clock Control: delay setting for 1000M */ - mt7530_write(priv, MT7530_P5RGMIIRXCR, CSR_RGMII_EDGE_ALIGN); -@@ -924,7 +925,7 @@ static void mt7530_setup_port5(struct ds - P5_IO_CLK_DRV(1) | P5_IO_DATA_DRV(1)); - } - -- mt7530_write(priv, MT7530_MHWTRAP, val); -+ mt7530_write(priv, MT753X_MTRAP, val); - - dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, mode=%s, phy-mode=%s\n", val, - mt7530_p5_mode_str(priv->p5_mode), phy_modes(interface)); -@@ -2365,7 +2366,7 @@ mt7530_setup(struct dsa_switch *ds) - } - - /* Waiting for MT7530 got to stable */ -- INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP); -+ INIT_MT7530_DUMMY_POLL(&p, priv, MT753X_TRAP); - ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0, - 20, 1000000); - if (ret < 0) { -@@ -2380,7 +2381,7 @@ mt7530_setup(struct dsa_switch *ds) - return -ENODEV; - } - -- if ((val & HWTRAP_XTAL_MASK) == HWTRAP_XTAL_20MHZ) { -+ if ((val & MT7530_XTAL_MASK) == MT7530_XTAL_20MHZ) { - dev_err(priv->dev, - "MT7530 with a 20MHz XTAL is not supported!\n"); - return -EINVAL; -@@ -2401,12 +2402,12 @@ mt7530_setup(struct dsa_switch *ds) - RD_TAP_MASK, RD_TAP(16)); - - /* Enable port 6 */ -- val = mt7530_read(priv, MT7530_MHWTRAP); -- val &= ~MHWTRAP_P6_DIS & ~MHWTRAP_PHY_ACCESS; -- val |= MHWTRAP_MANUAL; -- mt7530_write(priv, MT7530_MHWTRAP, val); -+ val = mt7530_read(priv, MT753X_MTRAP); -+ val &= ~MT7530_P6_DIS & ~MT7530_PHY_INDIRECT_ACCESS; -+ val |= MT7530_CHG_TRAP; -+ mt7530_write(priv, MT753X_MTRAP, val); - -- if ((val & HWTRAP_XTAL_MASK) == HWTRAP_XTAL_40MHZ) -+ if ((val & MT7530_XTAL_MASK) == MT7530_XTAL_40MHZ) - mt7530_pll_setup(priv); - - mt753x_trap_frames(priv); -@@ -2586,7 +2587,7 @@ mt7531_setup(struct dsa_switch *ds) - } - - /* Waiting for MT7530 got to stable */ -- INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP); -+ INIT_MT7530_DUMMY_POLL(&p, priv, MT753X_TRAP); - ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0, - 20, 1000000); - if (ret < 0) { ---- a/drivers/net/dsa/mt7530.h -+++ b/drivers/net/dsa/mt7530.h -@@ -495,32 +495,30 @@ enum mt7531_clk_skew { - MT7531_CLK_SKEW_REVERSE = 3, - }; - --/* Register for hw trap status */ --#define MT7530_HWTRAP 0x7800 --#define HWTRAP_XTAL_MASK (BIT(10) | BIT(9)) --#define HWTRAP_XTAL_25MHZ (BIT(10) | BIT(9)) --#define HWTRAP_XTAL_40MHZ (BIT(10)) --#define HWTRAP_XTAL_20MHZ (BIT(9)) -+/* Register for trap status */ -+#define MT753X_TRAP 0x7800 -+#define MT7530_XTAL_MASK (BIT(10) | BIT(9)) -+#define MT7530_XTAL_25MHZ (BIT(10) | BIT(9)) -+#define MT7530_XTAL_40MHZ BIT(10) -+#define MT7530_XTAL_20MHZ BIT(9) -+#define MT7531_XTAL25 BIT(7) - --#define MT7531_HWTRAP 0x7800 --#define HWTRAP_XTAL_FSEL_MASK BIT(7) --#define HWTRAP_XTAL_FSEL_25MHZ BIT(7) --#define HWTRAP_XTAL_FSEL_40MHZ 0 --/* Unique fields of (M)HWSTRAP for MT7531 */ --#define XTAL_FSEL_S 7 --#define XTAL_FSEL_M BIT(7) --#define PHY_EN BIT(6) --#define CHG_STRAP BIT(8) -+/* Register for trap modification */ -+#define MT753X_MTRAP 0x7804 -+#define MT7530_P5_PHY0_SEL BIT(20) -+#define MT7530_CHG_TRAP BIT(16) -+#define MT7530_P5_MAC_SEL BIT(13) -+#define MT7530_P6_DIS BIT(8) -+#define MT7530_P5_RGMII_MODE BIT(7) -+#define MT7530_P5_DIS BIT(6) -+#define MT7530_PHY_INDIRECT_ACCESS BIT(5) -+#define MT7531_CHG_STRAP BIT(8) -+#define MT7531_PHY_EN BIT(6) - --/* Register for hw trap modification */ --#define MT7530_MHWTRAP 0x7804 --#define MHWTRAP_PHY0_SEL BIT(20) --#define MHWTRAP_MANUAL BIT(16) --#define MHWTRAP_P5_MAC_SEL BIT(13) --#define MHWTRAP_P6_DIS BIT(8) --#define MHWTRAP_P5_RGMII_MODE BIT(7) --#define MHWTRAP_P5_DIS BIT(6) --#define MHWTRAP_PHY_ACCESS BIT(5) -+enum mt7531_xtal_fsel { -+ MT7531_XTAL_FSEL_25MHZ, -+ MT7531_XTAL_FSEL_40MHZ, -+}; - - /* Register for TOP signal control */ - #define MT7530_TOP_SIG_CTRL 0x7808 diff --git a/target/linux/generic/pending-6.6/745-08-net-dsa-mt7530-return-mt7530_setup_mdio-mt7531_setup.patch b/target/linux/generic/pending-6.6/745-08-net-dsa-mt7530-return-mt7530_setup_mdio-mt7531_setup.patch deleted file mode 100644 index 3d16bf75d2..0000000000 --- a/target/linux/generic/pending-6.6/745-08-net-dsa-mt7530-return-mt7530_setup_mdio-mt7531_setup.patch +++ /dev/null @@ -1,39 +0,0 @@ -From 1f5669efca65564c7533704917f79003c6b36c9c Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= -Date: Mon, 22 Apr 2024 10:15:15 +0300 -Subject: [PATCH 08/15] net: dsa: mt7530: return mt7530_setup_mdio & - mt7531_setup_common on error -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -The mt7530_setup_mdio() and mt7531_setup_common() functions should be -checked for errors. Return if the functions return a non-zero value. - -Signed-off-by: Arınç ÜNAL ---- - drivers/net/dsa/mt7530.c | 6 +++++- - 1 file changed, 5 insertions(+), 1 deletion(-) - ---- a/drivers/net/dsa/mt7530.c -+++ b/drivers/net/dsa/mt7530.c -@@ -2651,7 +2651,9 @@ mt7531_setup(struct dsa_switch *ds) - 0); - } - -- mt7531_setup_common(ds); -+ ret = mt7531_setup_common(ds); -+ if (ret) -+ return ret; - - /* Setup VLAN ID 0 for VLAN-unaware bridges */ - ret = mt7530_setup_vlan0(priv); -@@ -3004,6 +3006,8 @@ mt753x_setup(struct dsa_switch *ds) - ret = mt7530_setup_mdio(priv); - if (ret && priv->irq) - mt7530_free_irq_common(priv); -+ if (ret) -+ return ret; - - /* Initialise the PCS devices */ - for (i = 0; i < priv->ds->num_ports; i++) { diff --git a/target/linux/generic/pending-6.6/745-09-net-dsa-mt7530-define-MAC-speed-capabilities-per-swi.patch b/target/linux/generic/pending-6.6/745-09-net-dsa-mt7530-define-MAC-speed-capabilities-per-swi.patch deleted file mode 100644 index 4e89bb2464..0000000000 --- a/target/linux/generic/pending-6.6/745-09-net-dsa-mt7530-define-MAC-speed-capabilities-per-swi.patch +++ /dev/null @@ -1,75 +0,0 @@ -From 6cc2d4ccd77509df74b7b8ef46bbc6ba0a571318 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= -Date: Mon, 22 Apr 2024 10:15:16 +0300 -Subject: [PATCH 09/15] net: dsa: mt7530: define MAC speed capabilities per - switch model -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -With the support of the MT7988 SoC switch, the MAC speed capabilities -defined on mt753x_phylink_get_caps() won't apply to all switch models -anymore. Move them to more appropriate locations instead of overwriting -config->mac_capabilities. - -Remove the comment on mt753x_phylink_get_caps() as it's become invalid with -the support of MT7531 and MT7988 SoC switch. - -Add break to case 6 of mt7988_mac_port_get_caps() to be explicit. - -Signed-off-by: Arınç ÜNAL ---- - drivers/net/dsa/mt7530.c | 15 ++++++++++----- - 1 file changed, 10 insertions(+), 5 deletions(-) - ---- a/drivers/net/dsa/mt7530.c -+++ b/drivers/net/dsa/mt7530.c -@@ -2669,6 +2669,8 @@ mt7531_setup(struct dsa_switch *ds) - static void mt7530_mac_port_get_caps(struct dsa_switch *ds, int port, - struct phylink_config *config) - { -+ config->mac_capabilities |= MAC_10 | MAC_100 | MAC_1000FD; -+ - switch (port) { - /* Ports which are connected to switch PHYs. There is no MII pinout. */ - case 0 ... 4: -@@ -2700,6 +2702,8 @@ static void mt7531_mac_port_get_caps(str - { - struct mt7530_priv *priv = ds->priv; - -+ config->mac_capabilities |= MAC_10 | MAC_100 | MAC_1000FD; -+ - switch (port) { - /* Ports which are connected to switch PHYs. There is no MII pinout. */ - case 0 ... 4: -@@ -2739,14 +2743,17 @@ static void mt7988_mac_port_get_caps(str - case 0 ... 3: - __set_bit(PHY_INTERFACE_MODE_INTERNAL, - config->supported_interfaces); -+ -+ config->mac_capabilities |= MAC_10 | MAC_100 | MAC_1000FD; - break; - - /* Port 6 is connected to SoC's XGMII MAC. There is no MII pinout. */ - case 6: - __set_bit(PHY_INTERFACE_MODE_INTERNAL, - config->supported_interfaces); -- config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | -- MAC_10000FD; -+ -+ config->mac_capabilities |= MAC_10000FD; -+ break; - } - } - -@@ -2916,9 +2923,7 @@ static void mt753x_phylink_get_caps(stru - { - struct mt7530_priv *priv = ds->priv; - -- /* This switch only supports full-duplex at 1Gbps */ -- config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | -- MAC_10 | MAC_100 | MAC_1000FD; -+ config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE; - - priv->info->mac_port_get_caps(ds, port, config); - } diff --git a/target/linux/generic/pending-6.6/745-10-net-dsa-mt7530-get-rid-of-function-sanity-check.patch b/target/linux/generic/pending-6.6/745-10-net-dsa-mt7530-get-rid-of-function-sanity-check.patch deleted file mode 100644 index df43224c47..0000000000 --- a/target/linux/generic/pending-6.6/745-10-net-dsa-mt7530-get-rid-of-function-sanity-check.patch +++ /dev/null @@ -1,33 +0,0 @@ -From dd0f15fc877c10567699190bce0f55e96f4ad6b5 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= -Date: Mon, 22 Apr 2024 10:15:17 +0300 -Subject: [PATCH 10/15] net: dsa: mt7530: get rid of function sanity check -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Get rid of checking whether functions are filled properly. priv->info which -is an mt753x_info structure is filled and checked for before this check. -It's unnecessary checking whether it's filled properly. - -Signed-off-by: Arınç ÜNAL ---- - drivers/net/dsa/mt7530.c | 7 ------- - 1 file changed, 7 deletions(-) - ---- a/drivers/net/dsa/mt7530.c -+++ b/drivers/net/dsa/mt7530.c -@@ -3216,13 +3216,6 @@ mt7530_probe_common(struct mt7530_priv * - if (!priv->info) - return -EINVAL; - -- /* Sanity check if these required device operations are filled -- * properly. -- */ -- if (!priv->info->sw_setup || !priv->info->phy_read_c22 || -- !priv->info->phy_write_c22 || !priv->info->mac_port_get_caps) -- return -EINVAL; -- - priv->id = priv->info->id; - priv->dev = dev; - priv->ds->priv = priv; diff --git a/target/linux/generic/pending-6.6/745-11-net-dsa-mt7530-refactor-MT7530_PMEEECR_P.patch b/target/linux/generic/pending-6.6/745-11-net-dsa-mt7530-refactor-MT7530_PMEEECR_P.patch deleted file mode 100644 index df7085f89c..0000000000 --- a/target/linux/generic/pending-6.6/745-11-net-dsa-mt7530-refactor-MT7530_PMEEECR_P.patch +++ /dev/null @@ -1,71 +0,0 @@ -From 2dff9759602b069f97ccc939e15a47ca051b2983 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= -Date: Mon, 22 Apr 2024 10:15:18 +0300 -Subject: [PATCH 11/15] net: dsa: mt7530: refactor MT7530_PMEEECR_P() -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -The MT7530_PMEEECR_P() register is on MT7530, MT7531, and the switch on the -MT7988 SoC. Rename the definition for them to MT753X_PMEEECR_P(). Use the -FIELD_PREP and FIELD_GET macros. Rename GET_LPI_THRESH() and -SET_LPI_THRESH() to LPI_THRESH_GET() and LPI_THRESH_SET(). - -Signed-off-by: Arınç ÜNAL ---- - drivers/net/dsa/mt7530.c | 8 ++++---- - drivers/net/dsa/mt7530.h | 13 +++++++------ - 2 files changed, 11 insertions(+), 10 deletions(-) - ---- a/drivers/net/dsa/mt7530.c -+++ b/drivers/net/dsa/mt7530.c -@@ -3035,10 +3035,10 @@ static int mt753x_get_mac_eee(struct dsa - struct ethtool_eee *e) - { - struct mt7530_priv *priv = ds->priv; -- u32 eeecr = mt7530_read(priv, MT7530_PMEEECR_P(port)); -+ u32 eeecr = mt7530_read(priv, MT753X_PMEEECR_P(port)); - - e->tx_lpi_enabled = !(eeecr & LPI_MODE_EN); -- e->tx_lpi_timer = GET_LPI_THRESH(eeecr); -+ e->tx_lpi_timer = LPI_THRESH_GET(eeecr); - - return 0; - } -@@ -3052,11 +3052,11 @@ static int mt753x_set_mac_eee(struct dsa - if (e->tx_lpi_timer > 0xFFF) - return -EINVAL; - -- set = SET_LPI_THRESH(e->tx_lpi_timer); -+ set = LPI_THRESH_SET(e->tx_lpi_timer); - if (!e->tx_lpi_enabled) - /* Force LPI Mode without a delay */ - set |= LPI_MODE_EN; -- mt7530_rmw(priv, MT7530_PMEEECR_P(port), mask, set); -+ mt7530_rmw(priv, MT753X_PMEEECR_P(port), mask, set); - - return 0; - } ---- a/drivers/net/dsa/mt7530.h -+++ b/drivers/net/dsa/mt7530.h -@@ -364,13 +364,14 @@ enum mt7530_vlan_port_acc_frm { - PMCR_FORCE_SPEED_100 | \ - PMCR_FORCE_FDX | PMCR_FORCE_LNK) - --#define MT7530_PMEEECR_P(x) (0x3004 + (x) * 0x100) --#define WAKEUP_TIME_1000(x) (((x) & 0xFF) << 24) --#define WAKEUP_TIME_100(x) (((x) & 0xFF) << 16) -+#define MT753X_PMEEECR_P(x) (0x3004 + (x) * 0x100) -+#define WAKEUP_TIME_1000_MASK GENMASK(31, 24) -+#define WAKEUP_TIME_1000(x) FIELD_PREP(WAKEUP_TIME_1000_MASK, x) -+#define WAKEUP_TIME_100_MASK GENMASK(23, 16) -+#define WAKEUP_TIME_100(x) FIELD_PREP(WAKEUP_TIME_100_MASK, x) - #define LPI_THRESH_MASK GENMASK(15, 4) --#define LPI_THRESH_SHT 4 --#define SET_LPI_THRESH(x) (((x) << LPI_THRESH_SHT) & LPI_THRESH_MASK) --#define GET_LPI_THRESH(x) (((x) & LPI_THRESH_MASK) >> LPI_THRESH_SHT) -+#define LPI_THRESH_GET(x) FIELD_GET(LPI_THRESH_MASK, x) -+#define LPI_THRESH_SET(x) FIELD_PREP(LPI_THRESH_MASK, x) - #define LPI_MODE_EN BIT(0) - - #define MT7530_PMSR_P(x) (0x3008 + (x) * 0x100) diff --git a/target/linux/generic/pending-6.6/745-12-net-dsa-mt7530-get-rid-of-mac_port_validate-member-o.patch b/target/linux/generic/pending-6.6/745-12-net-dsa-mt7530-get-rid-of-mac_port_validate-member-o.patch deleted file mode 100644 index d083708548..0000000000 --- a/target/linux/generic/pending-6.6/745-12-net-dsa-mt7530-get-rid-of-mac_port_validate-member-o.patch +++ /dev/null @@ -1,48 +0,0 @@ -From 21d67c2fabfe40baf33202d3287b67b6c16f8382 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= -Date: Mon, 22 Apr 2024 10:15:19 +0300 -Subject: [PATCH 12/15] net: dsa: mt7530: get rid of mac_port_validate member - of mt753x_info -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -The mac_port_validate member of the mt753x_info structure is not being -used, remove it. Improve the member description section in the process. - -Signed-off-by: Arınç ÜNAL ---- - drivers/net/dsa/mt7530.h | 10 +++------- - 1 file changed, 3 insertions(+), 7 deletions(-) - ---- a/drivers/net/dsa/mt7530.h -+++ b/drivers/net/dsa/mt7530.h -@@ -743,15 +743,14 @@ struct mt753x_pcs { - - /* struct mt753x_info - This is the main data structure for holding the specific - * part for each supported device -+ * @id: Holding the identifier to a switch model -+ * @pcs_ops: Holding the pointer to the MAC PCS operations structure - * @sw_setup: Holding the handler to a device initialization - * @phy_read_c22: Holding the way reading PHY port using C22 - * @phy_write_c22: Holding the way writing PHY port using C22 - * @phy_read_c45: Holding the way reading PHY port using C45 - * @phy_write_c45: Holding the way writing PHY port using C45 -- * @phy_mode_supported: Check if the PHY type is being supported on a certain -- * port -- * @mac_port_validate: Holding the way to set addition validate type for a -- * certan MAC port -+ * @mac_port_get_caps: Holding the handler that provides MAC capabilities - * @mac_port_config: Holding the way setting up the PHY attribute to a - * certain MAC port - */ -@@ -770,9 +769,6 @@ struct mt753x_info { - int regnum, u16 val); - void (*mac_port_get_caps)(struct dsa_switch *ds, int port, - struct phylink_config *config); -- void (*mac_port_validate)(struct dsa_switch *ds, int port, -- phy_interface_t interface, -- unsigned long *supported); - void (*mac_port_config)(struct dsa_switch *ds, int port, - unsigned int mode, - phy_interface_t interface); diff --git a/target/linux/generic/pending-6.6/745-13-net-dsa-mt7530-use-priv-ds-num_ports-instead-of-MT75.patch b/target/linux/generic/pending-6.6/745-13-net-dsa-mt7530-use-priv-ds-num_ports-instead-of-MT75.patch deleted file mode 100644 index d1f692f73a..0000000000 --- a/target/linux/generic/pending-6.6/745-13-net-dsa-mt7530-use-priv-ds-num_ports-instead-of-MT75.patch +++ /dev/null @@ -1,57 +0,0 @@ -From 6efc8ae3eb0363328f479191a0cf0dc12a16e090 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= -Date: Mon, 22 Apr 2024 10:15:20 +0300 -Subject: [PATCH 13/15] net: dsa: mt7530: use priv->ds->num_ports instead of - MT7530_NUM_PORTS -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Use priv->ds->num_ports on all for loops which configure the switch -registers. In the future, the value of MT7530_NUM_PORTS will depend on -priv->id. Therefore, this change prepares the subdriver for a simpler -implementation. - -Signed-off-by: Arınç ÜNAL ---- - drivers/net/dsa/mt7530.c | 8 ++++---- - 1 file changed, 4 insertions(+), 4 deletions(-) - ---- a/drivers/net/dsa/mt7530.c -+++ b/drivers/net/dsa/mt7530.c -@@ -1398,7 +1398,7 @@ mt7530_port_set_vlan_unaware(struct dsa_ - mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, - G0_PORT_VID_DEF); - -- for (i = 0; i < MT7530_NUM_PORTS; i++) { -+ for (i = 0; i < priv->ds->num_ports; i++) { - if (dsa_is_user_port(ds, i) && - dsa_port_is_vlan_filtering(dsa_to_port(ds, i))) { - all_user_ports_removed = false; -@@ -2415,7 +2415,7 @@ mt7530_setup(struct dsa_switch *ds) - /* Enable and reset MIB counters */ - mt7530_mib_reset(ds); - -- for (i = 0; i < MT7530_NUM_PORTS; i++) { -+ for (i = 0; i < priv->ds->num_ports; i++) { - /* Clear link settings and enable force mode to force link down - * on all ports until they're enabled later. - */ -@@ -2523,7 +2523,7 @@ mt7531_setup_common(struct dsa_switch *d - mt7530_clear(priv, MT753X_MFC, BC_FFP_MASK | UNM_FFP_MASK | - UNU_FFP_MASK); - -- for (i = 0; i < MT7530_NUM_PORTS; i++) { -+ for (i = 0; i < priv->ds->num_ports; i++) { - /* Clear link settings and enable force mode to force link down - * on all ports until they're enabled later. - */ -@@ -2610,7 +2610,7 @@ mt7531_setup(struct dsa_switch *ds) - priv->p5_sgmii = !!(val & PAD_DUAL_SGMII_EN); - - /* Force link down on all ports before internal reset */ -- for (i = 0; i < MT7530_NUM_PORTS; i++) -+ for (i = 0; i < priv->ds->num_ports; i++) - mt7530_write(priv, MT753X_PMCR_P(i), MT7531_FORCE_MODE_LNK); - - /* Reset the switch through internal reset */ diff --git a/target/linux/generic/pending-6.6/745-14-net-dsa-mt7530-do-not-pass-port-variable-to-mt7531_r.patch b/target/linux/generic/pending-6.6/745-14-net-dsa-mt7530-do-not-pass-port-variable-to-mt7531_r.patch deleted file mode 100644 index 32919df0f2..0000000000 --- a/target/linux/generic/pending-6.6/745-14-net-dsa-mt7530-do-not-pass-port-variable-to-mt7531_r.patch +++ /dev/null @@ -1,37 +0,0 @@ -From c078ebbf5f6f6d8390035a9f92eeab766b78884d Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= -Date: Mon, 22 Apr 2024 10:15:21 +0300 -Subject: [PATCH 14/15] net: dsa: mt7530: do not pass port variable to - mt7531_rgmii_setup() -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -The mt7531_rgmii_setup() function does not use the port variable, do not -pass the variable to it. - -Signed-off-by: Arınç ÜNAL ---- - drivers/net/dsa/mt7530.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - ---- a/drivers/net/dsa/mt7530.c -+++ b/drivers/net/dsa/mt7530.c -@@ -2769,7 +2769,7 @@ mt7530_mac_config(struct dsa_switch *ds, - mt7530_setup_port6(priv->ds, interface); - } - --static void mt7531_rgmii_setup(struct mt7530_priv *priv, u32 port, -+static void mt7531_rgmii_setup(struct mt7530_priv *priv, - phy_interface_t interface, - struct phy_device *phydev) - { -@@ -2820,7 +2820,7 @@ mt7531_mac_config(struct dsa_switch *ds, - if (phy_interface_mode_is_rgmii(interface)) { - dp = dsa_to_port(ds, port); - phydev = dp->slave->phydev; -- mt7531_rgmii_setup(priv, port, interface, phydev); -+ mt7531_rgmii_setup(priv, interface, phydev); - } - } - diff --git a/target/linux/generic/pending-6.6/745-15-net-dsa-mt7530-explain-exposing-MDIO-bus-of-MT7531AE.patch b/target/linux/generic/pending-6.6/745-15-net-dsa-mt7530-explain-exposing-MDIO-bus-of-MT7531AE.patch deleted file mode 100644 index 22cc625af8..0000000000 --- a/target/linux/generic/pending-6.6/745-15-net-dsa-mt7530-explain-exposing-MDIO-bus-of-MT7531AE.patch +++ /dev/null @@ -1,33 +0,0 @@ -From e7a9cc3cc00b40e0bc2bae40bd2ece0e48fa51d5 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= -Date: Mon, 22 Apr 2024 10:15:22 +0300 -Subject: [PATCH 15/15] net: dsa: mt7530: explain exposing MDIO bus of MT7531AE - better -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Unlike MT7531BE, the GPIO 6-12 pins are not used for RGMII on MT7531AE. -Therefore, the GPIO 11-12 pins are set to function as MDC and MDIO to -expose the MDIO bus of the switch. Replace the comment with a better -explanation. - -Signed-off-by: Arınç ÜNAL ---- - drivers/net/dsa/mt7530.c | 5 ++++- - 1 file changed, 4 insertions(+), 1 deletion(-) - ---- a/drivers/net/dsa/mt7530.c -+++ b/drivers/net/dsa/mt7530.c -@@ -2619,7 +2619,10 @@ mt7531_setup(struct dsa_switch *ds) - if (!priv->p5_sgmii) { - mt7531_pll_setup(priv); - } else { -- /* Let ds->slave_mii_bus be able to access external phy. */ -+ /* Unlike MT7531BE, the GPIO 6-12 pins are not used for RGMII on -+ * MT7531AE. Set the GPIO 11-12 pins to function as MDC and MDIO -+ * to expose the MDIO bus of the switch. -+ */ - mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO11_RG_RXD2_MASK, - MT7531_EXT_P_MDC_11); - mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO12_RG_RXD3_MASK, diff --git a/target/linux/generic/pending-6.6/795-01-net-dsa-mt7530-do-not-set-MT7530_P5_DIS-when-PHY-.patch b/target/linux/generic/pending-6.6/795-01-net-dsa-mt7530-do-not-set-MT7530_P5_DIS-when-PHY-.patch new file mode 100644 index 0000000000..286c96e43b --- /dev/null +++ b/target/linux/generic/pending-6.6/795-01-net-dsa-mt7530-do-not-set-MT7530_P5_DIS-when-PHY-.patch @@ -0,0 +1,79 @@ +From patchwork Sat Apr 27 11:24:42 2024 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 8bit +X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTCB2aWEgQjQgUmVsYXk=?= + +X-Patchwork-Id: 13645655 +From: =?utf-8?b?QXLEsW7DpyDDnE5BTCB2aWEgQjQgUmVsYXk=?= + +Date: Sat, 27 Apr 2024 14:24:42 +0300 +Subject: [PATCH net-next] net: dsa: mt7530: do not set MT7530_P5_DIS when + PHY muxing is being used +Precedence: bulk +X-Mailing-List: netdev@vger.kernel.org +List-Id: +List-Subscribe: +List-Unsubscribe: +MIME-Version: 1.0 +Message-Id: + <20240427-for-netnext-mt7530-do-not-disable-port5-when-phy-muxing-v1-1-793cdf9d7707@arinc9.com> +To: Daniel Golle , DENG Qingfang , + Sean Wang , Andrew Lunn , + Florian Fainelli , + Vladimir Oltean , + "David S. Miller" , Eric Dumazet , + Jakub Kicinski , Paolo Abeni , + Matthias Brugger , + AngeloGioacchino Del Regno +Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, + linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, + =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= +X-Mailer: b4 0.13.0 +X-Patchwork-Delegate: kuba@kernel.org + +From: Arınç ÜNAL + +When the PHY muxing feature is in use, port 5 won't be defined in the +device tree. Because of this, the type member of the dsa_port structure for +this port will be assigned DSA_PORT_TYPE_UNUSED. The dsa_port_setup() +function calls ds->ops->port_disable() when the port type is +DSA_PORT_TYPE_UNUSED. + +The MT7530_P5_DIS bit is unset when PHY muxing is being used. +mt7530_port_disable() which is assigned to ds->ops->port_disable() is +called afterwards. Currently, mt7530_port_disable() sets MT7530_P5_DIS +which breaks network connectivity when PHY muxing is being used. + +Therefore, do not set MT7530_P5_DIS when PHY muxing is being used. + +Fixes: 377174c5760c ("net: dsa: mt7530: move MT753X_MTRAP operations for MT7530") +Reported-by: Daniel Golle +Signed-off-by: Arınç ÜNAL +--- +Hello. + +I've sent this to net-next as the patch it fixes is on the current +development cycle. +--- + drivers/net/dsa/mt7530.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + + +--- +base-commit: 5c4c0edca68a5841a8d53ccd49596fe199c8334c +change-id: 20240427-for-netnext-mt7530-do-not-disable-port5-when-phy-muxing-7ff5fd0995d7 + +Best regards, + +--- a/drivers/net/dsa/mt7530.c ++++ b/drivers/net/dsa/mt7530.c +@@ -1220,7 +1220,7 @@ mt7530_port_disable(struct dsa_switch *d + if (priv->id != ID_MT7530 && priv->id != ID_MT7621) + return; + +- if (port == 5) ++ if (port == 5 && priv->p5_mode == GMAC5) + mt7530_set(priv, MT753X_MTRAP, MT7530_P5_DIS); + else if (port == 6) + mt7530_set(priv, MT753X_MTRAP, MT7530_P6_DIS);