From: John Crispin Date: Thu, 6 Nov 2014 09:31:19 +0000 (+0000) Subject: ralink: add mt7628 support to the ethernet driver X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=f8404aaf9e44bab6fb629d5ee106e50ca2943d1c;p=openwrt%2Fstaging%2Fdedeckeh.git ralink: add mt7628 support to the ethernet driver Signed-off-by: John Crispin SVN-Revision: 43196 --- diff --git a/target/linux/ramips/files/drivers/net/ethernet/ralink/esw_rt3052.c b/target/linux/ramips/files/drivers/net/ethernet/ralink/esw_rt3052.c index b9370628d8..ae37a0307d 100644 --- a/target/linux/ramips/files/drivers/net/ethernet/ralink/esw_rt3052.c +++ b/target/linux/ramips/files/drivers/net/ethernet/ralink/esw_rt3052.c @@ -38,7 +38,29 @@ #include #include +#ifdef CONFIG_SOC_MT7620 +static inline int soc_is_rt3352(void) +{ + return 0; +} + +static inline int soc_is_mt7628(void) +{ + return 1; +} + +static inline int soc_is_rt5350(void) +{ + return 0; +} +#else #include +static inline int soc_is_mt7628(void) +{ + return 0; +} +#endif + #include /* @@ -616,6 +638,53 @@ static void esw_hw_init(struct rt305x_esw *esw) rt305x_mii_write(esw, 0, 29, 0x598b); /* select local register */ rt305x_mii_write(esw, 0, 31, 0x8000); + } else if (soc_is_mt7628()) { + int i; + u32 phy_val; + u32 val; + + /* reset EPHY */ + val = rt_sysc_r32(SYSC_REG_RESET_CTRL); + rt_sysc_w32(val | RT5350_RESET_EPHY, SYSC_REG_RESET_CTRL); + rt_sysc_w32(val, SYSC_REG_RESET_CTRL); + + rt305x_mii_write(esw, 0, 31, 0x2000); /* change G2 page */ + rt305x_mii_write(esw, 0, 26, 0x0020); + + for (i = 0; i < 5; i++) { + rt305x_mii_write(esw, i, 31, 0x8000); //change L0 page + rt305x_mii_write(esw, i, 0, 0x3100); +// mii_mgr_read(i, 26, &phy_val);// EEE setting +// phy_val |= (1 << 5); +// rt305x_mii_write(esw, i, 26, phy_val); + rt305x_mii_write(esw, i, 30, 0xa000); + rt305x_mii_write(esw, i, 31, 0xa000); // change L2 page + rt305x_mii_write(esw, i, 16, 0x0606); + rt305x_mii_write(esw, i, 23, 0x0f0e); + rt305x_mii_write(esw, i, 24, 0x1610); + rt305x_mii_write(esw, i, 30, 0x1f15); + rt305x_mii_write(esw, i, 28, 0x6111); +// mii_mgr_read(i, 4, &phy_val); +// phy_val |= (1 << 10); +// rt305x_mii_write(esw, i, 4, phy_val); + rt305x_mii_write(esw, i, 31, 0x2000); // change G2 page + rt305x_mii_write(esw, i, 26, 0x0000); + } + + //100Base AOI setting + rt305x_mii_write(esw, 0, 31, 0x5000); //change G5 page + rt305x_mii_write(esw, 0, 19, 0x004a); + rt305x_mii_write(esw, 0, 20, 0x015a); + rt305x_mii_write(esw, 0, 21, 0x00ee); + rt305x_mii_write(esw, 0, 22, 0x0033); + rt305x_mii_write(esw, 0, 23, 0x020a); + rt305x_mii_write(esw, 0, 24, 0x0000); + rt305x_mii_write(esw, 0, 25, 0x024a); + rt305x_mii_write(esw, 0, 26, 0x035a); + rt305x_mii_write(esw, 0, 27, 0x02ee); + rt305x_mii_write(esw, 0, 28, 0x0233); + rt305x_mii_write(esw, 0, 29, 0x000a); + rt305x_mii_write(esw, 0, 30, 0x0000); } else { rt305x_mii_write(esw, 0, 31, 0x8000); for (i = 0; i < 5; i++) { @@ -1002,7 +1071,7 @@ esw_get_port_tr_badgood(struct switch_dev *dev, int shift = attr->id == RT5350_ESW_ATTR_PORT_TR_GOOD ? 0 : 16; u32 reg; - if (!soc_is_rt5350()) + if (!soc_is_rt5350() && !soc_is_mt7628()) return -EINVAL; if (idx < 0 || idx >= RT305X_ESW_NUM_LANWAN) diff --git a/target/linux/ramips/files/drivers/net/ethernet/ralink/soc_rt305x.c b/target/linux/ramips/files/drivers/net/ethernet/ralink/soc_rt305x.c index ec09500afd..746b118e1e 100644 --- a/target/linux/ramips/files/drivers/net/ethernet/ralink/soc_rt305x.c +++ b/target/linux/ramips/files/drivers/net/ethernet/ralink/soc_rt305x.c @@ -18,7 +18,19 @@ #include #include +#ifdef CONFIG_SOC_MT7620 +static inline int soc_is_rt3352(void) +{ + return 0; +} + +static inline int soc_is_rt3052(void) +{ + return 0; +} +#else #include +#endif #include "ralink_soc_eth.h" #include "mdio_rt2880.h" @@ -79,6 +91,9 @@ static void rt305x_fe_reset(void) static void rt5350_init_data(struct fe_soc_data *data, struct net_device *netdev) { + struct fe_priv *priv = netdev_priv(netdev); + + priv->flags = FE_FLAG_PADDING_64B | FE_FLAG_PADDING_BUG; netdev->hw_features = NETIF_F_SG | NETIF_F_RXCSUM; }