From: Robert Marko Date: Mon, 19 Feb 2024 20:05:27 +0000 (+0100) Subject: airoha: copy 5.15 files to 6.1 X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=f6112096627da6158dacd8265692f73ca4544f7d;p=openwrt%2Fstaging%2Fneocturne.git airoha: copy 5.15 files to 6.1 Start working on updating airoha to 6.1 by copying 5.15 config and patches to 6.1. Signed-off-by: Robert Marko --- diff --git a/target/linux/airoha/config-6.1 b/target/linux/airoha/config-6.1 new file mode 100644 index 0000000000..ae6c1d5089 --- /dev/null +++ b/target/linux/airoha/config-6.1 @@ -0,0 +1,270 @@ +CONFIG_ALIGNMENT_TRAP=y +CONFIG_ARCH_32BIT_OFF_T=y +CONFIG_ARCH_AIROHA=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_KEEP_MEMBLOCK=y +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +CONFIG_ARCH_MULTIPLATFORM=y +CONFIG_ARCH_MULTI_V6_V7=y +CONFIG_ARCH_MULTI_V7=y +CONFIG_ARCH_NR_GPIO=0 +CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y +CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y +CONFIG_ARCH_SELECT_MEMORY_MODEL=y +CONFIG_ARCH_SPARSEMEM_ENABLE=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARM=y +CONFIG_ARM_AMBA=y +CONFIG_ARM_ARCH_TIMER=y +CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y +CONFIG_ARM_CPU_SUSPEND=y +CONFIG_ARM_CRYPTO=y +CONFIG_ARM_GIC=y +CONFIG_ARM_GIC_V3=y +CONFIG_ARM_GIC_V3_ITS=y +CONFIG_ARM_GIC_V3_ITS_PCI=y +CONFIG_ARM_HAS_SG_CHAIN=y +CONFIG_ARM_HEAVY_MB=y +# CONFIG_ARM_HIGHBANK_CPUIDLE is not set +CONFIG_ARM_L1_CACHE_SHIFT=6 +CONFIG_ARM_L1_CACHE_SHIFT_6=y +CONFIG_ARM_PATCH_IDIV=y +CONFIG_ARM_PATCH_PHYS_VIRT=y +CONFIG_ARM_PSCI=y +CONFIG_ARM_PSCI_FW=y +# CONFIG_ARM_SMMU is not set +CONFIG_ARM_THUMB=y +CONFIG_ARM_UNWIND=y +CONFIG_ARM_VIRT_EXT=y +CONFIG_ATAGS=y +CONFIG_AUTO_ZRELADDR=y +CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y +CONFIG_BLK_DEV_SD=y +CONFIG_BLK_MQ_PCI=y +CONFIG_BLK_PM=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_CACHE_L2X0=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_CMDLINE="rootfstype=squashfs,jffs2" +CONFIG_CMDLINE_FROM_BOOTLOADER=y +CONFIG_COMMON_CLK=y +CONFIG_COMMON_CLK_EN7523=y +CONFIG_COMPAT_32BIT_TIME=y +CONFIG_CPU_32v6K=y +CONFIG_CPU_32v7=y +CONFIG_CPU_ABRT_EV7=y +CONFIG_CPU_CACHE_V7=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y +CONFIG_CPU_HAS_ASID=y +CONFIG_CPU_IDLE=y +CONFIG_CPU_IDLE_GOV_MENU=y +CONFIG_CPU_PABRT_V7=y +CONFIG_CPU_PM=y +CONFIG_CPU_RMAP=y +CONFIG_CPU_SPECTRE=y +CONFIG_CPU_THUMB_CAPABLE=y +CONFIG_CPU_TLB_V7=y +CONFIG_CPU_V7=y +CONFIG_CRC16=y +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_HASH_INFO=y +CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y +CONFIG_CRYPTO_LZO=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_ZSTD=y +CONFIG_DCACHE_WORD_ACCESS=y +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" +CONFIG_DEBUG_MISC=y +CONFIG_DMA_OPS=y +CONFIG_DMA_REMAP=y +CONFIG_DTC=y +CONFIG_EDAC_ATOMIC_SCRUB=y +CONFIG_EDAC_SUPPORT=y +CONFIG_FIXED_PHY=y +CONFIG_FIX_EARLYCON_MEM=y +CONFIG_FWNODE_MDIO=y +CONFIG_FW_LOADER_PAGED_BUF=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_GENERIC_ARCH_TOPOLOGY=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y +CONFIG_GENERIC_CPU_AUTOPROBE=y +CONFIG_GENERIC_CPU_VULNERABILITIES=y +CONFIG_GENERIC_EARLY_IOREMAP=y +CONFIG_GENERIC_GETTIMEOFDAY=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y +CONFIG_GENERIC_IRQ_MIGRATION=y +CONFIG_GENERIC_IRQ_MULTI_HANDLER=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y +CONFIG_GENERIC_MSI_IRQ=y +CONFIG_GENERIC_MSI_IRQ_DOMAIN=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_PHY=y +CONFIG_GENERIC_PINCONF=y +CONFIG_GENERIC_PINCTRL_GROUPS=y +CONFIG_GENERIC_PINMUX_FUNCTIONS=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GENERIC_VDSO_32=y +CONFIG_GPIOLIB_IRQCHIP=y +CONFIG_GPIO_CDEV=y +CONFIG_GPIO_EN7523=y +CONFIG_GPIO_GENERIC=y +CONFIG_HANDLE_DOMAIN_IRQ=y +CONFIG_HARDEN_BRANCH_PREDICTOR=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HAVE_SMP=y +CONFIG_HOTPLUG_CPU=y +CONFIG_HW_RANDOM=y +CONFIG_HZ_FIXED=0 +CONFIG_INITRAMFS_SOURCE="" +# CONFIG_IOMMU_DEBUGFS is not set +# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set +# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set +CONFIG_IOMMU_SUPPORT=y +CONFIG_IRQCHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_TIME_ACCOUNTING=y +CONFIG_IRQ_WORK=y +# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set +CONFIG_LIBFDT=y +CONFIG_LOCK_DEBUGGING_SUPPORT=y +CONFIG_LOCK_SPIN_ON_OWNER=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_MDIO_BUS=y +CONFIG_MDIO_DEVICE=y +CONFIG_MDIO_DEVRES=y +CONFIG_MEMFD_CREATE=y +CONFIG_MFD_SYSCON=y +CONFIG_MIGHT_HAVE_CACHE_L2X0=y +CONFIG_MIGRATION=y +CONFIG_MODULES_USE_ELF_REL=y +CONFIG_MTD_NAND_CORE=y +CONFIG_MTD_NAND_ECC=y +CONFIG_MTD_NAND_ECC_SW_HAMMING=y +CONFIG_MTD_SPI_NAND=y +CONFIG_MTD_SPI_NOR=y +CONFIG_MTD_SPLIT_FIRMWARE=y +CONFIG_MTD_SPLIT_FIT_FW=y +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_BEB_LIMIT=20 +CONFIG_MTD_UBI_BLOCK=y +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_MUTEX_SPIN_ON_OWNER=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NET_FLOW_LIMIT=y +CONFIG_NET_SELFTESTS=y +CONFIG_NLS=y +CONFIG_NO_HZ_COMMON=y +CONFIG_NO_HZ_IDLE=y +CONFIG_NR_CPUS=2 +CONFIG_NVMEM=y +CONFIG_NVMEM_SYSFS=y +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IRQ=y +CONFIG_OF_KOBJ=y +CONFIG_OF_MDIO=y +CONFIG_OLD_SIGACTION=y +CONFIG_OLD_SIGSUSPEND3=y +CONFIG_OUTER_CACHE=y +CONFIG_OUTER_CACHE_SYNC=y +CONFIG_PADATA=y +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_PARTITION_PERCPU=y +CONFIG_PCI=y +CONFIG_PCIEAER=y +CONFIG_PCIEPORTBUS=y +CONFIG_PCIE_MEDIATEK=y +CONFIG_PCIE_PME=y +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_DOMAINS_GENERIC=y +CONFIG_PCI_MSI=y +CONFIG_PCI_MSI_IRQ_DOMAIN=y +CONFIG_PERF_USE_VMALLOC=y +CONFIG_PGTABLE_LEVELS=2 +CONFIG_PHYLIB=y +CONFIG_PINCTRL=y +CONFIG_PM=y +CONFIG_PM_CLK=y +CONFIG_PTP_1588_CLOCK_OPTIONAL=y +CONFIG_PWM=y +CONFIG_PWM_SYSFS=y +CONFIG_RAS=y +CONFIG_RATIONAL=y +CONFIG_REGMAP=y +CONFIG_REGMAP_MMIO=y +CONFIG_RESET_CONTROLLER=y +CONFIG_RFS_ACCEL=y +CONFIG_RPS=y +CONFIG_RWSEM_SPIN_ON_OWNER=y +CONFIG_SCSI=y +CONFIG_SCSI_COMMON=y +CONFIG_SERIAL_8250_EXTENDED=y +CONFIG_SERIAL_8250_FSL=y +# CONFIG_SERIAL_8250_SHARE_IRQ is not set +CONFIG_SERIAL_MCTRL_GPIO=y +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SGL_ALLOC=y +CONFIG_SG_POOL=y +CONFIG_SMP=y +CONFIG_SMP_ON_UP=y +CONFIG_SOCK_RX_QUEUE_MAPPING=y +CONFIG_SPARSE_IRQ=y +CONFIG_SPI=y +CONFIG_SPI_AIROHA_EN7523=y +CONFIG_SPI_MASTER=y +CONFIG_SPI_MEM=y +CONFIG_SRCU=y +CONFIG_STACKTRACE=y +# CONFIG_SWAP is not set +CONFIG_SWPHY=y +CONFIG_SWP_EMULATE=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_TIMER_OF=y +CONFIG_TIMER_PROBE=y +CONFIG_TREE_RCU=y +CONFIG_TREE_SRCU=y +CONFIG_UBIFS_FS=y +CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" +CONFIG_UNWINDER_ARM=y +CONFIG_USB=y +CONFIG_USB_COMMON=y +CONFIG_USB_SUPPORT=y +CONFIG_USB_XHCI_HCD=y +# CONFIG_USB_XHCI_PLATFORM is not set +CONFIG_USE_OF=y +# CONFIG_VFP is not set +CONFIG_WATCHDOG_CORE=y +# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set +CONFIG_XPS=y +CONFIG_XXHASH=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_BCJ=y +CONFIG_ZBOOT_ROM_BSS=0 +CONFIG_ZBOOT_ROM_TEXT=0 +CONFIG_ZLIB_DEFLATE=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZSTD_COMPRESS=y +CONFIG_ZSTD_DECOMPRESS=y diff --git a/target/linux/airoha/patches-6.1/0001-add-airoha-platform.patch b/target/linux/airoha/patches-6.1/0001-add-airoha-platform.patch new file mode 100644 index 0000000000..5b356ea23e --- /dev/null +++ b/target/linux/airoha/patches-6.1/0001-add-airoha-platform.patch @@ -0,0 +1,31 @@ +--- a/arch/arm/Kconfig ++++ b/arch/arm/Kconfig +@@ -572,6 +572,18 @@ config ARCH_VIRT + select HAVE_ARM_ARCH_TIMER + select ARCH_SUPPORTS_BIG_ENDIAN + ++config ARCH_AIROHA ++ bool "Airoha SoC Support" ++ depends on ARCH_MULTI_V7 ++ select ARM_AMBA ++ select ARM_GIC ++ select ARM_GIC_V3 ++ select ARM_PSCI ++ select HAVE_ARM_ARCH_TIMER ++ select COMMON_CLK ++ help ++ Support for Airoha EN7523 SoCs ++ + # + # This is sorted alphabetically by mach-* pathname. However, plat-* + # Kconfigs may be included either alphabetically (according to the +--- a/arch/arm/Makefile ++++ b/arch/arm/Makefile +@@ -156,6 +156,7 @@ textofs-$(CONFIG_ARCH_AXXIA) := 0x003080 + # Machine directory name. This list is sorted alphanumerically + # by CONFIG_* macro name. + machine-$(CONFIG_ARCH_ACTIONS) += actions ++machine-$(CONFIG_ARCH_AIROHA) += airoha + machine-$(CONFIG_ARCH_ALPINE) += alpine + machine-$(CONFIG_ARCH_ARTPEC) += artpec + machine-$(CONFIG_ARCH_ASPEED) += aspeed diff --git a/target/linux/airoha/patches-6.1/0002-add-airoha-en7523-clk-driver.patch b/target/linux/airoha/patches-6.1/0002-add-airoha-en7523-clk-driver.patch new file mode 100644 index 0000000000..bae5cacc5e --- /dev/null +++ b/target/linux/airoha/patches-6.1/0002-add-airoha-en7523-clk-driver.patch @@ -0,0 +1,28 @@ +--- a/drivers/clk/Kconfig ++++ b/drivers/clk/Kconfig +@@ -192,6 +192,15 @@ config COMMON_CLK_CS2000_CP + help + If you say yes here you get support for the CS2000 clock multiplier. + ++config COMMON_CLK_EN7523 ++ bool "Clock driver for Airoha EN7523 SoC system clocks" ++ depends on OF ++ depends on ARCH_AIROHA || COMPILE_TEST ++ default ARCH_AIROHA ++ help ++ This driver provides the fixed clocks and gates present on Airoha ++ ARM silicon. ++ + config COMMON_CLK_FSL_FLEXSPI + tristate "Clock driver for FlexSPI on Layerscape SoCs" + depends on ARCH_LAYERSCAPE || COMPILE_TEST +--- a/drivers/clk/Makefile ++++ b/drivers/clk/Makefile +@@ -27,6 +27,7 @@ obj-$(CONFIG_COMMON_CLK_CDCE925) += clk- + obj-$(CONFIG_ARCH_CLPS711X) += clk-clps711x.o + obj-$(CONFIG_COMMON_CLK_CS2000_CP) += clk-cs2000-cp.o + obj-$(CONFIG_ARCH_SPARX5) += clk-sparx5.o ++obj-$(CONFIG_COMMON_CLK_EN7523) += clk-en7523.o + obj-$(CONFIG_COMMON_CLK_FIXED_MMIO) += clk-fixed-mmio.o + obj-$(CONFIG_COMMON_CLK_FSL_FLEXSPI) += clk-fsl-flexspi.o + obj-$(CONFIG_COMMON_CLK_FSL_SAI) += clk-fsl-sai.o diff --git a/target/linux/airoha/patches-6.1/0003-add-airoha-en7523-gpio-driver.patch b/target/linux/airoha/patches-6.1/0003-add-airoha-en7523-gpio-driver.patch new file mode 100644 index 0000000000..319336257b --- /dev/null +++ b/target/linux/airoha/patches-6.1/0003-add-airoha-en7523-gpio-driver.patch @@ -0,0 +1,29 @@ +--- a/drivers/gpio/Kconfig ++++ b/drivers/gpio/Kconfig +@@ -247,6 +247,16 @@ config GPIO_EM + help + Say yes here to support GPIO on Renesas Emma Mobile SoCs. + ++config GPIO_EN7523 ++ tristate "Airoha GPIO support" ++ depends on ARCH_AIROHA ++ default ARCH_AIROHA ++ select GPIO_GENERIC ++ select GPIOLIB_IRQCHIP ++ help ++ Say Y or M here to support the GPIO controller block on the ++ Airoha EN7523 SoC. It supports two banks of 32 GPIOs. ++ + config GPIO_EP93XX + def_bool y + depends on ARCH_EP93XX +--- a/drivers/gpio/Makefile ++++ b/drivers/gpio/Makefile +@@ -57,6 +57,7 @@ obj-$(CONFIG_GPIO_DLN2) += gpio-dln2.o + obj-$(CONFIG_GPIO_DWAPB) += gpio-dwapb.o + obj-$(CONFIG_GPIO_EIC_SPRD) += gpio-eic-sprd.o + obj-$(CONFIG_GPIO_EM) += gpio-em.o ++obj-$(CONFIG_GPIO_EN7523) += gpio-en7523.o + obj-$(CONFIG_GPIO_EP93XX) += gpio-ep93xx.o + obj-$(CONFIG_GPIO_EXAR) += gpio-exar.o + obj-$(CONFIG_GPIO_F7188X) += gpio-f7188x.o diff --git a/target/linux/airoha/patches-6.1/0004-ARM-9124-1-uncompress-Parse-linux-usable-memory-rang.patch b/target/linux/airoha/patches-6.1/0004-ARM-9124-1-uncompress-Parse-linux-usable-memory-rang.patch new file mode 100644 index 0000000000..0f0cbaa10f --- /dev/null +++ b/target/linux/airoha/patches-6.1/0004-ARM-9124-1-uncompress-Parse-linux-usable-memory-rang.patch @@ -0,0 +1,107 @@ +From 48342ae751c797ac73ac9c894b3f312df18ffd21 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven +Date: Wed, 15 Sep 2021 13:46:20 +0100 +Subject: [PATCH] ARM: 9124/1: uncompress: Parse "linux,usable-memory-range" DT + property + +Add support for parsing the "linux,usable-memory-range" DT property. +This property is used to describe the usable memory reserved for the +crash dump kernel, and thus makes the memory reservation explicit. +If present, Linux no longer needs to mask the program counter, and rely +on the "mem=" kernel parameter to obtain the start and size of usable +memory. + +For backwards compatibility, the traditional method to derive the start +of memory is still used if "linux,usable-memory-range" is absent. + +Signed-off-by: Geert Uytterhoeven +Signed-off-by: Russell King (Oracle) +Signed-off-by: Daniel Danzberger +--- + .../arm/boot/compressed/fdt_check_mem_start.c | 48 ++++++++++++++++--- + 1 file changed, 42 insertions(+), 6 deletions(-) + +--- a/arch/arm/boot/compressed/fdt_check_mem_start.c ++++ b/arch/arm/boot/compressed/fdt_check_mem_start.c +@@ -55,16 +55,17 @@ static uint64_t get_val(const fdt32_t *c + * DTB, and, if out-of-range, replace it by the real start address. + * To preserve backwards compatibility (systems reserving a block of memory + * at the start of physical memory, kdump, ...), the traditional method is +- * always used if it yields a valid address. ++ * used if it yields a valid address, unless the "linux,usable-memory-range" ++ * property is present. + * + * Return value: start address of physical memory to use + */ + uint32_t fdt_check_mem_start(uint32_t mem_start, const void *fdt) + { +- uint32_t addr_cells, size_cells, base; ++ uint32_t addr_cells, size_cells, usable_base, base; + uint32_t fdt_mem_start = 0xffffffff; +- const fdt32_t *reg, *endp; +- uint64_t size, end; ++ const fdt32_t *usable, *reg, *endp; ++ uint64_t size, usable_end, end; + const char *type; + int offset, len; + +@@ -80,6 +81,27 @@ uint32_t fdt_check_mem_start(uint32_t me + if (addr_cells > 2 || size_cells > 2) + return mem_start; + ++ /* ++ * Usable memory in case of a crash dump kernel ++ * This property describes a limitation: memory within this range is ++ * only valid when also described through another mechanism ++ */ ++ usable = get_prop(fdt, "/chosen", "linux,usable-memory-range", ++ (addr_cells + size_cells) * sizeof(fdt32_t)); ++ if (usable) { ++ size = get_val(usable + addr_cells, size_cells); ++ if (!size) ++ return mem_start; ++ ++ if (addr_cells > 1 && fdt32_ld(usable)) { ++ /* Outside 32-bit address space */ ++ return mem_start; ++ } ++ ++ usable_base = fdt32_ld(usable + addr_cells - 1); ++ usable_end = usable_base + size; ++ } ++ + /* Walk all memory nodes and regions */ + for (offset = fdt_next_node(fdt, -1, NULL); offset >= 0; + offset = fdt_next_node(fdt, offset, NULL)) { +@@ -107,7 +129,20 @@ uint32_t fdt_check_mem_start(uint32_t me + + base = fdt32_ld(reg + addr_cells - 1); + end = base + size; +- if (mem_start >= base && mem_start < end) { ++ if (usable) { ++ /* ++ * Clip to usable range, which takes precedence ++ * over mem_start ++ */ ++ if (base < usable_base) ++ base = usable_base; ++ ++ if (end > usable_end) ++ end = usable_end; ++ ++ if (end <= base) ++ continue; ++ } else if (mem_start >= base && mem_start < end) { + /* Calculated address is valid, use it */ + return mem_start; + } +@@ -123,7 +158,8 @@ uint32_t fdt_check_mem_start(uint32_t me + } + + /* +- * The calculated address is not usable. ++ * The calculated address is not usable, or was overridden by the ++ * "linux,usable-memory-range" property. + * Use the lowest usable physical memory address from the DTB instead, + * and make sure this is a multiple of 2 MiB for phys/virt patching. + */ diff --git a/target/linux/airoha/patches-6.1/0005-spi-Add-support-for-the-Airoha-EN7523-SoC-SPI-contro.patch b/target/linux/airoha/patches-6.1/0005-spi-Add-support-for-the-Airoha-EN7523-SoC-SPI-contro.patch new file mode 100644 index 0000000000..6c21666ed1 --- /dev/null +++ b/target/linux/airoha/patches-6.1/0005-spi-Add-support-for-the-Airoha-EN7523-SoC-SPI-contro.patch @@ -0,0 +1,341 @@ +--- a/drivers/spi/Kconfig ++++ b/drivers/spi/Kconfig +@@ -307,6 +307,12 @@ config SPI_DLN2 + This driver can also be built as a module. If so, the module + will be called spi-dln2. + ++config SPI_AIROHA_EN7523 ++ bool "Airoha EN7523 SPI controller support" ++ depends on ARCH_AIROHA ++ help ++ This enables SPI controller support for the Airoha EN7523 SoC. ++ + config SPI_EP93XX + tristate "Cirrus Logic EP93xx SPI controller" + depends on ARCH_EP93XX || COMPILE_TEST +--- a/drivers/spi/Makefile ++++ b/drivers/spi/Makefile +@@ -45,6 +45,7 @@ obj-$(CONFIG_SPI_DW_BT1) += spi-dw-bt1. + obj-$(CONFIG_SPI_DW_MMIO) += spi-dw-mmio.o + obj-$(CONFIG_SPI_DW_PCI) += spi-dw-pci.o + obj-$(CONFIG_SPI_EP93XX) += spi-ep93xx.o ++obj-$(CONFIG_SPI_AIROHA_EN7523) += spi-en7523.o + obj-$(CONFIG_SPI_FALCON) += spi-falcon.o + obj-$(CONFIG_SPI_FSI) += spi-fsi.o + obj-$(CONFIG_SPI_FSL_CPM) += spi-fsl-cpm.o +--- /dev/null ++++ b/drivers/spi/spi-en7523.c +@@ -0,0 +1,313 @@ ++// SPDX-License-Identifier: GPL-2.0 ++ ++#include ++#include ++#include ++#include ++ ++ ++#define ENSPI_READ_IDLE_EN 0x0004 ++#define ENSPI_MTX_MODE_TOG 0x0014 ++#define ENSPI_RDCTL_FSM 0x0018 ++#define ENSPI_MANUAL_EN 0x0020 ++#define ENSPI_MANUAL_OPFIFO_EMPTY 0x0024 ++#define ENSPI_MANUAL_OPFIFO_WDATA 0x0028 ++#define ENSPI_MANUAL_OPFIFO_FULL 0x002C ++#define ENSPI_MANUAL_OPFIFO_WR 0x0030 ++#define ENSPI_MANUAL_DFIFO_FULL 0x0034 ++#define ENSPI_MANUAL_DFIFO_WDATA 0x0038 ++#define ENSPI_MANUAL_DFIFO_EMPTY 0x003C ++#define ENSPI_MANUAL_DFIFO_RD 0x0040 ++#define ENSPI_MANUAL_DFIFO_RDATA 0x0044 ++#define ENSPI_IER 0x0090 ++#define ENSPI_NFI2SPI_EN 0x0130 ++ ++// TODO not in spi block ++#define ENSPI_CLOCK_DIVIDER ((void __iomem *)0x1fa201c4) ++ ++#define OP_CSH 0x00 ++#define OP_CSL 0x01 ++#define OP_CK 0x02 ++#define OP_OUTS 0x08 ++#define OP_OUTD 0x09 ++#define OP_OUTQ 0x0A ++#define OP_INS 0x0C ++#define OP_INS0 0x0D ++#define OP_IND 0x0E ++#define OP_INQ 0x0F ++#define OP_OS2IS 0x10 ++#define OP_OS2ID 0x11 ++#define OP_OS2IQ 0x12 ++#define OP_OD2IS 0x13 ++#define OP_OD2ID 0x14 ++#define OP_OD2IQ 0x15 ++#define OP_OQ2IS 0x16 ++#define OP_OQ2ID 0x17 ++#define OP_OQ2IQ 0x18 ++#define OP_OSNIS 0x19 ++#define OP_ODNID 0x1A ++ ++#define MATRIX_MODE_AUTO 1 ++#define CONF_MTX_MODE_AUTO 0 ++#define MANUALEN_AUTO 0 ++#define MATRIX_MODE_MANUAL 0 ++#define CONF_MTX_MODE_MANUAL 9 ++#define MANUALEN_MANUAL 1 ++ ++#define _ENSPI_MAX_XFER 0x1ff ++ ++#define REG(x) (iobase + x) ++ ++ ++static void __iomem *iobase; ++ ++ ++static void opfifo_write(u32 cmd, u32 len) ++{ ++ u32 tmp = ((cmd & 0x1f) << 9) | (len & 0x1ff); ++ ++ writel(tmp, REG(ENSPI_MANUAL_OPFIFO_WDATA)); ++ ++ /* Wait for room in OPFIFO */ ++ while (readl(REG(ENSPI_MANUAL_OPFIFO_FULL))) ++ ; ++ ++ /* Shift command into OPFIFO */ ++ writel(1, REG(ENSPI_MANUAL_OPFIFO_WR)); ++ ++ /* Wait for command to finish */ ++ while (!readl(REG(ENSPI_MANUAL_OPFIFO_EMPTY))) ++ ; ++} ++ ++static void set_cs(int state) ++{ ++ if (state) ++ opfifo_write(OP_CSH, 1); ++ else ++ opfifo_write(OP_CSL, 1); ++} ++ ++static void manual_begin_cmd(void) ++{ ++ /* Disable read idle state */ ++ writel(0, REG(ENSPI_READ_IDLE_EN)); ++ ++ /* Wait for FSM to reach idle state */ ++ while (readl(REG(ENSPI_RDCTL_FSM))) ++ ; ++ ++ /* Set SPI core to manual mode */ ++ writel(CONF_MTX_MODE_MANUAL, REG(ENSPI_MTX_MODE_TOG)); ++ writel(MANUALEN_MANUAL, REG(ENSPI_MANUAL_EN)); ++} ++ ++static void manual_end_cmd(void) ++{ ++ /* Set SPI core to auto mode */ ++ writel(CONF_MTX_MODE_AUTO, REG(ENSPI_MTX_MODE_TOG)); ++ writel(MANUALEN_AUTO, REG(ENSPI_MANUAL_EN)); ++ ++ /* Enable read idle state */ ++ writel(1, REG(ENSPI_READ_IDLE_EN)); ++} ++ ++static void dfifo_read(u8 *buf, int len) ++{ ++ int i; ++ ++ for (i = 0; i < len; i++) { ++ /* Wait for requested data to show up in DFIFO */ ++ while (readl(REG(ENSPI_MANUAL_DFIFO_EMPTY))) ++ ; ++ buf[i] = readl(REG(ENSPI_MANUAL_DFIFO_RDATA)); ++ /* Queue up next byte */ ++ writel(1, REG(ENSPI_MANUAL_DFIFO_RD)); ++ } ++} ++ ++static void dfifo_write(const u8 *buf, int len) ++{ ++ int i; ++ ++ for (i = 0; i < len; i++) { ++ /* Wait for room in DFIFO */ ++ while (readl(REG(ENSPI_MANUAL_DFIFO_FULL))) ++ ; ++ writel(buf[i], REG(ENSPI_MANUAL_DFIFO_WDATA)); ++ } ++} ++ ++#if 0 ++static void set_spi_clock_speed(int freq_mhz) ++{ ++ u32 tmp, val; ++ ++ tmp = readl(ENSPI_CLOCK_DIVIDER); ++ tmp &= 0xffff0000; ++ writel(tmp, ENSPI_CLOCK_DIVIDER); ++ ++ val = (400 / (freq_mhz * 2)); ++ tmp |= (val << 8) | 1; ++ writel(tmp, ENSPI_CLOCK_DIVIDER); ++} ++#endif ++ ++static void init_hw(void) ++{ ++ /* Disable manual/auto mode clash interrupt */ ++ writel(0, REG(ENSPI_IER)); ++ ++ // TODO via clk framework ++ // set_spi_clock_speed(50); ++ ++ /* Disable DMA */ ++ writel(0, REG(ENSPI_NFI2SPI_EN)); ++} ++ ++static int xfer_read(struct spi_transfer *xfer) ++{ ++ int opcode; ++ uint8_t *buf = xfer->rx_buf; ++ ++ switch (xfer->rx_nbits) { ++ case SPI_NBITS_SINGLE: ++ opcode = OP_INS; ++ break; ++ case SPI_NBITS_DUAL: ++ opcode = OP_IND; ++ break; ++ case SPI_NBITS_QUAD: ++ opcode = OP_INQ; ++ break; ++ } ++ ++ opfifo_write(opcode, xfer->len); ++ dfifo_read(buf, xfer->len); ++ ++ return xfer->len; ++} ++ ++static int xfer_write(struct spi_transfer *xfer, int next_xfer_is_rx) ++{ ++ int opcode; ++ const uint8_t *buf = xfer->tx_buf; ++ ++ if (next_xfer_is_rx) { ++ /* need to use Ox2Ix opcode to set the core to input afterwards */ ++ switch (xfer->tx_nbits) { ++ case SPI_NBITS_SINGLE: ++ opcode = OP_OS2IS; ++ break; ++ case SPI_NBITS_DUAL: ++ opcode = OP_OS2ID; ++ break; ++ case SPI_NBITS_QUAD: ++ opcode = OP_OS2IQ; ++ break; ++ } ++ } else { ++ switch (xfer->tx_nbits) { ++ case SPI_NBITS_SINGLE: ++ opcode = OP_OUTS; ++ break; ++ case SPI_NBITS_DUAL: ++ opcode = OP_OUTD; ++ break; ++ case SPI_NBITS_QUAD: ++ opcode = OP_OUTQ; ++ break; ++ } ++ } ++ ++ opfifo_write(opcode, xfer->len); ++ dfifo_write(buf, xfer->len); ++ ++ return xfer->len; ++} ++ ++size_t max_transfer_size(struct spi_device *spi) ++{ ++ return _ENSPI_MAX_XFER; ++} ++ ++int transfer_one_message(struct spi_controller *ctrl, struct spi_message *msg) ++{ ++ struct spi_transfer *xfer; ++ int next_xfer_is_rx = 0; ++ ++ manual_begin_cmd(); ++ set_cs(0); ++ list_for_each_entry(xfer, &msg->transfers, transfer_list) { ++ if (xfer->tx_buf) { ++ if (!list_is_last(&xfer->transfer_list, &msg->transfers) ++ && list_next_entry(xfer, transfer_list)->rx_buf != NULL) ++ next_xfer_is_rx = 1; ++ else ++ next_xfer_is_rx = 0; ++ msg->actual_length += xfer_write(xfer, next_xfer_is_rx); ++ } else if (xfer->rx_buf) { ++ msg->actual_length += xfer_read(xfer); ++ } ++ } ++ set_cs(1); ++ manual_end_cmd(); ++ ++ msg->status = 0; ++ spi_finalize_current_message(ctrl); ++ ++ return 0; ++} ++ ++static int spi_probe(struct platform_device *pdev) ++{ ++ struct spi_controller *ctrl; ++ int err; ++ ++ ctrl = devm_spi_alloc_master(&pdev->dev, 0); ++ if (!ctrl) { ++ dev_err(&pdev->dev, "Error allocating SPI controller\n"); ++ return -ENOMEM; ++ } ++ ++ iobase = devm_platform_get_and_ioremap_resource(pdev, 0, NULL); ++ if (IS_ERR(iobase)) { ++ dev_err(&pdev->dev, "Could not map SPI register address"); ++ return -ENOMEM; ++ } ++ ++ init_hw(); ++ ++ ctrl->dev.of_node = pdev->dev.of_node; ++ ctrl->flags = SPI_CONTROLLER_HALF_DUPLEX; ++ ctrl->mode_bits = SPI_RX_DUAL | SPI_TX_DUAL; ++ ctrl->max_transfer_size = max_transfer_size; ++ ctrl->transfer_one_message = transfer_one_message; ++ err = devm_spi_register_controller(&pdev->dev, ctrl); ++ if (err) { ++ dev_err(&pdev->dev, "Could not register SPI controller\n"); ++ return -ENODEV; ++ } ++ ++ return 0; ++} ++ ++static const struct of_device_id spi_of_ids[] = { ++ { .compatible = "airoha,en7523-spi" }, ++ { /* sentinel */ } ++}; ++MODULE_DEVICE_TABLE(of, spi_of_ids); ++ ++static struct platform_driver spi_driver = { ++ .probe = spi_probe, ++ .driver = { ++ .name = "airoha-en7523-spi", ++ .of_match_table = spi_of_ids, ++ }, ++}; ++ ++module_platform_driver(spi_driver); ++ ++MODULE_LICENSE("GPL v2"); ++MODULE_AUTHOR("Bert Vermeulen "); ++MODULE_DESCRIPTION("Airoha EN7523 SPI driver"); diff --git a/target/linux/airoha/patches-6.1/0006-PCI-mediatek-Allow-building-for-ARCH_AIROHA.patch b/target/linux/airoha/patches-6.1/0006-PCI-mediatek-Allow-building-for-ARCH_AIROHA.patch new file mode 100644 index 0000000000..4659809074 --- /dev/null +++ b/target/linux/airoha/patches-6.1/0006-PCI-mediatek-Allow-building-for-ARCH_AIROHA.patch @@ -0,0 +1,31 @@ +From b3b76fc86f0fb4d98918f48c784138bfa950dff6 Mon Sep 17 00:00:00 2001 +From: Felix Fietkau +Date: Wed, 15 Jun 2022 14:53:34 +0200 +Subject: [PATCH] PCI: mediatek: Allow building for ARCH_AIROHA + +Allow selecting the pcie-mediatek driver if ARCH_AIROHA is set, because the +Airoha EN7523 SoC uses the same controller as MT7622. + +The driver itself is not modified. The PCIe controller DT node should use +mediatek,mt7622-pcie after airoha,en7523-pcie. + +Link: https://lore.kernel.org/r/20220615125335.96089-2-nbd@nbd.name +Signed-off-by: Felix Fietkau +Signed-off-by: Bjorn Helgaas +Acked-by: Lorenzo Pieralisi +Signed-off-by: Daniel Danzberger +--- + drivers/pci/controller/Kconfig | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/pci/controller/Kconfig ++++ b/drivers/pci/controller/Kconfig +@@ -233,7 +233,7 @@ config PCIE_ROCKCHIP_EP + + config PCIE_MEDIATEK + tristate "MediaTek PCIe controller" +- depends on ARCH_MEDIATEK || COMPILE_TEST ++ depends on ARCH_AIROHA || ARCH_MEDIATEK || COMPILE_TEST + depends on OF + depends on PCI_MSI_IRQ_DOMAIN + help