From: Marek Vasut <marex@denx.de>
Date: Mon, 13 Aug 2018 16:42:39 +0000 (+0200)
Subject: ARM: dts: socfpga: Add missing UART resets
X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=f5775e69cc201da6998dd992a93c1696e087d39a;p=project%2Fbcm63xx%2Fu-boot.git

ARM: dts: socfpga: Add missing UART resets

The UART0 and UART1 resets are missing from DT, so the reset manager
cannot control them. Add the missing DT reset entries.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
---

diff --git a/arch/arm/dts/socfpga_arria10.dtsi b/arch/arm/dts/socfpga_arria10.dtsi
index 51b31dc2b5..aafcfe9ce4 100644
--- a/arch/arm/dts/socfpga_arria10.dtsi
+++ b/arch/arm/dts/socfpga_arria10.dtsi
@@ -797,6 +797,7 @@
 			reg-shift = <2>;
 			reg-io-width = <4>;
 			clocks = <&l4_sp_clk>;
+			resets = <&rst UART0_RESET>;
 			status = "disabled";
 		};
 
@@ -807,6 +808,7 @@
 			reg-shift = <2>;
 			reg-io-width = <4>;
 			clocks = <&l4_sp_clk>;
+			resets = <&rst UART1_RESET>;
 			status = "disabled";
 		};