From: Mark Brown <broonie@linaro.org>
Date: Mon, 17 Jun 2013 16:20:32 +0000 (+0100)
Subject: Merge remote-tracking branch 'asoc/topic/wm8962' into asoc-next
X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=f57019aa0a796251e671882004dd58d2cc55f8f1;p=openwrt%2Fstaging%2Fblogic.git

Merge remote-tracking branch 'asoc/topic/wm8962' into asoc-next
---

f57019aa0a796251e671882004dd58d2cc55f8f1
diff --cc sound/soc/codecs/wm8962.c
index 4b7915bec2f1,dfaf592d2fc9..b1dc7d426438
--- a/sound/soc/codecs/wm8962.c
+++ b/sound/soc/codecs/wm8962.c
@@@ -3721,19 -3758,23 +3758,34 @@@ static int wm8962_runtime_resume(struc
  
  	wm8962_reset(wm8962);
  
+ 	/* SYSCLK defaults to on; make sure it is off so we can safely
+ 	 * write to registers if the device is declocked.
+ 	 */
+ 	regmap_update_bits(wm8962->regmap, WM8962_CLOCKING2,
+ 			   WM8962_SYSCLK_ENA, 0);
+ 
+ 	/* Ensure we have soft control over all registers */
+ 	regmap_update_bits(wm8962->regmap, WM8962_CLOCKING2,
+ 			   WM8962_CLKREG_OVD, WM8962_CLKREG_OVD);
+ 
+ 	/* Ensure that the oscillator and PLLs are disabled */
+ 	regmap_update_bits(wm8962->regmap, WM8962_PLL2,
+ 			   WM8962_OSC_ENA | WM8962_PLL2_ENA | WM8962_PLL3_ENA,
+ 			   0);
+ 
  	regcache_sync(wm8962->regmap);
  
 +	regmap_update_bits(wm8962->regmap, WM8962_ANTI_POP,
 +			   WM8962_STARTUP_BIAS_ENA | WM8962_VMID_BUF_ENA,
 +			   WM8962_STARTUP_BIAS_ENA | WM8962_VMID_BUF_ENA);
 +
 +	/* Bias enable at 2*5k (fast start-up) */
 +	regmap_update_bits(wm8962->regmap, WM8962_PWR_MGMT_1,
 +			   WM8962_BIAS_ENA | WM8962_VMID_SEL_MASK,
 +			   WM8962_BIAS_ENA | 0x180);
 +
 +	msleep(5);
 +
  	return 0;
  }