From: Harry Wentland Date: Mon, 23 Jan 2017 16:49:24 +0000 (-0500) Subject: drm/amd/display: Don't reserve pipe for underlay on ASIC without underlay X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=f0e3db90a6fbee4acc921a4912a3e3460efb5cc0;p=openwrt%2Fstaging%2Fblogic.git drm/amd/display: Don't reserve pipe for underlay on ASIC without underlay Signed-off-by: Harry Wentland Acked-by: Jordan Lazare Reviewed-by: Tony Cheng Signed-off-by: Alex Deucher --- diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index f9b7fc85d71a..270f8c5cfeda 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -621,7 +621,7 @@ struct dc *dc_create(const struct dc_init_data *init_params) core_dc->hwss.init_hw(core_dc); full_pipe_count = core_dc->res_pool->pipe_count; - if (core_dc->res_pool->underlay_pipe_index >= 0) + if (core_dc->res_pool->underlay_pipe_index != NO_UNDERLAY_PIPE) full_pipe_count--; core_dc->public.caps.max_streams = min( full_pipe_count, diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c index ae0e7eac2c9d..dc4f270ae44a 100644 --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c @@ -934,7 +934,7 @@ static bool construct( pool->base.res_cap = &res_cap; pool->base.funcs = &dce100_res_pool_funcs; - pool->base.underlay_pipe_index = -1; + pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; bp = ctx->dc_bios; @@ -1004,7 +1004,7 @@ static bool construct( /************************************************* * Resource + asic cap harcoding * *************************************************/ - pool->base.underlay_pipe_index = -1; + pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; pool->base.pipe_count = res_cap.num_timing_generator; dc->public.caps.max_downscale_ratio = 200; dc->public.caps.i2c_speed_in_khz = 40; diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c index 64fae91dd5eb..fa8699d3b9ef 100644 --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c @@ -1243,7 +1243,7 @@ static bool construct( /************************************************* * Resource + asic cap harcoding * *************************************************/ - pool->base.underlay_pipe_index = -1; + pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; pool->base.pipe_count = pool->base.res_cap->num_timing_generator; dc->public.caps.max_downscale_ratio = 200; dc->public.caps.i2c_speed_in_khz = 100; diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c index bee3a41ffe9f..fea60aa5d297 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c @@ -931,7 +931,7 @@ static bool construct( /************************************************* * Resource + asic cap harcoding * *************************************************/ - pool->base.underlay_pipe_index = -1; + pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; pool->base.pipe_count = res_cap.num_timing_generator; dc->public.caps.max_downscale_ratio = 200; dc->public.caps.i2c_speed_in_khz = 40; diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h index 66bfcdb57c4c..b349b5768b6e 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -230,6 +230,8 @@ struct audio_support{ bool hdmi_audio_native; }; +#define NO_UNDERLAY_PIPE -1 + struct resource_pool { struct mem_input *mis[MAX_PIPES]; struct input_pixel_processor *ipps[MAX_PIPES];